JP3372556B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to an EPROM (erasable programmable read only memory), EE
The present invention relates to a semiconductor integrated circuit including a memory such as a PROM (electrically erasable and programmable read only memory) that requires a boosted high voltage, and more particularly to a charge pump circuit for obtaining a boosted voltage.

[0002]

2. Description of the Related Art A memory cell having a channel injection structure for an EPROM having a control gate and a floating gate is written by applying a high voltage between the control gate and the drain. Further, MNOS (metal nitride oxide semiconductor or metal nitride oxide silicon) for an EEPROM configuration having a polysilicon film and a silicon nitride film at the gate is oxidized by applying a high voltage to the gate. Writing is performed by injecting electrons by the tunnel effect into the trap near the interface between the silicon film and the silicon nitride film, and erasing by injecting holes into the trap by applying an electric field opposite to the writing. Is done. In addition, a FLOTOX (floating gate tunnel oxide) type memory cell for EEPROM configuration has a tunnel oxide film of about 100Å to 200Å formed on the upper part of the drain, and electrons are formed between the floating gate and the drain through the tunnel oxide film. Writing or erasing is performed by injecting or discharging. In this way, a high voltage is required when writing to the memory cells of the EPROM or EEPROM.

For example, since the FLOTOX type memory cell has a weak tunnel current, an internal booster circuit to which a charge pump circuit is applied is usually used as a write power supply.
For example, this charge pump circuit includes a circuit in which a plurality of diode-connected MOS transistors are connected in series, and has a plurality of capacitive elements in which one storage electrode is connected to these diode-connected MOS transistors and is connected in series. A power supply voltage such as 5V is applied to the diode connection type MOS transistor on the base end side, and a signal with a phase shift is sequentially applied to the other storage electrode of the capacitative element to sequentially charge the capacitative element and the diode on the terminal side. A boosted voltage such as 15 to 20 V is obtained from the connection type MOS transistor.

The gate oxide film thickness of the diode connection type MOS transistor and the capacitor element used in the conventional charge pump circuit is one type and is relatively thick. FLO with control gate and floating gate
When the polysilicon two-layer process is adopted by utilizing the TOX type memory cell, the diode connection type MOS transistor and the MOS type capacitive element are arranged in the first-layer polysilicon gate or the second-layer polysilicon gate. It is composed of a polysilicon gate having a relatively thick gate oxide film thickness. It is considered that this is because the withstand voltage of the charge pump circuit constituent element that boosts the power supply voltage is taken into consideration.

Incidentally, as an example of the document describing the charge pump circuit applied to the EEPROM, it is shown in 1987.
There is "CMOS device handbook", page 447, published by Nikkan Kogyo Shimbun on September 29, 2014.

[0006]

However, the MOS
When the impurity concentration of the semiconductor substrate is increased as the transistor is scaled, the threshold voltage of the MOS transistor increases due to the substrate effect, and the N-channel type M
Reduction of source potential with respect to drain potential of OS transistor, that is, Vth (threshold voltage) of MOS transistor
The present inventor has found that there is a problem that the drop becomes large and the boosting by the charge pump circuit becomes insufficient, and it is difficult to efficiently obtain a high voltage. If the well concentration is divided and the charge pump circuit is formed in the well region on the relatively low concentration side as a countermeasure, the number of manufacturing steps increases with the division of the well concentration, and the process cost increases. Therefore, in the case of an EEPROM that is on-chip in a one-chip microcomputer, the process cost of the entire chip is increased even though the ratio of the allowable cost to the entire chip must be kept relatively small. I will end up.

An object of the present invention is to provide a semiconductor integrated circuit capable of improving the boosting efficiency by the built-in charge pump circuit even if the impurity concentration of the semiconductor substrate or the well region is increased due to the scaling of the MIS type transistor. It is in. Another object of the present invention is to provide a semiconductor integrated circuit capable of reducing the chip occupation area of the charge pump circuit. Still another object of the present invention is to provide a semiconductor integrated circuit that can achieve the above object without adding a special process such as division of well concentration.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, one or a plurality of MIS type transistors located at the base end side of the diode connection type MIS type transistor included in the charge pump circuit for EPROM or EEPROM are provided in the first layer and the second layer. A first or a plurality of MIS type transistors which are formed by a gate having a relatively thin gate insulating film in the eye gate and are located on the terminal side of the diode-connected type MIS type transistors connected in series; A gate having a relatively thick gate insulating film among the second and second layer gates is used.

A single or a plurality of capacitive elements located at the base end side of a diode-connected MIS type transistor connected in series included in a charge pump circuit for an EPROM or an EEPROM are provided in the first and second layers. A relatively thin gate insulating film in the gate is formed as a dielectric film, and a single or a plurality of capacitive elements located on the terminal side of the diode-connected MIS type transistors connected in series are referred to as a first layer. A relatively thick gate insulating film in the second layer gate is formed as a dielectric film.

[0012]

According to the above means, the Vth drop due to the substrate bias effect becomes smaller as the gate insulating film becomes thinner. In the charge pump circuit, the diode-connected MIS transistor on the front stage side to which a relatively high voltage is not applied is formed of a relatively thin gate insulating film to reduce the Vth drop due to the substrate bias effect of the transistor, and thus the charge pump circuit. Improve boosting efficiency.

In the charge pump circuit, if the dielectric film of the capacitance element on the front stage side to which a relatively high voltage is not applied is made of a relatively thin gate insulating film, the capacitance value per unit area becomes large, and the charge pump The chip occupation area of the entire circuit is reduced.

The relatively thick gate oxide film and dielectric film of the diode-connected MIS type transistor and the capacitive element after the charge pump circuit guarantee the withstand voltage against the boosted voltage.

Control of the film thickness of the gate insulating film of the diode type MIS type transistor and the capacitive element forming the charge pump circuit includes the first layer gate and the second layer gate in which the thickness of the gate insulating film is different. The existing process of the semiconductor integrated circuit in which a large number of MIS transistors are formed does not require addition of a special process such as well concentration division in order to make the boosting operation efficient.

[0016]

FIG. 3 shows an EEPRO according to an embodiment of the present invention.
A block diagram of M is shown. EEPRO shown in the figure
Although not particularly limited, M100 is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique. In the description of this specification, a MOS transistor is positioned as an example of a MIS (metal insulator semiconductor) type transistor.
In the figure, reference numeral 110 denotes a memory cell array in which a plurality of electrically rewritable non-volatile memory cells MC, which are typically shown, are arranged in a matrix. According to this embodiment, the memory cell MC includes the FLOTOX type transistor Qf.
And a selection MOS transistor Qs are connected in series. The control gate of the transistor Qf is coupled to the representative control line CL, and the source of the transistor Qf is representatively the source line SL.
And the gate of the selection MOS transistor Qs (selection terminal of the memory cell) is a representative word line WL.
And the drain of the select MOS transistor Qs is coupled to the representatively shown bit line BL. The selection terminal of the memory cell included in the memory cell array 110 is selected for each row by the output selection signal of the X selection address decoder 111. The memory cell of the selected predetermined row is
A predetermined one is conducted to the data input buffer 116 and the input data latch circuit 117 via the Y selection gate 113 which is switch-controlled by the output selection signal of the Y selection address decoder 112. An address signal ADRS is supplied to the address buffer 114, and a complementary address signal 115 corresponding thereto is supplied to the Y selection address decoder 112 and the X selection address decoder 111.

The data input / output buffer 116 has 8-bit (1 byte) data input / output terminals D0 to D7, and inputs / outputs data in 1-byte units, although not particularly limited thereto. An input data latch circuit 117 is arranged between the data input / output buffer 116 and the Y selection gate 113. The input data latch circuit 117 temporarily holds write data given from the outside and is not particularly limited, but statically stores 32 bytes of data corresponding to the number of memory cells of one row in the memory cell array 110. It is configured to be latchable to and write data up to 3 can be sequentially given in 1-byte units from the outside.
This is for realizing a so-called page write function in which after latching 2 bytes, this is collectively written in a predetermined row of the memory cell array.

A write / erase circuit 118 provided between the Y select gate 113 and the memory cell array 110.
In the rewriting mode of the EEPROM 100, the memory cell data for one row is saved and erased at the time of the first erase operation, and then part or all of the saved data is input data latch circuit 117.
The data is rewritten by the data supplied from, and the writing operation is performed in a predetermined memory cell according to the rewritten content. The high voltage Vpp required for the rewriting operation is not particularly limited, but is boosted by the high voltage generation circuit 119. Here, erasing of the memory cell MC is performed by applying a high voltage between the control gate and the drain to inject electrons into the floating gate, and writing to the memory cell MC is performed by applying an electric field in the opposite direction. This is done by emitting electrons from the floating gate.

The operation control of the EEPROM 100 is performed by the input / output control unit 120 and the write / erase control unit 121. Both control units 120 and 121 have chip enable signal CE *.
When (* means low enable or inversion) is asserted to a low level, it is activated and becomes operable, and in this state, the input / output control unit 120 outputs the data according to the instruction of the output enable signal OE *. Input / output control of data to / from the input / output buffer 116 is performed.
The output enable signal OE * indicates the output of data at a low level and the input of data at a high level. The write / erase control unit 121
In the operable state, the memory cell data read control and the memory cell rewrite control are performed according to the instruction of the write enable signal WE *. The write enable signal WE * indicates a rewrite operation at a low level and a read operation of memory cell data at a high level.

FIG. 2 shows an example of the high voltage generating circuit 119. The high voltage generation circuit 119 is composed of a charge pump circuit 130 and a voltage limiter 131, although not particularly limited. Charge pump circuit 13
0 is provided with diode-connected MOS transistors Qc0 to Qcn connected in series in which the drain is connected to the gate, and one storage electrode of each of the capacitance elements C1 to Cn is sequentially connected to the coupling node of each MOS transistor, The clock signal φ is supplied to the other storage electrodes of the elements C1, C3, ..., Cn-1 and the clock signal φ * is supplied to the other storage electrodes of the capacitive elements C2, C4, ..., Cn. A power supply voltage Vdd such as 5V is supplied to the drain of the MOS transistor Qc0 on the proximal side connected in series. When the clock signals φ and φ * are changed in opposite phases, the capacitance element is sequentially charged in synchronization with the change and the boosted voltage Vpp from the diode connection type MOS transistor Qcn on the termination side.
Can be obtained. The voltage limiter 131 is, although not particularly shown, a circuit for limiting the upper limit of the boosted voltage Vpp, for example, a diode-connected MOS between the power supply terminal and the source of the MOS transistor Qcn.
A predetermined number of transistors can be arranged in series.

The charge pump circuit 130 uses the clock signals φ and φ * of opposite phases to sequentially transfer the charges charged in the capacitive element to the subsequent stage through the diode-connected type MOS transistor, and thereby the power source. Potential V
Although the boosted voltage Vpp having a higher level than dd is generated, the boosted voltage Vpp obtained at this time is roughly as follows. Can be represented by However, in the above equation, n is the number of boosting stages and Vbs is the potential between the source and the substrate.

The threshold voltage Vth (Vbs) in the above equation can be expressed by Vth (Vbs) = Vth (0) + K {(Vbs + 2φf) ^1/2 − (2φf) ^1/2 }. In this equation, K = (2εsεoqNa) ^1/2 / Cox is the substrate effect constant, φf
Is the Fermi potential, εs is the relative permittivity of Si, εo is the permittivity in vacuum, Na is the substrate impurity concentration, q is the electron charge amount, and Cox is the gate oxide film capacitance. According to these equations, the higher the substrate impurity concentration, the larger the value of the substrate effect constant K and the larger the threshold voltage Vth of the MOS transistor. The thicker the gate oxide film, the larger the value of the substrate effect constant K, and the larger the threshold voltage Vth of the MOS transistor.

In the charge pump circuit 130 of the present embodiment, the MOS transistors QC0 to QCk from the first stage to the k-th stage.
Is composed of a gate with a thin gate oxide film.
The MOS transistors QK + 1 to Qn up to the stage are composed of thick gate oxide film gates. As a result, the boosted voltage Vpp
Is It is represented by. Diode connection type M from the first stage to k stages
Since the gate oxide film of the OS transistor is thin, the substrate effect constant K is small and the Vth drop is small. Therefore,
Even if the impurity concentration of the semiconductor substrate or the well region is increased due to the scaling of the MOS transistor, the boosting efficiency by the built-in charge pump circuit can be improved.

Although not particularly limited, the MOS type capacitive element is also composed of the capacitive elements C1 to Ck from the first stage to the k-th stage having a thin gate oxide film, and the capacitive element C from the (k + 1) th stage to the n-th stage.
k + 1 to Cn are composed of thick gate oxide film gates. In the charge pump circuit 130, by forming the MOS type capacitance elements C1 to Ck on the preceding stage side to which relatively high voltage is not applied with a relatively thin gate oxide film, the capacitance value per unit area becomes large, and the capacitance value per unit area is increased. Since the capacitance elements C1 to Ck can be reduced, the charge pump circuit 130
The chip occupying area can be reduced.

According to the above description, the kth stage diode-connected MOS transistor QCk and the MOS-type capacitance element Ck.
Withstand voltage is higher than the boosted voltage at this stage position. That is, up to which stage is constituted by the gate of the relatively thin gate oxide film is determined in consideration of the breakdown voltage of the diode-connected type MOS transistor and the MOS type capacitive element at the stage position. Diode-connected MOS transistor and MOS in the latter stage of the charge pump circuit 130
The relatively thick gate oxide film of the capacitive element ensures the withstand voltage of the transistor with respect to the boosted voltage.

FIG. 1 shows an example of a device structural cross section of a transistor included in the charge pump circuit 130.

The FLOTOX type transistor Qf forming a memory cell in the EEPROM has a control gate and a floating gate, and therefore, a polysilicon two-layer process is usually adopted. According to the example of FIG. 1, 12 is a first layer gate and 9 is a gate oxide film of the first layer gate 12. Reference numeral 16 is a second layer gate, and 14 is a gate oxide film of the gate 16.
The thickness T of the gate oxide film 9 on the p-type well region 2
T is between the ox1 and the thickness Tox2 of the gate oxide film 14.
There is a relationship of ox1> Tox2. At this time, the diode-connected type MOS transistors and the MOS-type capacitance elements from the first stage to the k-th stage have a relatively thin gate oxide film 14
And the diode connection type MOS transistor and the MOS type capacitive element of the k + 1th stage and thereafter are composed of the first layer gate 12 having a relatively thick gate oxide film 9. In addition, a MOS transistor requiring a high breakdown voltage, such as a transistor in a write circuit system, is formed by the first-layer gate 12 having a relatively thick gate oxide film 9.

The structure of each transistor will be described in detail with reference to FIG. The EEPROM of this embodiment is formed on the p ⁻ type semiconductor substrate 1. This p ^- type semiconductor substrate 1
Is composed of, for example, single crystal silicon. The p ^-
The element formation surface (hereinafter referred to as the main surface) of the semiconductor substrate 1 is
A p ⁻ type well region 2 is provided. An element isolation insulating film 4 is provided in the inactive region of the main surface of the p ⁻ type well region 2. Under the element isolation insulating film 4, ap ⁺ type semiconductor region 3 forming a channel stopper region is provided. The element isolation insulating film 4 is made of, for example, a silicon oxide film.

Each of the FLOTOX type transistor Qf and the selection MOS transistor Qs constituting the memory cell is provided in the main surface portion of the p--type well region 2 in the region defined by the element isolation insulating film 4. Has been.

The FLOTOX type transistor Qf is
The first gate insulating film 9, the n ⁺ type semiconductor region 7a forming the write semiconductor plate region, the tunnel insulating film 10, the n ⁺ type semiconductor region 7 forming the source and drain regions, the floating gate electrode 12, the 2 gate insulating film 1
4 and the control gate electrode 16 respectively.

In this FLOTOX transistor Qf, the first gate insulating film 9 is provided on the main surface of the p ^-- type well region 2. The gate insulating film 9 is composed of, for example, a silicon oxide film. A part of the gate insulating film 9 has a small film thickness and is used as the tunnel insulating film 10. The floating gate electrode 12
Is on the first gate insulating film 9 and the tunnel insulating film 1.
0 is provided above. The floating gate electrode 12 is composed of a first-layer conductive film, for example, a polycrystalline silicon film (first-layer gate). The control gate electrode 16 is provided on the floating gate electrode 12 with the second gate insulating film 14 interposed therebetween. The control gate electrode 16 is formed integrally with the control line CL shown as a representative. The control gate electrode 16 is composed of a second layer conductive film, for example, a polycrystalline silicon film (second layer gate). The control gate electrode 16 includes a metal film having a resistance value lower than that of the polycrystalline silicon film, for example, a refractory metal film, a silicide metal film, a laminated film of these, or a polycrystalline silicon film and these metal films. You may comprise by a laminated film. The second gate insulating film 14 is composed of a silicon oxide film formed by thermally oxidizing the floating gate electrode. The write semiconductor region 7a is formed under the tunnel insulating film 10.
It is provided on the main surface portion of the p ⁻ type well region 2. The n ⁺ type semiconductor region 7 forming the source region and the drain region is provided on the main surface of the p ⁻ type well region 2 on the side of the floating gate electrode 12. One of the n ⁺ type semiconductor regions 7 is formed integrally with the writing semiconductor region 7a. The wiring 22 (source line SL) is connected to the other of the n ⁺ type semiconductor region 7 through the connection hole 21 of the interlayer insulating film 20. The interlayer insulating film 20 is composed of, for example, a deposited silicon oxide film. The wiring 22 is made of, for example, an aluminum film. The wiring 22 may be formed of, for example, an aluminum alloy film containing silicon or copper, or an aluminum alloy film containing silicon and copper. A surface protective film 25 is provided on the wiring 22. The surface protection film 25 is composed of, for example, a deposited silicon nitride film.

The selection MOS transistor Qs comprises a gate insulating film 9, a gate electrode 12, and an n ⁺ type semiconductor region 7 forming a source region and a drain region.

In the selection MOS transistor Qs, the gate insulating film 9 is provided on the main surface of the p ^-- type well region 2. The gate insulating film 9 is composed of, for example, a silicon oxide film. In addition, this gate insulating film 9
Are formed in the same step as the first gate insulating film 9. The gate electrode 12 is formed integrally with the word line WL. The n ⁺ type semiconductor region 7 forming the source region and the drain region is provided on the side surface of the gate electrode 12 in the main surface portion of the p ⁻ type well region 2. One of the n ⁺ type semiconductor regions 7 is provided with the FLOT.
It is formed integrally with the n ⁺ type semiconductor region 7a of the OX type transistor Qf. On the other side of the n ⁺ type semiconductor region 7, the wiring 2 is formed through the connection hole 21 of the interlayer insulating film 20.
2 (data line DL) is connected.

The MOS transistors requiring high breakdown voltage, such as the diode-connected type MOS transistors QCk + 1 to QCn, are the main regions of the p ^-- type well region 2 within the region defined by the element isolation insulating film 4. The first-layer gate 12 is provided on the surface portion. These M
OS transistor (typically one MO in FIG. 1)
QCn (shown as S transistor QCn) is mainly composed of each of the gate insulating film 9, the gate electrode 12, and the n ⁺ type semiconductor region 7 forming the source region and the drain region.

In the MOS transistor QCn, the gate insulating film 9 is provided on the main surface of the p--type well region 2. The gate electrode 12 is provided on the gate insulating film 9. The n ⁺ type semiconductor region 7 forming the source region and the drain region is provided on the side surface of the gate electrode 12 in the main surface portion of the p ⁻ type well region 2. The diffusion depth of this n + type semiconductor region 7 is
Although not particularly limited, it is larger than the diffusion depth of the n ⁺ type semiconductor region 18 forming the source region and the drain region of the other MOS transistor, and the diffusion depth of the n ⁺ type semiconductor region 7 is the FLOTOX type transistor. This is the same as the diffusion depth of each of the n ⁺ type semiconductor regions 7 and 7a of Qf. A wiring 22 is connected to the n ⁺ type semiconductor region 7 forming the drain region through a connection hole 21 in the interlayer insulating film 20. N ⁺ constituting the source region
One of the wirings 22 is connected to the type semiconductor region 7 through the connection hole 21 of the interlayer insulating film 20.

The MOS transistors such as the diode connection type MOS transistors QC0 to QCk which do not require a high withstand voltage are provided in the main surface portion of the p ^-- type well region 2 within the region defined by the element isolation insulating film 4. And the second layer gate 16 is applied. These M
OS transistor (typically one MO in FIG. 1)
The S transistor QCk is shown in the figure. QCk is mainly composed of the gate insulating film 14 provided on the main surface of the p ⁻ type well region 2, the gate electrode 16 provided on the gate insulating film 14, and the p In the main surface portion of the -type well region 2, each of the n ⁺ type semiconductor regions 18 constituting the source region and the drain region provided on the side of the gate electrode 16 is formed. A wiring 22 is connected to the n ⁺ type semiconductor region 18 through a connection hole 21 in the interlayer insulating film 20. Incidentally, the p-channel type MOS transistor is
^It is formed in an n ⁻ type well region (not shown) formed in the main surface portion of the ⁻ type semiconductor substrate 1.

Next, an example of a manufacturing process of the structure shown in FIG. 1 will be described with reference to FIGS.

[0038] First, p ^- -type main surface of the semiconductor substrate 1 p ^- -type well region 2 and the p ⁺ -type semiconductor regions 3, the field portion by selective oxidation techniques as shown in FIG. 4 (A) Forms an element isolation film 4, and forms a relatively thick gate insulating film or gate oxide film 9 in the active region. As shown in FIG. 4B, the n-type impurities are diffused to form the drain region and the source region 7 of the FLOTOX transistor Qf and the high breakdown voltage MOS transistor.
To form. Then, as shown in FIG. 4C, the FLOTOX type transistor Q is formed on the gate insulating film 9.
floating gate of f and MOS transistor QCk
First layer gate (first layer polysilicon gate) 1 for the gate of a high voltage MOS transistor such as +1 to QCn
Form 2. Next, as shown in FIG. 4D, an oxide film 14 and a second layer gate (second layer polysilicon gate) 16 are formed. The oxide film 14 serves as an interlayer insulating film of the FLOTOX type transistor Qf, and is a MOS transistor Q that does not require a high breakdown voltage to operate at 5V.
It is used as a gate oxide film of C0 to QCk. Second layer gate 16
Is a control gate of the FLOTOX type transistor Qf and gates of the MOS transistors QC0 to QCk. Then, as shown in FIG. 5E, the polycrystalline silicon and the silicon oxide in the element forming portion are removed by photoetching to remove them, and then they are oxidized by high heat to completely surround the gate with the silicon oxide. This insulates the gate portion of the device from the surroundings. Next, as shown in FIG. 5F, n-type impurities are diffused to form the drain region and the source region 18 of the MOS transistor. Further, as shown in FIG. 5G, an insulating film is grown by, for example, a CVD method, a contact hole for forming a wiring is formed by photoetching, and a wiring layer is formed through aluminum vapor deposition or photoetching. Finally, final passivation is performed.

FIG. 6 shows a block diagram of an embodiment of a microcomputer equipped with the EEPROM. This microcomputer 140 is a central processing unit (CP
U) R centering on 141 and holding its operating program
A RAM 14 used as a work area of the OM 142, the central processing unit 141, a primary storage area of data, or the like.
3, timer 144, direct memory access
Controller (DMAC) 145, I / O port (PO
RT) 146, and the EEPROM 100, which are commonly connected to the internal bus 147. EEPROM 10
0 is used as a programmable logic device that stores constant data necessary for calculation and control, and has a required logic programmable.

According to the above embodiment, there are the following effects.

(1) The gate oxide film 14 of the diode connection type MOS transistors QC0 to QCK in the first to kth stages included in the charge pump circuit 130 is changed to a diode connection type MOS transistor in the subsequent stage within a range allowable in terms of withstand voltage. It is made thinner compared to Vth due to the substrate effect.
The drop is reduced, and the boosting efficiency by the built-in charge pump circuit 130 can be improved even if the impurity concentration of the semiconductor substrate or the well region is increased due to the scaling of the MOS transistor.

(2) The MOS type capacitance element included in the charge pump circuit 130 and the gate oxide films of the capacitance elements C1 to Ck in the first stage to the kth stage are thinner than the capacitance elements in the subsequent stages as long as the breakdown voltage allows. Configured so they M
It is possible to increase the capacitance value per unit area of the OS type capacitance elements C1 to Ck.
Since Ck can be reduced, the chip occupation area of the charge pump circuit 130 can be reduced.

(3) The relatively thick gate oxide film of the diode connection type MOS transistor and the MOS type capacitance element in the latter stage of the charge pump circuit 130 guarantees the withstand voltage of the transistor against the boosted voltage.

(4) The thickness control of the gate oxide film of the diode connection type MOS transistor and the MOS type capacitance element which constitutes the charge pump circuit is controlled by the first layer gate and the second layer which are different in the thickness of the gate oxide film. Since it is performed in the existing process of the semiconductor integrated circuit in which a large number of MOS transistors are formed including the layer gate, it is not necessary to add a special process such as well concentration division in order to make the boosting operation efficient.

(5) One-chip type microcomputer 1
Under the constraint that the process cost allowed for the EEPROM 100 on-chip in 40 must be kept relatively small, compared to the technique of forming the charge pump circuit in the well region on the relatively low concentration side, It is possible to suppress an increase in the process cost of the entire chip.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the thickness of the gate oxide film on the preceding stage side is made relatively thin with respect to each of the diode-connected type MOS transistor and the MOS capacitor included in the charge pump circuit. In addition, it can be applied only to the diode-connected type MOS transistor or only to the MOS capacitor element in order to reduce the area of the charge pump circuit. Further, the capacitance element applied to the charge pump circuit is not limited to the MOS type capacitance element, and may be a capacitance element using an interlayer insulating film or the like. Also, EE
The nonvolatile memory element applied to the PROM is FLOTOX.
The MNOS type is not limited to the type. Further, the phased signals to be given to the storage electrodes of the capacitive elements included in the charge pump circuit are not limited to the two-phase clock signals and may be clock signals of three or more phases. Furthermore, the first layer gate and the second layer gate are not limited to polysilicon gates.

Although the above embodiments have been described with respect to the case where the present invention is applied to the EEPROM, the present invention is not limited thereto. In a memory cell having a channel injection structure for an EPROM having a control gate and a floating gate, writing is performed by applying a high voltage between the control gate and the drain. However, when a booster circuit is applied to this writing, the present invention is applied. Can also be applied to EPROMs. The present invention can also be applied to a charge pump circuit of a substrate back bias voltage generating circuit of a dynamic RAM or a pseudo static RAM. The present invention can be widely applied to at least a semiconductor substrate having a condition including a charge pump circuit.

[0049]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, as far as the withstand voltage is allowed, the proximal side diode connection type M included in the charge pump circuit is included.
By thinning the gate insulating film of the IS transistor as compared with the latter stage side, Vth drop due to the substrate effect can be reduced, and even if the impurity concentration of the semiconductor substrate or the well region becomes high due to the scaling of the MIS transistor. There is an effect that the boosting efficiency by the built-in charge pump circuit can be improved.

By making the dielectric film of the capacitance element on the proximal side included in the charge pump circuit thinner than that on the rear stage side within the range allowable in terms of breakdown voltage, the capacitance value per unit area of these capacitance elements is increased. As a result, it is possible to reduce the size of these capacitance elements and reduce the chip occupation area of the charge pump circuit.

A charge pump circuit is constructed by applying it to a semiconductor integrated circuit in which a large number of MIS transistors are formed including a first layer gate and a second layer gate having different thicknesses of gate insulating films. The thickness control of the gate insulating film of the diode connection type MIS transistor and the dielectric film of the capacitive element can be performed by the existing process.
There is no need to add a special process such as well concentration division in order to make the boosting operation efficient. Therefore, EEPRO which is on-chip in a one-chip microcomputer
Under the constraint that the process cost allowed for M or EPROM and the like must be kept relatively small, the process cost of the entire chip can be reduced as compared with the technique of forming the charge pump circuit in the well region on the relatively low concentration side. The rise can be suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of a device structure of a transistor included in a charge pump circuit.

FIG. 2 is a circuit diagram of an example of a high voltage generation circuit including a charge pump circuit.

FIG. 3 is a block diagram of an EEPROM according to an embodiment of the present invention.

FIG. 4 is an explanatory view showing the first half of a manufacturing process for obtaining the structure shown in FIG. 1.

5 is an explanatory diagram showing the latter half of the manufacturing process for obtaining the structure shown in FIG. 1. FIG.

FIG. 6 is a block diagram of an example of a microcomputer including the EEPROM.

[Explanation of symbols]

2 P ⁻ type well region 9 first-layer gate oxide film 12 first-layer gate 14 second-layer gate oxide film 16 second-layer gate Tox1 first-layer gate oxide film thickness Tox2 Second layer gate oxide film thickness 100 EEPROM MC Memory cell Qf FLOTOX type transistor Qs Select MOS transistor QC0 to QCk Diode connection type MOS transistor QCk + 1 to QCn having relatively thin gate oxide film Relatively thick gate Diode-connected MOS transistor C1 to Ck having an oxide film MOS type capacitance element Ck + 1 to Cn having a relatively thin gate oxide film MOS type capacitance element 130 having a relatively thick gate oxide film Charge pump circuit φ, φ * Two-phase clock signal Vpp Boost voltage Vdd Power supply voltage 140 Microcomputer

Front Page Continuation (72) Inventor Kota Tanaka 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Masaaki Terasawa 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo・ In Eye Engineering Co., Ltd. (56) Reference JP-A-2-236899 (JP, A) JP-A-2-16774 (JP, A) JP-A-3-86065 (JP, A) JP-A 4-268294 (JP, A) JP-A-2-237153 (JP, A) JP-A-63-141363 (JP, A) JP-A-63-185054 (JP, A) JP-A-60-59970 (JP, A) A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 16/06 H01L 27/115

Claims (5)

(57) [Claims] 1. A gate thickness gate is selected from a first-layer gate insulating film and the second-layer gate insulating film which is different from
A semiconductor integrated circuit in which a large number of MIS-type transistors using an insulating film are formed, which is a circuit in which a plurality of diode-connection type MIS-type transistors are connected in series, and those diode-connection type MISs.
Type transistor having a plurality of capacitance elements connected to one storage electrode, applying a voltage to a diode-connection type MIS type transistor on the proximal side connected in series, and a phase to the other storage electrode of the capacitance element. singular by the offset may grant signal includes a charge pump circuit for obtaining a boosted voltage from the diode connection type MIS transistor of the terminating side while charging the capacitor, located on the proximal side of the series-connected circuit Alternatively, in the plurality of diode-connected MIS transistors, the gate is formed by using a relatively thin gate insulating film of the first-layer gate insulating film and the second-layer gate insulating film , and the circuit connected in series is used. One or more diode-connection type MIS transistors located on the terminal side of the are connected to the first layer gate insulating film and the second layer gate insulating film The semiconductor integrated circuit, wherein the gate using a relatively thick gate insulation film of the inner are those composed configured. Wherein said capacitive element relatively with a thin gate insulating film <br/> gate is constructed diode connection type MIS transistor side has a relatively thin dielectric layer, said relatively capacitive element of the gate is constructed diode connection type MIS transistor side with a thick gate insulating film semiconductor according to claim 1, characterized in that is configured with a relatively thick dielectric film Integrated circuit. 3. A gate thickness gate is selected from a first-layer gate insulating film and the second-layer gate insulating film which is different from
A non-volatile semiconductor memory element in which a large number of MIS transistors using an insulating film are formed, which is electrically writable by using a boosted voltage, and a plurality of diode-connected MIS transistors. Circuits connected in series and diode-connected MISs
-Type transistor and a plurality of capacitive elements to which one storage electrode is connected, a voltage is applied to a diode-connected type MIS transistor on the proximal side connected in series, and at the same time to the other storage electrode of the capacitive element. includes a charge pump circuit for obtaining a boosted voltage from the diode connection type MIS transistor of the terminating side while charging the capacitive element by obtaining given a phase-shifted signal <br/>, the series connected circuit of the base A capacitive element coupled to one or more diode-connected MIS type transistors located on the end side is a dielectric layer formed of a relatively thin gate insulating film of the first layer gate insulating film and the second layer gate insulating film. and film, capacitive elements that bind to single or a plurality of diodes connected form the MIS transistor located at the end side of the series connection circuit is the first layer gate The semiconductor integrated circuit, characterized in that the relatively thick gate insulating film of the insulating film and the second-layer gate insulating film are those composed configured as a dielectric film. 4. The charge pump circuit forms a boosted voltage for a non-volatile memory element for EPROM or EEPROM configuration, and the EPROM or EEPR.
4. An on-chip OM is formed as a one-chip microcomputer, and any one of claims 1 to 3 is characterized.
The semiconductor integrated circuit according to the item. 5. A thickness of the gate insulating film is selected from a first-layer gate insulating film and the second-layer gate insulating film which is different from
A semiconductor integrated circuit in which a large number of MIS transistors using a gate insulating film are formed, wherein a nonvolatile semiconductor memory element electrically writable by using a boosted voltage and a plurality of MIS transistors of diode connection type are provided. Circuits connected in series and their diode connection type MIS
Type transistor and a plurality of capacitance means to which one storage electrode is connected, for applying a voltage to the diode-connected type MIS type transistor on the base end side connected in series, and to the other storage electrode of the capacitance means. includes a charge pump circuit for obtaining a boosted voltage from the diode connection type MIS transistor of the terminating side while charging said capacitance means by obtaining given a phase-shifted signal <br/>, the series connected circuit of the base the capacitive means for coupling to a single or a plurality of diodes connected form the MIS transistor located at the end side relative made from one gate insulating film of the first-layer gate insulating film and the second-layer gate insulating film Means having a relatively thin dielectric film and coupled to one or more diode-connected MIS type transistors located on the terminal side of the series connection circuit The first-layer gate insulation
The semiconductor integrated circuit, wherein the film and those comprising a relatively thick dielectric film made from one of the Gate insulating film of the second-layer gate insulating film.