JP2003152097A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To independently set the source voltages of an electrically writable and erasable semiconductor storage circuit and other MISFETs. SOLUTION: A device internally has a plurality of memory cells each having a floating gate electrode where information is recorded or written by injecting or discharging electrons, and a control electrode which comes into contact with the floating gate across an insulating film, so as to control the injection or discharge of the electrons into or from the floating gate electrode, the electrically writable; erasable semiconductor storage circuit which has word lines and data lines connected to the memory cells; and a voltage control circuit which generates a voltage used to inject or discharge the electrons by stepping up or down a source voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device including a one-chip microcomputer.

[0002]

2. Description of the Related Art A one-chip microcomputer in which a control unit, a calculation unit, a storage unit and an input / output unit are mounted on the same semiconductor substrate is, for example, Hayakawa issued by CQ Publishing Co., Ltd. on April 1, 1984. As described in "Basics of One-Chip Microcomputers and Their Application Technologies" by Masaharu, they are widely used for industrial and home appliances as inexpensive and highly functional control elements. The storage unit of the one-chip microcomputer has a ROM (Read Only Memory) in which programs for various information processing, dictionary data, etc. are stored, and a RAM in which mainly programs being executed and data in the middle of calculation are temporarily stored.
(Random Access Memory).

As the ROM, a mask ROM for writing data during the manufacturing process is usually used. However, in order to facilitate system debugging, EPROM (Erasable and
Programmable ROM) is also widely used. EPRO
Since the data of M can be erased by irradiating it with ultraviolet rays, the information can be rewritten any number of times and a one-chip microcomputer with a high degree of freedom can be obtained.

[0004]

The present inventor has found the following problems as a result of examining a one-chip microcomputer having a built-in non-volatile memory that can be electrically written and erased.

A high breakdown voltage is required for the MISFET in the I / O of the one-chip microcomputer. In addition, when a nonvolatile memory cell that can be electrically written and erased and a circuit that generates a voltage for writing or erasing the same are built in a one-chip microcomputer, a logic voltage system and a voltage of a higher level than that. Since the system is applied to the peripheral circuit of the nonvolatile memory cell, the MISF in the peripheral circuit
The withstand voltage of ET must be taken into consideration.

An object of the present invention is to provide a technique capable of improving the function of a semiconductor integrated circuit device included in a semiconductor integrated circuit device including a one-chip microcomputer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, in a semiconductor integrated circuit device that constitutes a microcomputer having a central processing unit on one semiconductor chip and a non-volatile memory for storing program data, dictionary data, etc. of the central processing unit, A non-volatile memory electrically writes information, electrically erases the written information by irradiation of ultraviolet rays, and a non-volatile memory electrically writes the information and electrically writes the written information. And a second non-volatile memory for erasing.

Further, the EPROM is formed on the first region of the semiconductor substrate.
Memory cell is formed, and a memory MISFET in the memory cell of the EEPROM is formed in a second region different from the first region of the semiconductor substrate, and the second MISFET of the semiconductor substrate is formed.
A method of manufacturing a semiconductor integrated circuit device constituting a microcomputer including a step of forming a switch MISFET in a memory cell of an EEPROM in a third region adjacent to a region, the method comprising: Forming a first gate insulating film on the surface of each of the first and third regions, forming a source and a drain in a predetermined portion of the second and third regions below the first gate insulating film, Forming a floating gate electrode on the first gate insulating film in the first and second regions and forming a gate electrode on the first gate insulating film in the third region;
Forming a second gate insulating film on the surface of the floating gate electrode in the region and the second region, and the first and second regions.
Each of the steps includes a step of forming a control gate electrode on the second gate insulating film in the region, and a step of forming a source and a drain in a predetermined portion below the first gate insulating film in the first region. It is done in the above order.

According to the above-mentioned means, program data and dictionary data which require a large storage capacity are stored in the EPROM.
EEPR is the control data that needs to be stored even when the power supply is cut off and the content of the data changes with time like the control data of the feedback control.
Since the information is stored in the OM, the function of the semiconductor integrated circuit device including the one-chip microcomputer can be improved.

Further, since a part of the step of forming the memory cells of the EPROM on the semiconductor integrated circuit device composed of the one-chip microcomputer and the step of forming the memory cells of the EEPROM are shared, the semiconductor integrated circuit device is described. The manufacturing process of can be reduced.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit device comprising a one-chip microcomputer according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 is a semiconductor chip in which a microcomputer is configured, and includes a CPU (microprocessor) 100, an OSC (oscillator) 101, and an I / O.
O (input / output port) 102, SI (serial interface) 103, TIMER (timer) 104, EP
ROM (erasable & programmable read only memory) 105, V _CX C (voltage control circuit) 10
6. EEPROM (Electrically Erasable &
Programmable read only memory) 107,
SRAM (Static Random Access Memory) 108, DRAM (Dynamic Random Access Memory) 109, I / OBUS (I / O Bus) 1
Equipped with 10. The CPU 100 is composed of a control unit, a calculation unit and various registers. OSC101 is
Although not limited, a crystal oscillator Xtal provided outside the semiconductor chip 1 is used to form a highly accurate reference frequency signal. The reference frequency signal formed here is necessary for the CPU 100. Form a clock pulse that is generated. The I / O 102 includes a data transfer direction register inside. EPROM 10
5, EEPROM107, SRAM108, DRAM1
Reference numeral 09 includes a control circuit required for reading, writing, or erasing information in the memory element. V _CX C10
6 is a writing operation of the EPROM 105 and an EEPROM
The word line voltage or the data line voltage necessary for the write / erase operation of 107 is controlled. The SI 103 is composed of three terminals of serial clock, serial in, and serial out and a register of a predetermined bit, and is an input / output for data transfer between the microcomputers when a plurality of microcomputers are used. Used as a port. The TIMER 104 is used to set the time required for multiple processing such as interrupt processing. CPU 100, I / O 10
2, SI103, TIMER104, EPROM10
5, V _CX C 106, EEPROM 107, SRAM 10
8. DRAM109 is I / OB centered on CPU100
Connected to each other by US110. In addition, I /
The OBUS 110 is composed of three parts: a data bus, an address bus, and a control bus.

The EPROM 105 stores programs for various information processing, dictionary data and the like. The EPROM 105 is used for storing those programs, dictionary data, etc., which require a relatively small number of data rewrites and require a large capacity. EEPROM
Reference numeral 107 denotes a memory for storing programs for various information processing, dictionary data, etc. It is also used to store data that needs to be stored even when shutting off. In addition, the EEPROM 107
Among the data that can be stored in the EPROM 105 such as programs for various information processing and dictionary data, the data is frequently rewritten and used for storing data having a large data capacity.

The writing operation of the EPROM 105 is as follows.
The procedure is as follows.

That is, various control signals output from the CPU 100 bring the EPROM 105 into a writable operating state and the voltage control circuit (V _CX C) 106.
And a predetermined word line voltage or data line voltage is generated by a write voltage applied from the outside or a voltage applied for normal operation of the microcomputer.

Next, the CPU 100 externally inputs data directly to the EPROM 105 via the I / O 102 or once RAM (SRAM 108, DRAM 109).
EPROM 105 based on the data input via
Write the predetermined data to the predetermined address of. EPRO
After writing various data to M105,
U100 ends the writing operation of the EPROM 105 and the operation of the voltage control circuit 106.

Next, the write and erase operations of the EEPROM 107 will be described.

In the writing and erasing operations of the EEPROM 107, various control signals output from the CPU 100 cause the EEPROM 106 to be in a writable or erasable operation state, and the voltage control circuit 106 is operated to write voltage applied from the outside. A predetermined word line voltage or data line voltage is generated by the erase voltage or the voltage for normal operation of the microcomputer. Next, the CPU 100 writes or erases predetermined data at a predetermined address of the EEPROM 107 based on the data directly input to the EEPROM 107 from the outside via the I / O 102 or the data once input via the SRAM 108 or the DRAM 109. Rewrite the data. After the writing, erasing or rewriting of various data to or from the EEPROM 107 is completed, the CPU 100 terminates the writing or erasing operation of the EEPROM 107.

The normal operation of the microcomputer of this embodiment is to control various control signals, EPROM 105 and EE.
Based on the programs and dictionary data stored in the PROM 107, various data input to the I / O 102 is subjected to predetermined processing, and then the data is output from the I / O 102 to the outside. Here, various data input to the I / O 102, data subjected to predetermined processing, or the CPU 10
Among the data in the register of 0, the data that needs to be stored even when the power is cut off, that is, each of the above-mentioned data that is necessary at the time of restarting after the power is cut off, is the EEP described above.
It is stored at a predetermined address in accordance with the operation procedure of the ROM 107. The storage in the EEPROM 107 may be performed while the intermediate data is stored in the EEPROM 107 for each processing at each place, or the final data after the predetermined processing is completed may be stored in the EEPROM 107.

On the other hand, in the microcomputer of the present embodiment, when abnormal power interruption occurs due to an accident, various data necessary for restarting operation,
That is, various data input to the I / O 102, data subjected to a predetermined process, or predetermined data among the data in the register of the CPU 100 are stored in the EEPROM described above.
It is stored at a predetermined address according to the operation procedure of 107. As described above, the microcomputer of the present embodiment has the power supply voltage backup circuit that supplies the voltage necessary for the operation of the EEPROM 107 so that the EEPROM 107 operates normally even when the power is cut off. This power supply voltage backup circuit is not particularly limited, but it may be configured of a capacitor and a control circuit on the same semiconductor chip as the microcomputer of the present embodiment, or it may be the microcomputer of the present embodiment. It may be configured on an electronic device including a computer and having the same power source.

Next, referring to FIG. 1 and FIG.
The circuit operation of M105 will be described.

FIG. 3 is an equivalent circuit diagram showing a schematic configuration of a circuit of the EPROM 105 incorporated in the microcomputer of the present embodiment.

E of the microcomputer of this embodiment
The PROM 105 includes a logic voltage system such as a power supply voltage Vcc of 5 V, and a write voltage system including a write voltage Vpp or a high voltage V _{CX of} tens of volts obtained by stepping up or down the write voltage Vpp by the voltage control circuit 106. Is the operating power supply. During a normal read operation, the logic voltage system operates.

The EPROM 105 has an address input terminal Xo.
Through Xi and Yo through Yj, the operation is controlled by the address signal supplied through the control terminals CE, OE, and PGM, the chip enable signal, the output enable signal, and the program signal. These control signals are relayed or formed by a control circuit in the EPROM 105 (not shown) under the control of the CPU 100.

The EPROM 105 in this embodiment performs a read or write operation of a memory cell in units of 8 bits. The memory cell array M-ARY has a plurality of Ms that are electrically written and erased by irradiation with ultraviolet rays.
ISFETs Q _{EP1 to} Q _EP4 , a plurality of word lines including word lines W0 to W1, and a plurality of data lines including data lines D0 to D1. Memory cell array M-
In ARY, MISFETQs arranged in the same row
The drains of _EP1 , Q _{EP2 to} Q _EP3 , Q _EP4 are connected to the corresponding data lines D0, D1, respectively. Address terminal X
The X address signal and the Y address signal supplied from the CPU 100 via o to Xi and Yo to Yj are X
Address buffer XADB and Y address buffer Y
Input to ADB. Address buffer XADB, YA
DB operates according to the timing signal ce formed by the control circuit CONT, takes in the address signal supplied from the CPU 100, forms a complementary address signal composed of internal address signals in phase and in phase with the address signal, and X address decoders XDCR and Y Address decoder YD
Supply to CR.

The X address decoder XDCR supplies a selection signal for selecting a word line of the memory cell array M-ARY according to the complementary address signal supplied by the X address buffer XADB. The voltage level of the word line selection signal formed by the X address decoder XDCR is determined by the voltage V _CX supplied from the voltage control circuit 106. During a normal read operation, the power supply voltage Vcc level, which is a logic voltage system, is set, and during a write operation, it is set to the V _CX level, which is a write voltage system.

Y address decoder YDCR
The complementary address signal supplied by the buffer YADB
Select the data line of the memory cell array M-ARY.
Form a selection signal for Y address decoder YD
The selection signal output from the CR is the Y gate circuit YGATE.
MISFETY₁₁, Y₁₂, Y_{twenty one}, Y_{twenty two}On the gate electrode of
Supplied. The data line is selected by the Y gate circuit YGAT.
AE's MISFETY ₁₁, Y₁₂Multiple data line groups
After making the first selection consisting of_{twenty one}, Y
_{twenty two}Select a predetermined data line from the data line group by
The second selection is performed. Here, the Y gate circuit YGAT
E is composed of two MISFETs connected in series
Can reduce the load capacitance of each MISFET.
Therefore, high-speed read operation can be performed. Also normal
The voltage level of the data line in the read operation is
MISFET Q in the middle_EP1To Q_EP4Is written incorrectly
Power supply voltage V supplied to the word line in order to prevent
It is set to a level lower than the cc level. More concrete
Specifically, it is set to a level of 20 to 40% of Vcc.
During the write operation, V which is a write voltage system_CXlevel
Is set to a predetermined voltage. Also, each day
The data lines D0 and D1 are coupled to the common data line CD.

The data output circuit DOB is coupled to the common data line via the sense amplifier circuit SA. The sense amplifier is not particularly limited, but a current mirror type sense amplifier circuit is used in the present embodiment. The data output circuit DOB has an input / output terminal DI.
0 through are coupled to DI7. Data input circuit DI
B comprises an input buffer coupled to the input / output terminals DI0 to DI7.

Data is stored in the EPROM 105 by using the MISFETs Q _EP1 to Q _EP used in the memory cells.
The threshold voltage of _EP4 is usually a relatively low voltage (logic “1”) or a relatively high voltage (logic “0”) due to writing by charge injection to the floating gate electrode.
It depends on whether or not.

Next, referring to FIGS. 1 and 4, the EEPR
The circuit operation of the OM 107 will be described.

FIG. 4 is an equivalent circuit diagram showing a schematic configuration of a circuit of the EEPROM 107 mounted in the microcomputer of this embodiment.

The EEPROM 107 mounted in the microcomputer of the present embodiment has a logic voltage system such as a power supply voltage Vcc of 5 V and a write or erase voltage V.
The operating power supply is a write or erase voltage V _CX system having a high level such as ten and several V obtained by raising or lowering the voltage Vpp or the voltage Vcc by the pp or the voltage control circuit 106. A normal read operation operates by a logic voltage system. The EEPROM 107 is controlled by an address signal supplied through the address input terminals Xo to Xi and Yo to Yi, and various control signals controlled by or formed by a memory control circuit in the EEPROM 107 (not shown) under the control of the CPU 100. , Its operation is controlled.

EEPROM 107 in the present embodiment
Read or write memory in 8-bit units
Performs an erase operation. The memory array M-ARY is electrically
Multiple memory MISFETQ for writing and erasing
_EEP1To Q_EEP4And the memory MISFETQ_EEP1Through
Q_EEP4Control the read, write and erase operations of the
Switch MISFETQ_S1To Q_S4And the word line W_E0
Through W_E1And W_S0Through W _S1Multiple word lines, including
Line D₀Through D₁Consists of multiple data lines including
It In the memory array M-ARY, they are arranged in the same row.
Memory MISFETQ_EEP1, Q_EEP2To Q_EEP3, Q
_EEP4The control gate electrodes of the
Line W_E0Through W_E1Connected to the switch MISFETQ
_S1, Q_S2To Q_S3, Q_S4The gate electrodes of
Word line W_S0Through W_S1Connected to and placed in the same column
Switch MISFETQ_S1, Q_S3To Q_S2, Q_S4The de
Rain is the corresponding data line D₀Through D₁Connected to
Be done. Also, the switch MISFETQ_S1To Q_S4Saw
Memory MISFETQ_EEP1To Q_EEP4Connected to the
Memory MISFETQ_EEP1To Q_EEP4Source is grounded
Has been.

The X address signal and the Y address signal supplied from the CPU 100 via the address terminals Xo to Xi and Yo to Yj are input to the X and Y address buffer XYADB. Address buffer XYAD
B operates in accordance with the timing signal formed by the control circuit CONT, takes in the address signal supplied from the CPU 100, forms a complementary address signal composed of internal address signals of the same phase and opposite phase, and forms it as X.
Address decoder XDCR and Y address decoder Y
Supply to DCR. Also, the address buffer XYADB
Has a latch circuit therein, and the address signal can be temporarily stored in the latch circuit.

The X address decoder XDCR forms a selection signal for selecting two types of word lines of the memory array M-ARY according to the complementary address signal supplied from the address buffer XYADB.

The Y address decoder YDCR forms a selection signal for selecting the data lines D _{0 to} D ₁ of the memory array M-ARY according to the complementary address signals supplied from the address buffer YADB. The selection signal output from the Y address decoder YDCR is the Y gate circuit YG.
Supplied to ATE. The Y gate circuit YGATE is not particularly limited, but the Y gate circuit Y of FIG.
It is the same method as GATE.

The data input / output circuit IOB is connected to the data line and the input / output terminals DI0 to DI7. The data input / output circuit IOB includes a sense amplifier circuit, an input / output buffer circuit, and a latch circuit for temporarily storing input data.

Data latch circuit and program circuit DL
Temporarily stores the write or erase data supplied from the input / output terminals DI0 to DI7, and based on the write or erase data, the memory cell MISFETQ.
_EEP1 to those for writing or erasing operation of information Q _EEP4.

E of the microcomputer of this embodiment
Since the EPROM 107 includes various latch circuits as described above, it is possible to prevent erroneous writing or erasing during the writing or erasing operation.

Memory MISF of the EEPROM 107
As will be described later, the ETQ _{EEP1 to} Q _EEP4 each include a floating gate electrode, a tunnel insulating film below which a tunnel current can flow, and a semiconductor region below the floating gate electrode. Then, the write operation is to discharge electrons from the floating gate electrode to cause the memory MIS.
It _{means lowering} the threshold voltage of the _FETs Q _EEP1 to Q _EEP4 lower than the source voltage, and the erasing operation is the injection of electrons into the floating gate electrode to cause the memory MI.
This is to _make the thresholds of _SFETs Q _EEP1 to Q _EEP4 higher than the source voltage. Emission of electrons in writing and injection of electrons in erasing are performed through the tunnel insulating film.

Next, the circuit operation when writing information in the EEPROM 107 will be described.

First, various controls issued from the CPU 100
An operation state in which the EEPROM 107 can be written by a signal
Address and write address
The data is temporarily stored in the latch circuit of the buffer XYADB. Well
Also, the latch of the data latch circuit and the program circuit DL
The write data is temporarily stored in the circuit. Then write
Memory MISFETQ_EEP1To Q_EEP4Are combined
Switch MISFETQ_S1To Q_S4Word line W_S0No
To W_S1Set the potential of the
MISFETQ_S1To Q_S4To the operating state. this
When the memory MISFETQ_EEP1To Q_EEP4Is bound to
All word lines W_E0Through W_E1Is a low voltage of almost 0V
To After this, the memory MISFETQ to be written
_EEP1To Q _EEP4Switch MISFETQ_S1To Q_S4To
Data line D coupled through₀Through D₁Can write to
Apply a high voltage that is effective.

By the above circuit operation, the memory MISFE is
Since the potential of the semiconductor region under the tunnel insulating film provided under the floating gate electrodes of TQ _{EEP1 to} Q _EEP4 is higher than the potential applied to the control gate electrode, it is lower than this control gate electrode. The electrons in the floating gate electrode, which is at the potential, are emitted into the semiconductor region thereunder through the tunnel insulating film and writing is performed.

Next, the circuit operation for erasing information will be described.

In the present embodiment, although not controlled, the erase operation is performed for each word line.
In the erase operation, first, the EEPROM 107 is set to an erasable state by various control signals output from the CPU 100, and the word lines W _E0 , W _{E1 to} W _S0 , and W _S1 are set to a low voltage level close to the ground voltage. At this time, although not limited, the voltages of the data lines D ₀ and D ₁ are also set to a low voltage level close to the ground voltage. next,
Of the memory MISFET Q _EEP1 to Q word line coupled to _EEP4 W _E0, W _E1, erase the word line W _E0 to W _E1 to be erased and high voltage levels available. When these operations are performed, the voltage of the control gate electrodes of the memory _MISFETs Q _EEP1 to Q _EEP4 becomes higher than the voltage of the semiconductor region below the tunnel insulating film, so that electrons in the semiconductor region pass through the tunnel insulating film. It is injected into the floating gate electrode and erased.

Next, the circuit operation for reading information will be described.

In the read operation, first, the memory MISFET
Always Q _EEP1 to word lines coupled to Q _EEP4 W _E0 to W _E1 in the unselected state close to the ground voltage, the switch MIS
Word lines W _S0 through W _S1 coupled to FETs Q _S1 through Q _S4
A specific memory cell is selected from the plurality of memory cells by selecting the data lines D _{0 to} D ₁ .

The memory MIS of this selected memory cell
Either FET (Q _EEP1 to Q _EEP4, hereinafter simply Q
_When electrons are written in the floating gate electrodes of _{EEP1 to} Q _EEP4 ), the word line W is written as described above.
_{Since E0 to} W _E1 are at low potential, the memory M
ISFETQ _EEP1 to Q _EEP4 becomes nonconductive, this logic "0" corresponding to the read data lines D ₀ to D _1.

On the other hand, when electrons are not injected into the floating gate electrodes of the memory _MISFETs Q _EEP1 to Q _EEP4 of the selected memory cell, the memory _MISFETs Q _EEP1 to Q _EEP4 become conductive, which corresponds to this. As a result, the logic "1" is read to the data lines D _{0 to} D ₁ .

Next, the SRAM 108 and the DRAM 109 included in the microcomputer shown in FIG. 1 will be described.

The SRAM 108 is mainly used as a temporary storage circuit for data that needs to be transferred at high speed to / from the CPU 100 or the I / O 102 among programs being executed and data being calculated.

As shown in FIG. 2, the memory cell of the SRAM 108 included in the microcomputer of this embodiment has two P-channel MISFETs 205 and 206.
And four N-channel MISFETs 203, 204, 2
07 and 208.

2 is an SRAM provided in the microcomputer of the embodiment of the present invention shown in FIG.
It is an equivalent circuit of 108 memory cells.

The SRAM 108 has two memory cells.
It may be composed of four high resistance elements and four MISFETs. The DRAM 109 is mainly used in the CPU 1 in the program being executed and the data being calculated.
00 or I / O 102 does not need to perform high-speed data transfer and is used as a temporary storage circuit for data that requires a large capacity memory. D of this embodiment
The memory cell of the RAM 109 is composed of a capacitor section for accumulating charges and a switch MISFET for controlling the capacitor section. As described above, the RAM of the microcomputer of this embodiment is composed of the SRAM 108 and the DRAM 109, and the SRAM 108 is used for storing data which has a small data capacity but requires high-speed data transfer. The transfer does not have to be performed at a high speed, but the DRAM 109 is used for storing a large amount of data. The SRAM 10
8 operates as a so-called cache memory, and has a CPU
High-speed data transfer with 100.

The DRAM 109 in this embodiment is
The substrate 1 is not operated by applying a potential serving as a reference for electrical operation of the circuit, that is, a ground potential Vss, for example, a negative potential lower than 0V. This is because when a negative potential lower than the ground potential Vss is applied to the substrate 1 as described above, the EPROM 105 or E that normally operates without setting the substrate 1 to the negative potential.
This is because the characteristics of the MISFET that constitutes the EPROM 107 and the like change. However, the DRAM 1 on the substrate 1
The area in which 09 is configured is the EPROM 105 or EE
When it is electrically separated from the region where other MISFETs such as the PROM 107 are formed, the negative potential may be applied to the substrate 1 to operate the substrate 1. That is, as will be described later, the DRAM 109 and other EEP
The ROM 107, the EPROM 105, etc. may be provided in separate P-type well regions, and the P-type well regions may be electrically isolated.

The refresh operation of the DRAM 109 is C
It is controlled by the PU 100. In addition, the potential of the word line of the DRAM 109 is set to a potential higher than Vcc which is the voltage of the logic system to operate. This voltage is generated by the voltage control circuit 106.

Next, the structure of each MISFET constituting the microcomputer of this embodiment will be described with reference to FIGS. 5, 6 and 7.

FIG. 5 shows a MISFET constituting the EPROM 105 provided in the microcomputer shown in FIG.
6 is a cross-sectional view of the MISFET which configures the EEPROM 107 included in the microcomputer of FIG.
7 is a cross-sectional view of the MIS that configures the CPU 100, the I / O 102, and the like included in the microcomputer of FIG.
It is sectional drawing of FET.

In FIG. 5, Q1 is a MISFET forming a memory cell of the EPROM 105, Q2 is an N-channel MISFET forming a peripheral circuit such as an address buffer and a decoder of the EPROM 105, and Q3 is an address buffer and a decoder of the EPROM 105. Is a P-channel MISFET that constitutes the peripheral circuit of. EP
MISFET Q1 that constitutes a memory cell of the ROM 105
Is a first gate insulating film 6 formed of a thin silicon oxide film, provided in the p ⁻ type well region 3 of the main surface portion of the semiconductor substrate 1 formed of p ⁻ type single crystal silicon, and a floating gate formed of, for example, a polycrystalline silicon film. The electrode 7A, the second gate insulating film 8A made of a thin silicon oxide film, and the tungsten silicide film (W
A control gate electrode 9A made of a two-layer film in which Si ₂ ) is laminated, an n-type semiconductor region 11A forming a source / drain channel region side, and a part other than the n-type semiconductor region 11A of the source / drain forming and n ⁺ type semiconductor region 13A. The thickness of the first gate insulating film 6 is, for example, about 500 Å, and the second gate insulating film 8 is formed.
A is, for example, about 350Å. The n-type semiconductor region 1
1A is for increasing the generation of hot carriers and improving the writing characteristics of information. The control gate electrode 9A is also a word line. The side surface of the floating gate electrode 7A and the side surface and the upper surface of the control gate electrode 9A are covered with a thin silicon oxide film 10. Then, a sidewall 12 made of a silicon oxide film is provided on the side portions of the floating gate electrode 7A and the control gate electrode (word electrode) 9A. Then, between the memory cells Q1 in the direction in which the word line extends, the field insulating film 4 made of a silicon oxide film and the p-type channel stopper region 5 thereunder are formed.
Separated by. A data line 16 is formed in the n ⁺ type semiconductor region 13 which forms a part of the drain at the time of reading information.
D is connected. The data line 16D includes, for example, an aluminum film, aluminum as a main component, silicon,
Copper or palladium added, or a silicide film (MoSi ₂ ,
(TaSi ₂ , TiSi ₂ , WSi ₂ etc.). Reference numeral 14 denotes a first-layer passivation film, for example, a silicon oxide film formed by CVD, a phosphosilicate glass (PSG) film, a boron-doped P film.
It is formed of an SG (BPSG) film, a silicon oxide film by a plasma CVD method, or a laminated film thereof. 15
Is a connection hole. Reference numeral 17 denotes a second-layer passivation film, which is a silicon oxide film formed by a plasma CVD method,
It consists of a spin-on-glass film formed by spin coating. N-channel MISF constituting the peripheral circuit
The ETQ2 includes a gate insulating film 6, a gate electrode 7B made of, for example, a polycrystalline silicon film, an n ⁻ type semiconductor region 11B forming a source / drain channel region side, a source,
An n ⁺ type semiconductor region 13B forming a part of the drain other than the n ⁻ type semiconductor region 11B. The n ^-
The type semiconductor region 11B is for controlling the generation of hot carriers at the end of the drain and preventing the electrical characteristics of the MISFET Q2 from changing. The side surface and the upper surface of the gate electrode 7B are covered with a thin silicon oxide film 10. A wiring 16 made of an aluminum film is provided in the n ⁺ type semiconductor region 13B on the drain side through a connection hole 15.
Are connected. Then, this n ⁺ type semiconductor region 13
Is provided at a predetermined distance from the sidewall 12 in order to improve the breakdown voltage of the drain. The P-channel MISFET Q3 forming the peripheral circuit is provided in the n ⁻ type well region 2 on the main surface of the semiconductor substrate 1,
A gate insulating film 6, a gate electrode 7B made of, for example, polycrystalline silicon film, a source, p forms a portion of the channel side of the drain ^- -type semiconductor region 11C, the source, the p drain ^- part of the non-type semiconductor region 11C And a p ⁺ type semiconductor region 13C which forms A wiring 19 is connected to the wiring 17 through a connection hole 18. This wiring 19
Is made of the same material as the wiring 17. Although not shown, a final passivation film made of a PSG film, a silicon nitride film by a plasma CVD method, or the like is provided on the wiring 19.

The floating gate electrode 7A of the memory cell Q1, the gate electrode 7B of the N-channel MISFET Q2, and the gate electrode 7 of the P-channel MISFET Q3.
B is made of the same first-layer conductive film. The gate electrode 9A of the memory cell Q2 is made of the second layer conductive film. In addition, the memory cell Q1, N channel MISFET
The gate insulating films 6 of the Q2 and P-channel MISFET Q3 have the same film thickness.

In FIG. 6, Q4 is an EEPROM 107.
_MISFETs Q _{EEP1 to} Q in the memory cells of
N-channel MISFET constituting _EEP4 , Q5 is the above E
Switch MISF in memory cell of EPROM 107
ETQ _{S1 to} Q _S4 or N channel MISFETs constituting peripheral circuits such as address buffers and decoders of the EEPROM 107, and Q6 are P channel MISFETs constituting peripheral circuits of the EEPROM 107.

The N-channel MISFET Q4 has 50
A first gate insulating film 6 made of a thin silicon oxide film of about 0 Å, an insulating film 21 made of a silicon oxide film having a thickness of about 1000 to 2000 Å, and a tunnel insulating film 22 made of an extremely thin silicon oxide film of about 100 Å. , A floating gate electrode 7 made of, for example, a polycrystalline silicon film
Second layer consisting of C and a thin silicon oxide film of about 350 Å
It is composed of a gate insulating film 8C, a control gate electrode 9C formed integrally with the word line, and an n-type semiconductor region 20 serving as a source and a drain. The thin silicon oxide film 10 covers the side surface of the floating gate electrode 7C and the side surface and the upper surface of the control gate electrode (word line) 9C. The insulating film 21 is for relaxing the electric field at the end of the floating gate electrode 7C and improving the breakdown voltage. Switch MISFE of the memory cell
N-channel MISF for configuring T or peripheral circuits
The ETQ 5 includes a gate insulating film 6, an insulating film 21, a gate electrode 7B made of, for example, a polycrystalline silicon film, a source,
It is composed of an n-type semiconductor region 20 serving as a drain. The side surface and the upper surface of the gate electrode 7B are covered with the insulating film 10. A wiring 16D is connected to the n-type semiconductor region 20 serving as the drain of the N-channel MISFET Q5 through the connection hole 15. The wiring 16D is a data line in the memory cell and MIS in the peripheral circuit.
It is a signal wiring that connects between FETs. The P-channel MISFET Q6 forming the peripheral circuit has a gate insulating film 6 and
The gate electrode 7B, the p ⁻ type semiconductor region 11C forming the source and drain on the channel region side, and the p ⁺ forming the source and drain other than the p ⁻ type semiconductor region 11C.
And the type semiconductor region 13C. Gate electrode 7
The side surface and the upper surface of B are covered with the insulating film 10. A connection hole 15 is formed in the p ⁺ -type semiconductor region 13C forming a part of the source region.
The wiring 16 is connected through. And this p ⁺
The type semiconductor region 13C is provided at a predetermined distance from the sidewall 12 in order to improve the breakdown voltage of the source region.

The N-channel MISFE of the memory cell
N-channel MISFET forming TQ4 and switch element
A wiring 19 made of a second-layer aluminum film is formed on Q5.
Is covered. That is, the memory cell array region is entirely covered with the wiring 19. This is EPROM 105
This is to prevent the data stored in the EEPROM 107 from being erased by the ultraviolet rays when the data stored in the memory is erased by irradiating the ultraviolet rays.

The floating gate electrode 7C of the memory element Q4 and the gate electrodes 7 of the MISFETs Q5 and Q6.
B is formed of the same first-layer conductive film as the floating gate electrode 7A of the memory cell Q1 of the EPROM 105 and the gate electrode 7B of the MISFETs Q2 and Q3. The control gate electrode 9C of the memory MISFET Q4 of the EEPROM 107 is made of the same second-layer conductive film as the control gate electrode 9A of the EPROM 105.

In FIG. 7, Q7 is an N-channel MISFET for configuring the CPU 100, and Q8 is an I / O10.
2 and an N-channel MISFET that configures the SI (serial interface) 103, and a Q-channel MISFET that configures the CPU 100. The N-channel MISFET Q7 has a gate insulating film 8D made of a thin silicon oxide film of about 250 Å and a gate electrode 9D.
And n that form the part of the source and drain on the channel region side.
^An n ⁺ type semiconductor region 1 which forms the ⁻ type semiconductor region 11B and parts of the source and drain other than the n ⁻ type semiconductor region 11B.
3B and 3B. The N-channel MISFET
Q8 is a gate insulating film 8D, a gate electrode 9D, an n-type semiconductor region 11A forming a source / drain channel region side portion, and an n ⁺ -type forming a source / drain portion other than the n-type semiconductor region 11A. And the semiconductor region 13B. The n-type semiconductor region 11A is for preventing the MISFET Q8 from being destroyed when an abnormally high voltage is applied to the drain region. The P-channel MISFET Q9 includes a gate insulating film 8D, a gate electrode 9D, a p ^- type semiconductor region 11C forming a part of the source / drain on the channel region side, and a part of the source / drain other than the p ^- type semiconductor region 11C. And a p ⁺ type semiconductor region 13C which forms

The gate electrodes 9D of the MISFETs Q7, Q8 and Q9 are made of the same second layer conductive film as the control gate electrode 9A of the EPROM 105 and the control gate electrode 9C of the EEPROM 107.

The N-channel MISFET and the P-channel MISFET forming the memory cell of the SRAM 108 shown in FIG. 2 are the CPU (logical unit) 10 shown in FIG.
It has the same structure as the N-channel MISFET Q7 and the P-channel MISFET Q9 which form 0.

Next, the MISFETs Q1, Q2, Q
A method of manufacturing each of Q3, Q4, Q5, Q6, Q7, Q8, and Q9 will be described with reference to FIGS. 5, 6, and 7 to 56, 57, and 58.

5, FIG. 6, FIG. 7 to FIG. 56, FIG. 57, and FIG. 58 are EPROM 105, EEPROM 107, and CPU 1 of the microcomputer according to the embodiment of the present invention.
Is a cross-sectional view in the manufacturing process of the MISFET that configures 00 or the like, FIGS.
No. 7 memory cell and its peripheral circuits
Sectional views of a region where T is provided, and FIGS. 7 to 58 are CPUs.
FIG. 3 is a cross-sectional view of a region where a MISFET that constitutes 100 and the I / O 102 is provided.

The P-channel MISFET and N-channel MI forming the memory cell of the SRAM shown in FIG.
The SFET is formed by the same manufacturing method as the N-channel MISFET Q7 and the P-channel MISFET Q9 which form the logic part shown in FIG.

E of the microcomputer of this embodiment
The manufacturing method of the MISFET that constitutes the PROM 105, the EEPROM 107, the CPU 100, and the I / O 102 is as follows.
As shown in FIGS. 8 to 10, ion implantation and annealing are performed to predetermined regions of the main surface of the p ⁻ type semiconductor substrate (chip) 1 to form the n ⁻ type well region 2 or the p ⁻ type well region 3. Form. Reference numeral 50 is a thin silicon oxide film used as a buffer film when performing the ion implantation.

Next, as shown in FIGS. 11 to 13, a well-known technique is used to thermally oxidize predetermined regions of the n ^-- type well region 2 and the p ^-- type well region 3 to form the field insulating film 4. And a p channel stopper region 5 is formed in the p ⁻ type well region 3. 51 is the field insulating film 4
It is a silicon nitride film used as a mask for thermal oxidation when forming a. Next, the silicon nitride film 51 is removed, and further the silicon oxide film 50 used as the base film is removed to expose the portions of the n ⁻ type well region 2 and the p ⁻ type well region 3 which are not covered with the field insulating film 4. After that, the exposed surface is thermally oxidized again to form the gate insulating film 6 as shown in FIGS. 14 to 16.

Next, the EEPROM 107 shown in FIG.
N-channel MISFE of memory cell and its peripheral circuit
T source, as an ion implantation mask for forming the n-type semiconductor region 20 serving as the drain, n ^- -type well region 2 and to form p ^- resist film 52 on the type well region 3. Next, an n-type impurity, for example, arsenic (As) ion is introduced at about 10 ¹⁴ to 10 ¹⁶ atoms / cm ² to form the n-type semiconductor region 20. After that, the resist film 52 is removed.

Next, as shown in FIGS. 17 to 19, thermal oxidation is performed to form an insulating film (Si) on the n-type semiconductor region 20.
O ₂ ) 21 is formed. Since the insulating film 21 has the n-type semiconductor region 20 of the high-concentration layer below, a thick insulating film can be obtained. At this time, the oxide film thickness is set so that the film thickness of the gate insulating film 6 is about 500 Å. The film thickness of the insulating film 21 is about 1000 to 2000Å. Alternatively, after the gate insulating film 6 is removed, thermal oxidation is performed once to obtain 5
The gate insulating film of about 00Å and the insulating film on the upper portion of the n-type semiconductor region 20 of about 1000 to 2000Å may be simultaneously formed. Next, the memory MISFE of the EEPROM 107
In order to etch the insulating film 21 in the portion where the tunnel insulating film 22 of TQ4 is provided, as shown in FIGS. 20 to 22, a resist film 54 as a mask is formed.

Next, as shown in FIG. 21, the insulating film 21
The portion where the tunnel insulating film 22 is formed is etched to expose the surface of the n-type semiconductor region 20. After that, the resist film 54 is removed. Next, in the previous step, the insulating film 21
N-type semiconductor region 20 exposed by removing the
The surface of is thermally oxidized to form the tunnel insulating film 22 made of a silicon oxide film. The film thickness of the tunnel insulating film 22 is
It is about 100Å.

Next, the memory cell Q1 of the EPROM 105
Floating gate electrode 7A, MISF of peripheral circuit
ETQ2, Q3 gate electrode 7B and EEPROM 10
Floating gate electrode 7C of the memory MISFETQ4 of the memory cell of No. 7, switch MIS of the memory cell
Gate electrode 7 of MISFET Q5 of FET and peripheral circuit
In order to form B, as shown in FIGS.
For example, a polycrystalline silicon film 7 is formed on the n ⁻ type well region 2 and the p ⁻ type well region 3 by CVD. In this polycrystalline silicon film 7, n-type impurities,
For example, phosphorus (P) is introduced to reduce the resistance.

Next, as shown in FIGS. 26 to 28, the polycrystalline silicon film 7 is patterned to form an EPROM.
Floating gate electrode 7 of memory cell Q1 of 105
A, the gate electrode 7B of the peripheral circuit, the floating gate electrode 7 of the memory MISFET Q4 of the EEPROM 107.
C, switch MIS of memory cell of EEPROM 107
The FETs and the gate electrodes 7B of the MISFETs Q5 and Q6 of the peripheral circuit are formed, respectively. CPU 100 and I / O
Since the gate electrodes of the MISFETs Q7, Q8, and Q9 that form 102 are formed of the second-layer conductive film that will be formed later, the first-layer polycrystalline silicon film is formed in the region for forming these MISFETs Q7 to Q9. 7 has been removed and does not remain.

Here, the EPROM 105 shown in FIG.
The floating gate electrode 7A of the memory cell Q1 of
In the direction in which the data lines extend, the floating gate electrodes 7A of the individual memory cells are not divided and are extended long. However, in the extending direction of the word line, the floating gate electrodes 7A of the adjacent memory cells are separated from each other. This is because when the control gate electrode (word line) 9A is formed on the floating gate electrode 7A, the floating gate electrode 7A extending long in the direction in which the data line extends is patterned for the second time. This is to make it a predetermined pattern.

On the other hand, the floating gate electrode 7 of the memory MISFET Q4 of the memory cell of the EEPROM 107.
C has a pattern separated for each memory cell. Next, as shown in FIGS. 29 to 31, EP
Floating gate electrodes 7A and EE of ROM 105
The surface of the floating gate electrode 7C of the PROM 107 is thermally oxidized to form the second gate insulating films 8A and 8C.
When forming the second gate insulating films 8A and 8C, the surface of the other gate electrode 7B is also thermally oxidized to form a thin silicon oxide film 8. Next, after covering a portion other than the CPU 100 region and the I / O 102 region with the resist film 55, the thin silicon oxide film (gate insulating film) 6 formed in the CPU 100 region and the I / O 102 region is removed by etching.

Next, as shown in FIGS. 32 to 34, the CPU 100 region and the I / O 102 region exposed by previously etching the silicon oxide film 6 are thermally oxidized to form the CPU 100 and the I / O 102. For M
A gate insulating film 8D of ISFET is formed. When the gate insulating film 8D is formed, the surfaces of the floating gate electrodes 7A and 7C and the gate electrode 7B are oxidized, and the film thicknesses of the second gate insulating films 8A and 8C and the silicon oxide film 8 are increased.

Here, the film thickness of the second gate insulating films 8A and 8C is finally set to about 350 Å. Also,
The thickness of the gate insulating film 8D depends on the CPU 100 and the I / O 10
The film thickness is made optimum for the MISFETs Q7 to Q9 which form No. 2. The EPROM 105 and the EEPROM 10
No. 7 memory cell and MIS constituting the peripheral circuits thereof
FET gate insulating film 6, CPU 100 and I / O 10
Since the gate insulating film 8D of the MISFET forming the second structure has an optimum value for those MISFETs, the gate insulating film 6 may be formed thicker or the gate insulating film 8D may be formed thicker. is there. Further, the gate insulating film 6 and the gate insulating film 8D may be formed to have the same film thickness.

After forming the gate insulating film 8D, a second-layer conductive film 9 is formed on the entire surface of the semiconductor chip 1. The conductive film 9 is a two-layer film in which a polycrystalline silicon film is formed by CVD, for example, and a silicide film is further stacked thereon by sputtering. An n-type impurity such as phosphorus (P) is added to the polycrystalline silicon film by ion implantation or thermal diffusion to reduce the resistance.

Next, as shown in FIGS. 35 to 36, the conductive film 9 is patterned using the resist film 72 as a mask,
Control gate electrode (word line) 9C, MISFETQ of memory MISFETQ4 of EEPROM107
Gate electrodes 9D of 7, Q8 and Q9 are formed.

Next, as shown in FIGS. 38 to 40, a resist film 73 is formed. In this state, the EPROM 10
The control gate electrode 9A, the second gate insulating film 8A, and the floating gate electrode 7A of the memory cell Q1 of FIG. The floating gate electrode 7A divided for each is formed.
After that, the resist film 73 is removed.

Next, as shown in FIGS. 44 to 46, E
Surfaces of the control gate electrodes (word lines) 9A and 9D of the PROM 105 and the EEPROM 107 are thermally oxidized to form a thin silicon oxide film 10. At this time, the other MISFETs Q2, Q3, Q5, Q6, Q7,
The surfaces of the gate electrodes 7B and 9D of Q8 and Q9 are also oxidized to form the silicon oxide film 10. Region of memory cell Q1 of EPROM 105 and MISFET of I / O 102
A resist film 56 having an opening in the area of Q8 is formed,
An n-type impurity such as arsenic (As) is introduced into the p ^- type well region 3 by ion implantation to form an n-type semiconductor region 11A which becomes a part of the source and drain of the memory cell Q1 and the N-channel MISFET Q8. The dose amount of the impurity ions introduced at this time is, for example, 10 ¹⁵ atoms / cm ² .

After that, the resist film 56 is removed, and FIG.
As shown in FIG. 49, a resist film 57 is formed by opening an area in which the N-channel MISFET Q2 for forming the peripheral circuit of the EPROM 105 is provided and an area in which the N-channel MISFET Q7 for forming the CPU 100 is provided. Then, an n-type impurity such as phosphorus (P) is introduced by ion implantation, and the N-channel M
An n ⁻ type semiconductor region 11B which becomes a part of the sources and drains of the ISFETs Q2 and Q7 is formed. The dose amount of the impurity ions introduced at this time is, for example, 10 ¹³ atoms / cm ²
Is. After that, the resist film 57 is removed.

Next, as shown in FIGS. 50 to 52, E
P-channel MISFETs Q3 and Q for forming peripheral circuits of the PROM 105 and the EEPROM 107, respectively.
A resist film 58 is formed by opening a region where the 6 is provided and a region where the P-channel MISFET Q9 for forming the CPU 100 is provided. Then, a p-type impurity such as boron (B) is introduced by ion implantation to form a p ^- type semiconductor region 11C which becomes a part of the source and drain of the P-channel MISFETs Q3, Q6, Q9. The dose amount of the impurity ions at this time is, for example, 10
It is about ¹³ atoms / cm ² . After that, the resist film 58 is removed.

Next, as shown in FIGS. 53 to 55, a silicon oxide film is formed on the side portions of the respective gate electrodes 7A, 9A, 7B, 7C, 9C and 9D by using, for example, CVD and reactive ion etching. The side wall 12 is formed. Next, P-channel MISFETs Q3 and Q9
Then, a region where the N-channel MISFET for forming the memory cells of the EEPROM 107 and their peripheral circuits is provided is covered with the resist film 59. In addition, EPROM1
A resist film 59 is formed in order to increase the breakdown voltage of the drain of the N-channel MISFET Q2 of the peripheral circuit of No. 05 and to separate a high concentration portion thereof from the sidewall 12 and the field insulating film 4 by a predetermined distance. Then, an n-type impurity such as arsenic (As) is introduced by ion implantation to form n ⁺ -type semiconductor regions 13A and 13B. After that, the resist film 59 is removed.

Next, as shown in FIGS. 56 to 58, the respective N-channel MISFETs Q1, Q2, Q4, Q are shown.
5, Q7, Q8 is covered with a resist film 60, and EE
P-channel MISFETQ of peripheral circuit of PROM107
In order to increase the breakdown voltage of the drain of No. 6, a resist film 60 is formed in order to separate the high concentration portion from the sidewall 12 and the field insulating film 4 by a predetermined distance. Then, p-type impurities such as boron (B) are introduced by ion implantation to form the respective p ⁺ -type semiconductor regions 13. After that, the resist film 60 is removed. After that, as shown in FIGS. 5 to 7, the passivation film 14 is removed by, for example, CV.
A silicon oxide film formed by D, a PSG film, a BPSG film is formed by using a silicon oxide film formed by sputtering or a laminated film thereof.

Next, the passivation film 14 is selectively removed to form the connection hole 15, and thereafter, in order to alleviate the step at the portion of the connection hole 15, for example, annealing is performed at a temperature of about 900 ° C. to form the passivation film 14. Perform a glass flow. Next, on the passivation film 14, an aluminum film, an aluminum alloy film containing aluminum as a main component and adding silicon, copper, palladium, or the like to the aluminum film is formed by, for example, a sputtering method, a CVD method, or a vapor deposition method. A silicide film (MoSi
₂ , TaSi ₂ , TiSi ₂ , WSi ₂ ) and then these films are patterned to form the wiring 16 and the data line 16D.
To form. The silicide film may be formed on the passivation film 14 before forming the aluminum film or the aluminum alloy film, and the aluminum film or the like may be formed thereon. After forming the wirings 16 and 16D, for example, a silicon oxide film formed by plasma CVD, a spin-on-glass film formed by spin coating, and the like in this order from the bottom.
A silicon oxide film formed by plasma CVD is stacked to form a passivation film 17. Next, the passivation film 17 is selectively removed to form the connection hole 18. Since the connection hole 18 has the wiring layers 16 and 16D made of an aluminum film or the like having a low melting point in the lower portion, it is not possible to reduce the step difference by the glass flow. Etching is performed up to about half the film thickness, and then the remaining half is etched by anisotropic dry etching. Next, the wiring 19 is formed on the passivation film 17 by the method of forming the wirings 16 and 16D.
Next, although not shown, a PSG film and a silicon nitride film are formed as final passivation.

Incidentally, FIGS. 29 to 31 and FIGS. 32 to 3
As shown in FIG. 4, MI for configuring the CPU 100
M for configuring SFETs Q7, Q9 and I / O 102
First, the gate insulating film 8D of ISFET Q8 is EPROM.
Second gate insulating film 8A of 105 and EEPROM 107
After the second gate insulating film 8C is formed, the MISFE
The thin silicon oxide film 6 previously formed in the regions of TQ7, Q8, and Q9 was removed by etching, and then a dedicated thermal oxidation process was performed. 2 Before forming the gate insulating film 8C, the MISFETs Q7, Q8,
The thin silicon oxide film 6 in the area of Q9 is etched, and thereafter, when the second gate insulating films 8A and 8C of the EPROM and the EEPROM 107 are formed, the MISF is simultaneously performed.
Gate insulating film 8D by oxidizing the ETQ7, Q8 and Q9 regions
May be formed.

In addition, the manufacturing method of this embodiment is similar to that shown in FIG.
To the memory cell Q1 of the EPROM 105 shown in FIG.
The first gate insulating film 6 and the first gate insulating film 6 of the memory MISFETQ4 of the memory cell of the EEPROM 107 are formed at the same time. You may make it a little different.

Next, a method of manufacturing the memory cell of the DRAM provided in the microcomputer of this embodiment shown in FIG. 1 will be described.

59 to 62 are DRA's provided in the microcomputer of the present embodiment shown in FIG.
FIG. 9 is a cross-sectional view in the manufacturing process of the M memory cell.

First, the sectional structure of the memory cell of the RAM will be described with reference to FIG. As shown in FIG. 59, DR
The AM memory cell is provided in the p ⁻ type well region 3. And Q is the switch MISFET of the memory cell
And C is the capacitive element of the memory cell. Switch M
The ISFETQ is a gate electrode composed of a gate insulating film 8D made of a silicon oxide film and a two-layer film formed by laminating a silicide film (MoSi ₂ , TaSi ₂ , TiSi ₂ , WSi ₂ ) on a polycrystalline silicon film, for example. (Word line) 9
N, which is a part of D, the source, and the drain on the channel region side
N ^- type semiconductor region 11B, and n ⁺ type semiconductor region 13 forming a part other than the n ⁻ type semiconductor region 11B of the source and drain.
It is composed of B and. The capacitive element C includes an n-type semiconductor region 20 which is one electrode, a dielectric film 22 which is a thin silicon oxide film, and a conductive plate 7E which is the other electrode different from the above and which is, for example, a polycrystalline silicon film. It is configured. Switch MISFE for conductive plate 7E
An insulating film 21 made of a silicon oxide film thicker than the dielectric film 22 is provided at the end portion on the TQ side so as to relax the electric field at the end portion of the conductive plate 7E. An insulating film 23 made of a silicon oxide film is provided on the surface of the conductive plate 7E. Reference numeral 16D is a data line, which is connected to the n ⁺ type semiconductor region 13B of the drain when reading information.

Next, a method of manufacturing the memory cell of the DRAM will be described with reference to FIGS.

As shown in FIG. 60, p ⁻ type semiconductor substrate 1
P ⁻ type well region 3, field insulating film 4, p on the main surface of
After forming the mold channel stopper region 5, the EPROM 1
05 or the step of forming the gate insulating film 6 of the memory cells Q1, Q4 and Q5 of the EEPROM 107 (FIGS. 14 to 1).
In 6), the silicon oxide film 6 having a film thickness of about 500 Å is formed in the memory cell region of the DRAM. However, the silicon oxide film 6 is not used as the gate insulating film of the switch MISFETQ. At this point, n shown in FIG.
The type semiconductor region 20 and the insulating films 21 and 22 are not formed. Then, in the step of forming the n-type semiconductor region 20 which is the source and drain of the memory cells Q4 and Q5 of the EEPROM 107, the n-type semiconductor region 20 which is one electrode of the capacitor C is formed.

Next, in the step of forming the insulating film 21 of the memory cell of the EEPROM 107 (FIGS. 17 to 19), the insulating film 21 is formed in the region where the capacitive element C is provided.
At this point, the region where the dielectric film 22 is provided also covers the insulating film 2.
It is 1. The thickness of the insulating film 21 is 1000 to 20.
It is about 00Å. Next, in the step of etching the insulating film 21 of the portion where the tunnel insulating film 22 of the EEPROM 107 is formed (FIGS. 20 to 22), the insulating film 21 of the portion where the dielectric film 22 of the capacitive element C is provided is selectively selected. To remove. Next, the tunnel insulating film 22 of the EEPROM 107
The dielectric film 22 of the capacitive element C is formed in the step of forming. Next, the floating gate electrodes 7A and 7C of the EPROM 105 and the EEPROM 107 and the gate electrodes 7B of the MISFETs Q2, Q3 and Q6 of the peripheral circuits, respectively.
In the step of forming (FIG. 23 to FIG. 28), the plate electrode 7E of the capacitive element C is formed as shown in FIG. Next, the surface of the conductive plate 7E is thermally oxidized to form the insulating film 23 made of a silicon oxide film. The insulating film 23
May be formed of a silicon oxide film by a CVD method,
Alternatively, it may be formed by stacking a silicon oxide film formed by thermal oxidation and a silicon oxide film formed by CVD. The insulating film 23
Area, the area where the switch MISFETQ is provided, the CPU 100, the I / O 102, and the EPROM 105.
And MISF that constitutes the peripheral circuit of the EEPROM 107
The silicon oxide film 6 in the region where ET is provided becomes the thick insulating film 74. In addition, EPROM105 and EEP
A thick insulating film 23 is formed on the surfaces of the floating gate electrodes of the memory cells Q1 and Q4 of the ROM 107 and the gate electrodes 7B of their peripheral circuits. Therefore, after forming the insulating film 23 on the surface of the conductive plate 7E, for example, D
The portion of the capacitive element C of the RAM 109 is covered with a resist film,
The area where the switch MISFETQ is provided and the CPU 10
0, I / O 102, EPROM 105 and EEPROM
107, the thick insulating film 74 in the region where the MISFET forming the peripheral circuit of 107 is provided, the EPROM 105 and the EEPR.
The thick insulating film 23 formed on the surfaces of the floating gate electrodes of the memory cells Q1 and Q4 of the OM 107 and the gate electrodes 7B of their peripheral circuits is removed by etching. Then, after removing the resist film, the EPROM
105 and the surfaces of the floating gate electrodes 7A and 7C of the EEPROM 107 are thermally oxidized to form a second gate insulating film 8
A and 8C are formed.

Next, as shown in FIG. 62, the CPU 100
In the step of forming the gate insulating film 8D in the region of the I / O 102 (FIGS. 32 to 34), the gate insulating film 8D made of a silicon oxide film is formed in the region where the switch MISFETQ is provided. The gate insulating film 8D is made of EP
The second gate insulating film 8A on the surfaces of the floating gate electrodes 7A and 7C of the ROM 105 and the EEPROM 107,
It may be formed simultaneously with the step of forming 8C. Next, in the step of forming the control gate electrodes 9A and 9C of the EPROM 105 and the EEPROM 107, the gate electrode 9D of the CPU 100 and the I / O 102 region (FIGS. 32 to 43), the gate electrode 9D of the switch MISFETQ is formed. Next, EPROM 105 and EE
When the insulating film 10 is formed on the surfaces of the control gate electrodes 9A and 9C of the PROM 107, the switch MISF
An insulating film 10 is formed on the surface of the gate electrode 9D of the ETQ. After that, the sidewall 12 made of a silicon oxide film is formed. Next, the n ^- type semiconductor region 11B of the N-channel MISFET Q2 of the peripheral circuit of the EPROM 105 and the N-channel MISFET Q7 of the CPU 100 region.
In the step of forming the switch (FIGS. 47 to 49), the switch MI
N ⁻ which forms the channel side of the source and drain of SFETQ
The type semiconductor region 11B is formed. Next, the EPROM 10
5 and the memory cells Q1 and Q4 of the EEPROM 107 and their peripheral circuits MISFETs Q2 and Q5, and CPU1.
00 and N channel MISFET Q in I / O 102 area
Process of forming n ⁺ type semiconductor regions 13A and 13B which are a part of the source and drain of Q7 and Q8 (FIGS. 53 to 5)
At 5), the n ⁺ type semiconductor regions 13B of the source and drain of the switch MISFETQ are formed. After that, the passivation film 14, the connection hole 15, the data line 16D, the passivation film 17, the wiring 19, and a final passivation film (not shown) are formed.

As described above, the EPROM 10
5. In the process of forming the EEPROM 107, the DRAM 10
9 can be formed.

Next, an operational amplifier, an analog / digital converter, and the like included in the microcomputer shown in FIG.
The structures of the capacitive element and the resistive element in the digital / analog converter will be described. The resistance element and the capacitance element are used when the microcomputer performs analog amount processing.

FIG. 63 is a sectional view of a capacitance element and a resistance element provided in the operational amplifier, the analog / digital converter, and the digital / analog converter in the microcomputer shown in FIG.

In FIG. 63, R is a resistance element used when processing an analog amount, and C is a capacitance element used when processing an analog amount.

The resistance element R is composed of a resistance layer 7G made of a first-layer conductor (polycrystalline silicon film) on the field insulating film 4, and connection terminals 7H provided at both ends thereof. . Impurities are injected into the connection terminal 7H at a high concentration so that the connection terminal 7H can be ohmic-connected to the wiring 16 made of aluminum or the like. Further, a wiring 16 to which a fixed potential Vcc or Vss is applied is provided above the resistance layer 7G. The potential of the n ⁻ type well region 2 is fixed to Vcc or Vss. The capacitive element C includes a first electrode 7F made of a first-layer polycrystalline silicon film on the field insulating film 4, and a dielectric film 8F on the surface of the first electrode 7F.
And a second electrode 9F made of a second-layer conductive film provided on the first electrode 7F. The second conductive film is, for example, a silicide film (MoSi ₂ , TaSi ₂ , TiSi ₂ , WS) on a polycrystalline silicon film.
i ₂ ) is a laminated two-layer film. First electrode 7F
The second electrode 9F and the second electrode 9F are implanted with impurities at a high concentration to reduce the resistance. The wiring 16 is connected to each of the first electrode 7F and the second electrode 9F.

Next, a method of forming the resistance element R and the capacitance element C will be described. 64 to 66 are cross-sectional views in the manufacturing process of the resistance element and the capacitance element shown in FIG. 63.

In the method of forming the resistance element R and the capacitance element C, as shown in FIG. 64, the first-layer polycrystalline silicon film 7 is formed on the field insulating film 4 by, for example, CVD. At this point, no impurity for reducing the resistance is introduced into the polycrystalline silicon film 7. Next, a silicon oxide film 61 is formed, for example, by thermally oxidizing the surface of the polycrystalline silicon film 7 as a buffer film when introducing impurities into the polycrystalline silicon film 7 by ion implantation. Next, by ion implantation, one or more kinds of phosphorus (P), boron (B), arsenic (As), etc. are added to the polycrystalline silicon film 7 by, for example, 10 ¹² to.
Implant about 10 ¹⁶ atoms / cm ² . When the ion implantation is performed by thermal diffusion, the silicon oxide film 61 on the surface of the polycrystalline silicon film 7 is removed. Next, the impurity implantation mask 62 is formed on the predetermined region to be the resistance layer 7G.
The impurity implantation mask 62 may be formed of a resist film when the subsequent impurity implantation is performed by ion implantation, and may be formed of a silicon oxide film by CVD when performed by thermal diffusion. The polycrystalline silicon film 7 is formed on the memory cells Q of the EPROM 105 and the EEPROM 107.
Used as the floating gate electrodes 7A and 7C of Q1 and Q4, the gate electrodes 7B of the MISFETs Q2, Q3, Q5 and Q6 of their peripheral circuits, and also used as the connection terminal 7H of the resistance element R and the first electrode 7F of the capacitance element C. Therefore, after the impurity implantation mask 62 is formed, the second impurity implantation is performed to reduce the resistance of the polycrystalline silicon film 7. When the second impurity implantation is performed by thermal diffusion, the insulating film 61 not covered with the impurity implantation mask 62 is removed to expose the polycrystalline silicon film 7, and then thermal diffusion is performed. I do.

Next, as shown in FIG. 65, the resist film 6
3 is used to pattern the polycrystalline silicon film 7 to form the resistance layer 7G, the connection terminal 7H, and the first electrode 7F of the capacitive element C. At this time, the EPROM 105, the EEPROM
Floating gate electrodes 7A and 7C of memory cells Q1 and Q4 of 107, and MISFETQ of their peripheral circuits
Gate electrodes 7B of 2, Q3, Q5 and Q6 are also formed.
Next, FIG. 29, FIG. 30, FIG. 31 to FIG.
5, by the same process as FIG. 46, as shown in FIG.
Dielectric film 8F of capacitive element C, second electrode 9F, resistive element R
And the thin insulating film 10 which covers the surface of the capacitive element C 1st electrode 7F and 2nd electrode 9F is formed.

As a method of providing the resistance layer 7G with a predetermined resistance value, instead of implanting the predetermined impurity at a low concentration in the first impurity implantation as described above, the second impurity implantation is performed. Before or after performing, the impurity of the opposite conductivity type to the impurity introduced in the second impurity implantation may be implanted, or a predetermined amount of an insulator such as oxygen or nitrogen may be implanted to form the resistance layer 7G. The resistance value may be adjusted. Further, the resistance layer 7G may remain as the polycrystalline silicon film 7 into which impurities are not injected (however, the connection terminal 7H is injected with impurities to reduce the resistance), or a conductive layer other than the resistance layer 7G. 7A, 7B, 7C, 7
As with H and 7F, a high concentration impurity may be introduced.

As described above, the resistance element R and the capacitance element C can be formed by using the process of forming the EPROM 105 and the EEPROM 107.

Next, FIG. 67 shows one I / O cell in the I / O 102 of the microcomputer shown in FIG.

The I / O cell shown in FIG. 67 is a fluorescence table.
It is used to drive a display tube and the like. Fluorescent display tube
Is driven in a large voltage range of, for example, -40 to 0V.
Is in the normal operating range of the microcomputer
There is a large difference between 0V and 5V. So an example
For example, a voltage of about -40V is a depletion type P
Channel MISFETT_D1By microcomputer
After the voltage is converted to the normal operating voltage Vcc level of
Channel MISFETT_P1And N channel MISFETT
_N1Is input to the inverter consisting of
Done. The N-channel MISFET shown in FIG.
Q8 is the N-channel MISFETT _N1Equivalent to.
On the other hand, exit from the microcomputer to the fluorescent display tube.
The input data is P channel MISFETT_P2And N
Channel MISFETT_N2Via an inverter circuit consisting of
Depletion type P-channel MISFETT_D2
And an enhancement type P-channel MISFETT_P3
Output after voltage conversion by the inverter circuit consisting of
To be done.

Next, the P channel MI shown in FIG.
The sectional structure of SFET _P3 is shown in FIG. As shown in FIG. 68, the P-channel MISFETT _P3 is formed in the n ⁻ type well region 2I. This n ^-- type well region 2I
Has a lower impurity concentration than the n ⁻ type well region 2 and a junction depth deeper than the n ⁻ type well region 2. The MISFETT _P3 includes a gate insulating film 6 made of a silicon oxide film, a gate electrode 7I made of, for example, a polycrystalline silicon film, a p ⁻ type semiconductor region 11I which is a part of a source and a drain, and the source and drain. It is composed of a p ⁺ type semiconductor region 13C forming a part other than the p ⁻ type semiconductor region 11I. The p ⁻ type semiconductor region 11I is provided below the field insulating film 4 without the gate electrode 7I,
Further, it is provided so as to surround the periphery of the p ⁺ type semiconductor region 13C. The end of the gate electrode 7I extends on the field insulating film 4. Below the field insulating film 4 of the n ⁻ type well region 2I, the p ⁻ type semiconductor region 1 is formed.
An n-type channel stopper region 5I is provided apart from 1I.

Next, a method of manufacturing the P-channel MISFET T _P3 will be described with reference to FIGS. 69 to 70.

69 to 70 are sectional views in the manufacturing process of the P-channel MISFET T _P3 operating in the range of 0 to + 40V.

As shown in FIG. 69, the P-channel MISFETT _P3 is manufactured by first thermally oxidizing the surface of the p ^-- type semiconductor substrate 1 to form the silicon oxide film 64 in order to form the n ^-- type well region 2I. Form. Next, a silicon nitride film 66 is formed thereon as a mask for heat resistant oxidation, and this is used as a mask for ion implantation to perform ion implantation to form an n ⁻ type well region 2I. Next, a portion of the surface of the semiconductor substrate 1 exposed from the silicon nitride film 66, that is, the n ⁻ type well region 2I is thermally oxidized to form a silicon oxide film 65 slightly thicker than the silicon oxide film 64.

As shown in FIG. 70, the silicon nitride film 66 is formed.
Are removed to form a new silicon nitride film, and the silicon nitride film in the formation region of the n ⁻ type well region 2 is removed,
After ion implantation is performed to form the n ⁻ type well region 2,
A silicon oxide film 65 is formed on the surface by thermal oxidation. After this, the silicon nitride film is removed, and then, as shown in FIG.
As shown in FIG.
Using the film thickness difference of 5, p-type impurities are implanted into the portion of the semiconductor substrate 1 other than the n ⁻ type well region 2I and the n ⁻ type well region 2 to form the p ⁻ type well region 3. Next, the silicon nitride film 6 is used as a mask for thermal oxidation when the field insulating film 4 is formed on the silicon oxide films 64 and 65.
8 is formed. Next, as a mask for forming the n-type channel stopper region 5I, the n ^-- type well region 2I,
A resist film is formed on the n ⁻ type well region 2 and the p ⁻ type well region 3. Then, an n-type impurity is ion-implanted into the surface of the n ⁻ type well region 2I to form an n-type channel stopper region 5I. After that, the resist film 68 is removed.

Next, as shown in FIG. 72, a new resist film 69 is formed, and using the resist film 69 and the silicon nitride film 68 as a mask, ions are implanted into the surface of the n ⁻ type well region 2I to p ^−. The type semiconductor region 11I is formed. After that, the resist film 69 is removed. Next, as shown in FIG. 73, the p-type channel stopper is ion-implanted into the surface of the p ⁻ -type well region 3 by utilizing the film thickness difference between the silicon oxide film 64 and the silicon oxide film 65. Region 5 is formed. Thereafter, the exposed portions of the n ⁻ type well regions 2I, the n ⁻ type well regions 2 and the p ⁻ type well regions 3 from the silicon nitride film 68 are thermally oxidized to form the field insulating film 4. After this, the EP shown in FIGS.
Memory cell Q1 of ROM 105, MISFE of peripheral circuit
TQ2, Q3, memory MISFET Q4 of the memory cell of the EEPROM 107, switch M in the memory cell
N-channel MISFET Q5 for configuring ISFET or peripheral circuit, P-channel MISFET for peripheral circuit
In the step of forming Q6, the gate insulating film 6, the gate electrode 7I, the insulating film 10, and the sidewall 1 shown in FIG.
2, p ⁺ type semiconductor region 1 that forms part of the source and drain
Form 3C. Further, a first-layer passivation film 14, a connection hole 15, a wiring 16, a second-layer passivation film 17, a connection hole 18, a wiring 19 and a final passivation film (not shown) are formed.

The P channel MI shown in FIG. 68 is used.
As shown in FIG. 74, the SFET may be configured by using the gate insulating film 70 thicker than the gate insulating film 6.

FIG. 74 shows the P channel MI shown in FIG.
P-channel MISFET and N-channel MISF using gate insulating film 70 thicker than gate insulating film 6 of SFET
It is sectional drawing of ET.

In FIG. 74, a P channel MISFET is formed in the left n ^-- type well region 2I. This P
The gate insulating film 70 of the channel MISFET is made of a silicon oxide film and has a large film thickness of about 1000 to 2000Å. In the p ⁻ type well region 3, an N channel MISFET operating in the range of 0 to +40 V is formed. This N-channel MISFET has a gate insulating film 70.
And a gate electrode 7J made of, for example, a polycrystalline silicon film
And an n-type semiconductor region 5I forming part of the source and drain
And an n ⁺ type semiconductor region 13B which constitutes the source and drain other than the n type semiconductor region 5I. The gate electrode 7J also extends on the field insulating film 4. The n-type semiconductor region 5I is provided below the field insulating film 4 and is provided so as to surround the n ⁺ -type semiconductor region 13B. Further, between the n-type semiconductor region 5I and the n ⁻ type well region 2I and between the n-type semiconductor region 5I and the p-type channel stopper region 5, a p-type channel stopper region 5J having an impurity concentration higher than that of the p-type channel stopper region 5 is formed.
Is provided.

Next, the P channel MI shown in FIG.
FIG. 7 shows a method of manufacturing SFET and N-channel MISFET.
This will be described using 5.

FIG. 75 shows the P channel MI shown in FIG.
It is sectional drawing in the manufacturing process of SFET and N channel MISFET.

[0126] P-channel and N-channel MISFET illustrated in FIG. 75, FIG. 69 or in substantially the same steps as steps shown in FIG. 73, p ^- -type semiconductor substrate 1 n ^- -type well region 2I (and 2 ), P ^- type well region 3,
The n-type semiconductor region 5I, the p-type semiconductor region 5J, the p ⁻ type semiconductor region 11I, the p-type channel stopper region 5, and the field insulating film 4 are formed. After that, the silicon nitride film 68 (FIG. 71) which is a mask for thermal oxidation used when forming the field insulating film 4 and the silicon oxide film 64 thereunder,
65 is removed to expose the surfaces of the n ⁻ type well regions 2I (and 2) and the p ⁻ type well region 3 which are not covered with the field insulating film 4. Then, the exposed surfaces of the n ⁻ type well region 2I (and 2) and the p ⁻ type well region 3 are thermally oxidized to form the gate insulating film 70. After this, FIG.
P channel MISFET and N channel MI shown in FIG.
The gate insulating film 70 other than the region where the SFET is provided is removed by etching using a resist film. Then, after removing the resist film, the n ⁻ type well region 2I is again formed.
(And 2) and the surface of the p ⁻ type well region 3 is thermally oxidized,
For example, the gate insulating film 6 of the MISFET operating in the range of 0 to 5V is formed.

After this, the memory cell Q1 of the EPROM 105 shown in FIGS.
SFETQ2, Q3, memory MISFETQ4 of the memory cell of EEPROM107, N channel MISFETQ5 which is a switch MISFET in the memory cell,
In the step of forming the P channel MISFET Q6 of the peripheral circuit, the gate electrodes 7I and 7J, the insulating film 10, the sidewall 12, the n ⁺ type semiconductor region 13B which is a part of the source and drain of the N channel MISFET, and the P channel MIS.
The p ⁺ type semiconductor region 13C which is a part of the source and drain of the FET, the passivation film 14, the connection hole 15, the wiring 16, the passivation film 17, the connection hole 18, and the wiring 19
And a final passivation film (not shown) is formed.

As described above, the microcomputer according to the present embodiment has the M of the peripheral circuit of the EPROM 105.
Gate electrodes 7B of ISFETs Q2 and Q3, EEPROM
The gate electrodes 7B of the MISFETs Q5 and Q6 of the peripheral circuit 107 are formed by using the first-layer polycrystalline silicon film, but the first-layer polycrystalline silicon film is formed with the miniaturization of the semiconductor integrated circuit device. The thickness of the silicon film is reduced. Also,
The thickness of the silicon oxide film 10 on the surfaces of the gate insulating film 6 and the gate electrode 7B is also reduced. Therefore, at the time of ion implantation for forming the source and the drain, the impurity ions are removed by the silicon oxide film 10, the gate electrode 7, and the gate insulating film 6.
May leak through to the channel region.
The threshold values of the ISFETs Q2, Q3, Q5, Q6 may deviate from the predetermined values. To solve this,
If a thick silicon oxide film is formed on the first-layer polycrystalline silicon film by, for example, CVD, the silicon oxide film and the polycrystalline silicon film are patterned to form a gate electrode 7B. Since there is a thick silicon oxide film on the top, it is possible to prevent impurity ions from leaking into the channel region during the ion implantation.
However, as described above, the first-layer polycrystalline silicon film is the floating gate electrode 7A of the memory cell Q1 of the EPROM 105 and the floating gate electrode 7 of the memory MISFET Q4 of the memory cell of the EEPROM 107.
Since it is used as C, and the second gate insulating films 8A and 8C made of a thin silicon oxide film have to be formed on it, as described above, the thick oxide is simply formed on the polycrystalline silicon film by CVD or the like. There is a problem that a silicon film cannot be formed.

Therefore, a method for forming a source and a drain without leaking impurity ions into the channel region in the MISFET in which the gate electrode 7B is formed of the first-layer polycrystalline silicon film will be described next.

76 to 81 show a MISFET in which the gate electrode is formed of the first-layer conductive film, for example, a polycrystalline silicon film, and the source and drain can be formed without leaking impurity ions into the channel region. It is a figure for explaining a manufacturing method. 76 to 81, the area indicated by Q1 is the area where the memory cells of the EPROM 105 are formed, and the area indicated by Q2 is the EP.
This is a region where the N-channel MISFET of the peripheral circuit of the ROM 105 is formed.

A method of forming a MISFET without leaking impurity ions into the channel region is as shown in FIG. 76, in which a first-layer polycrystalline silicon film 7 is formed, and a predetermined impurity for achieving a low resistance is formed therein. After injecting
A thick silicon oxide film 71 is formed by VD.

Next, as shown in FIG. 77, EPROM1
The silicon oxide film 71 in the region where the memory cell Q1 of No. 05 is formed is removed by etching using, for example, a resist film as a mask. The resist film is removed after the silicon oxide film 71 is selectively removed. Next, the polycrystalline silicon film 7 is patterned by etching using a resist film (not shown) as a mask, and as shown in FIG.
The floating gate electrode 7A of the memory cell Q1 of the OM 105 and the gate electrode 7B of the MISFET Q2 are formed. The mask made of the resist film is removed after patterning. Gate electrode 7B of N-channel MISFET Q2
A thick silicon oxide film 71 is on the top.

Next, as shown in FIG. 79, the surface of the floating gate electrode 7A is thermally oxidized to form a second gate insulating film 8A. Next, as shown in FIG. 80, a second layer conductive film is formed on the semiconductor substrate (chip) 1 and patterned to form the control gate electrode (word line) 9A of the EPROM 105. Next, as shown in FIG. 81, the n-type semiconductor region 11A forming part of the source and drain of the memory cell Q1 and the MISFET of the peripheral circuit.
The n ⁻ type semiconductor region 11B forming part of the source and drain of Q2, the memory cell Q1, and the MISFET Q of the peripheral circuit.
The n ⁺ type semiconductor regions 13A and 13B forming the source and drain of the second region other than the above are formed.

In this way, the N-channel MISFET is
When the source and drain of Q2 are formed, since the thick silicon oxide film 71 is placed on the gate electrode 7B, it is possible to prevent impurities for forming the source and drain from leaking to the channel region.

As described above, according to this embodiment, the following effects can be obtained.

(1) In a semiconductor integrated circuit device constituting a microcomputer having a central processing unit on one semiconductor chip and a non-volatile memory for storing program data, dictionary data, etc. of the central processing unit, The nonvolatile memory electrically writes information,
A first non-volatile memory (EPROM 105) that erases the written information by irradiation of ultraviolet rays, and a second non-volatile memory (EEPROM 107) that electrically writes the information and electrically erases the written information.
By consisting of and, it is a large capacity and rewritable R
An OM can be obtained, and an electrically rewritable ROM can be obtained on the system.

(2) From the above (1), an EPROM is used for storing data that requires a large capacity although the number of times of rewriting is small.
By using the EEPROM 105, the EEPROM 107 is used for storing data that requires a large number of times of rewriting but requires only a small capacity or operation data that needs to be stored even after the power is cut off. It is possible to obtain a semiconductor integrated circuit device composed of a micro computer provided with a ROM having a high degree of freedom, which compensates for the drawback that the EEPROM 107 cannot be replaced and the drawback that the memory capacity of the EEPROM 107 is small.

That is, the EPROM 105 stores the program data and the dictionary data which require a large storage capacity, and stores the data even when the content of the data changes with time and the power is cut off like the control data for the feedback control. The control data that needs to be stored is EEPROM
Since the data can be stored in 107, the function of the semiconductor integrated circuit device including the one-chip microcomputer can be improved.

(3) A nonvolatile RAM can be obtained from the EEPROM 107 of (1) above.

(4) Since the SRAM is provided as the first RAM of the one-chip microcomputer, the RAM capable of high-speed data transfer can be obtained.

(5) Since the DRAM is provided as the second RAM of the one-chip microcomputer, a large capacity RA
M can be obtained.

(6) From the above (4) and (5), SRAM is used for storing data that requires a small capacity but needs high-speed data transfer, and high-speed data transfer is not necessary. D for storing data that requires a large storage capacity
By using the RAM, it is possible to obtain a RAM that compensates for the drawback that the SRAM cannot have a large capacity and the drawback that the transfer speed of the DRAM is slow.

(7) EPRO is formed on the first region of the semiconductor substrate 1.
The memory cell Q1 of M105 is formed, and the semiconductor substrate 1
In the second area different from the first area of the EEPROM 107
Forming a memory MISFET Q4 in the memory cell of
The switch MIS in the memory cell of the EEPROM 107 is provided in the third region adjacent to the second region of the semiconductor 1.
In a method of manufacturing a semiconductor integrated circuit device that constitutes a microcomputer including a step of forming a FET Q5,
Forming a first gate insulating film 6 on the surfaces of the first, second and third regions of the semiconductor substrate 1;
And a step of forming the source / drain 20 in a predetermined portion below the first gate insulating film 6 in the third region, and a floating gate electrode 7A on the first gate insulating film 6 in the first and second regions. 7C and the first of the third regions
Forming a gate electrode 7B on the gate insulating film 6; forming second gate insulating films 8A, 8C on the surfaces of the floating gate electrodes 7A, 7C in the first region and the second region; A step of forming control gate electrodes 9A and 9C on the second gate insulating films 8A and 8C in the first and second regions, and a source and a drain in predetermined portions below the first gate insulating film 6 in the first region. 11A,
13A is formed, and the steps are performed in the above order to form the EPROM 105. In the step of forming the EPROM 105, a step of forming an n-type semiconductor region 20 serving as a source and a drain of the EEPROM 107, and an n-type semiconductor region 20.
The EEPROM 107 can be formed only by adding a step of forming the tunnel insulating film 22 on the above.

(8) Memory cell Q1 of EPROM 105
Floating gate electrode 7A and EEPROM 10
In the memory cell of No. 7, the floating gate electrode 7C of the memory element Q4 is used as the first conductive layer (polycrystalline silicon film).
The first gate insulating film 6 of each of the elements Q1 and Q4 is formed in the same step, and the second gate insulating film 8A on the floating gate electrodes 7A and 7C of each of the elements Q1 and Q4, By forming 8C in the same step, it is possible to obtain the memory cells of the EPROM 105 and the EEPROM 107 by a small number of manufacturing steps.

(9) The gate insulating film 6 of the MISFETs Q2 and Q3 forming the peripheral circuit of the EPROM 105 and the MISFETs Q5 and Q6 forming the peripheral circuit of the EEPROM 107 is provided as the first memory cell Q1 of the EPROM 105.
Since the gate insulating film 6 and the first gate insulating film 6 of the memory MISFET Q4 in the memory cell of the EEPROM 107 are formed in the same process, the MISFETs of those peripheral circuits are formed.
The film thickness of the gate insulating film 6 of Q2, Q3, Q5, Q6 is increased, and the withstand voltage can be improved.

(10) CPU (logical unit) 100 and I /
The gate insulating film 8D of the MISFETs Q7 to Q9 for forming the O102 is the first gate insulating film 6 of the memory cell Q1 of the EPROM 105 and the first gate insulating film 6 of the memory MISFET Q4 of the memory cells of the EEPROM 107.
Since the gate insulating film 8D and the gate insulating film 6 are formed in separate steps, the film thicknesses of the gate insulating film 8D and the gate insulating film 6 can be independently set to optimum values.

(11) CPU (logical unit) 100 and I /
Since the gate electrodes 9D of the MISFETs Q7 to Q9 for forming the O102 are formed of the second conductive layer, that is, for example, a two-layer film in which a silicide film is laminated on a polycrystalline silicon film, the gate electrodes 9D are Resistance can be achieved.

(12) From the above (8) to (11), the EPROM 105 and the EEPRO including the peripheral circuits are included.
The voltage applied to the MISFET of M107 and the CPU
(Logic part) M for configuring 100 and I / O 102
Since the voltage applied to the ISFET can be set independently,
The structure of each element can be set independently.

(13) The DRAM 109 is replaced by the EEPROM 1
07 can be formed in the manufacturing process or almost the same process.

(14) From the above (12), the DRA
The dielectric film 22 of the capacitive element C of the memory cell of M109 is
Tunnel insulating film 22 of memory cell of EEPROM 107
Since it is formed to be very thin similarly to, the capacitance value of the capacitive element C can be increased.

(15) A large capacity DRAM can be obtained from the above (14), and a large capacity RAM can be obtained from this.

(16) The resistance element R forming the analog circuit is used as the memory cell of the EPROM 105 or EEPRO.
The floating gate electrodes 7A and 7C of the memory MISFET Q4 in the memory cell of M107 can be formed in the same step or almost the same step.
It can be formed in the same process as the memory cell of the PROM 105 or the EEPROM 107.

(17) Since the resistance element R and the capacitance element C are covered with the insulating film 10, stable resistance values and capacitance values can be obtained during the operation of the circuit.

(18) Since the well region under the resistance element R and the capacitance element C is electrically fixed, stable resistance and capacitance values can be obtained during the operation of the circuit.

(19) Since the upper portion of the resistance element R is covered with the conductive layer 19 having a fixed potential, another signal wiring can be extended on the conductive layer 19.

(20) From the above (16) to (19),
It is possible to easily obtain the stable resistance element R and capacitance element C required for processing the analog amount of the one-chip microcomputer.

(21) EPROM 105, EEPROM
The high breakdown voltage MISFET can be formed in substantially the same step as the step of forming 107 and the DRAM 109.

(22) Since the gate electrode 7I of the high breakdown voltage MISFET is extended to above the field insulating film 4 so that its end portion is on the field insulating film 4,
The breakdown voltage between the gate electrode 7I and the semiconductor substrate 1 can be improved.

(23) The withstand voltage of the source and drain can be improved by surrounding the semiconductor region with a high impurity concentration, which is a part of the source and drain of the high withstand voltage MISFET, with the semiconductor region with a low impurity concentration. it can.

(24) From the above (21) to (23), the high breakdown voltage MISFET used for the I / O 102 of the one-chip microcomputer can be easily obtained.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. There is no end.

For example, the microcomputer shown in FIG. 1 includes the SRAM 108 and the DRAM 109 as the RAM, but only one of the SRAM 108 and the DRAM 109 may be used.

[0163]

The effects of typical ones of the inventions disclosed by the present application will be briefly described as follows.

The low-concentration and high-concentration semiconductor regions are provided in the source / drain regions of the MISFET in the CPU and the I / O, respectively, and the low-concentration semiconductor region of the MISFET in the I / O is made higher than that in the CPU. This makes it possible to prevent the MISFET from being destroyed when an abnormally high voltage is applied. In addition, MISFE in the peripheral circuit
By making the gate insulating film of T thicker than that in the CPU, the withstand voltage can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a microcomputer of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a memory cell of SRAM 108 included in the microcomputer shown in FIG.

FIG. 3 E mounted on the microcomputer
3 is an equivalent circuit diagram showing a schematic configuration of a PROM 105. FIG.

FIG. 4 E mounted on the microcomputer
3 is an equivalent circuit diagram showing a schematic configuration of an EPROM 107. FIG.

FIG. 5 EPROM and EE of the microcomputer
MISFET which constitutes the logic part such as PROM and CPU
FIG. 6 is a cross-sectional view in the manufacturing process of.

FIG. 6 EPROM, EE of said microcomputer
MISFET which constitutes the logic part such as PROM and CPU
FIG. 6 is a cross-sectional view in the manufacturing process of.

FIG. 7 EPROM, EE of the microcomputer
MISFET which constitutes the logic part such as PROM and CPU
FIG. 6 is a cross-sectional view in the manufacturing process of.

FIG. 8 EPROM, EE of the microcomputer
MISFET which constitutes the logic part such as PROM and CPU
FIG. 6 is a cross-sectional view in the manufacturing process of.

FIG. 9 EPROM, EE of the microcomputer
MISFET which constitutes the logic part such as PROM and CPU
FIG. 6 is a cross-sectional view in the manufacturing process of.

FIG. 10: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 11 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 12 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 13: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 14 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 15 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 16: EPROM, E of said microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 17: EPROM, E of said microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 18: EPROM and E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 19 is an EPROM or E of the microcomputer.
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 20: EPROM and E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 21: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 22: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 23: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 24 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 25: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 26: EPROM and E of the above microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 27 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 28 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 29 is an EPROM or E of the microcomputer.
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 30: EPROM, E of said microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 31: EPROM, E of the above microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 32 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 33: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 34 is an EPROM or E of the microcomputer.
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 35 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 36 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 37 EPROM, E of the above microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 38 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 39 EPROM, E of the above microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 40 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 41 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 42 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 43 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 44 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 45 is an EPROM or E of the microcomputer.
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 46 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 47 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 48 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 49 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 50: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 51 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 52 EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 53: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 54: EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 55 is an EPROM, E of the microcomputer
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 56 is an EPROM or E of the microcomputer.
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 57 is an EPROM or E of the microcomputer.
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 58 is an EPROM or E of the microcomputer.
MISFE which constitutes the logic part such as EPROM and CPU
It is sectional drawing in the manufacturing process of T.

FIG. 59 is a cross-sectional view in the manufacturing process of the memory cell of the DRAM provided in the microcomputer.

FIG. 60 is a cross-sectional view in the manufacturing process of the DRAM memory cell provided in the microcomputer.

FIG. 61 is a cross-sectional view in the manufacturing process of the memory cell of the DRAM provided in the microcomputer.

62 is a sectional view in the manufacturing process of the memory cell of the DRAM provided in the microcomputer. FIG.

FIG. 63 is a cross-sectional view of a capacitance element and a resistance element in an operational amplifier, an analog / digital converter, and a digital / analog converter included in the microcomputer.

64 is a cross-sectional view in the manufacturing process of the capacitive element and the resistive element shown in FIG. 63.

FIG. 65 is a cross-sectional view in the manufacturing process of the capacitive element and the resistive element shown in FIG. 63.

66 is a sectional view in the manufacturing process for the capacitive element and the resistive element shown in FIG. 63. FIG.

67 is an equivalent circuit diagram showing one I / O cell in the I / O of the microcomputer shown in FIG. 1. FIG.

68 is a cross-sectional view of the P-channel MISFET shown in FIG. 67.

69 is a sectional view in the manufacturing process of P-channel MISFETT _P3 shown in FIG. 68. FIG.

70 is a cross-sectional view showing the manufacturing process of P-channel MISFET T _P3 shown in FIG. 68. FIG.

71 is a cross-sectional view in the manufacturing process of P-channel MISFETT _P3 shown in FIG. 68. FIG.

72 is a cross-sectional view in the manufacturing process of P-channel MISFETT _P3 shown in FIG. 68. FIG.

FIG. 73 is a cross-sectional view in the manufacturing process of P-channel MISFETT _P3 shown in FIG. 68.

74 is a cross-sectional view of a P-channel MISFET and an N-channel MISFET using a gate insulating film 70 thicker than the gate insulating film 6 of the P-channel MISFET shown in FIG. 68.

75 is a P-channel MISFET and N shown in FIG. 74;
It is sectional drawing in the manufacturing process of a channel MISFET.

FIG. 76 is a MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region.
FIG. 9 is a cross-sectional view illustrating the method of manufacturing the FET.

77 is a MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region.
FIG. 9 is a cross-sectional view illustrating the method of manufacturing the FET.

FIG. 78 is a MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region.
FIG. 9 is a cross-sectional view illustrating the method of manufacturing the FET.

FIG. 79 is a MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region.
FIG. 9 is a cross-sectional view illustrating the method of manufacturing the FET.

FIG. 80 is a MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region.
FIG. 9 is a cross-sectional view illustrating the method of manufacturing the FET.

FIG. 81 is a MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region.
FIG. 9 is a cross-sectional view illustrating the method of manufacturing the FET.

[Explanation of symbols]

1 ... Semiconductor chip (microcomputer), 100 ...
CPU, 101 ... OSC, 102 ... I / O, 103 ... S
I, 104 ... TIMER, 105 ... EPROM, 106
... voltage control circuit, 107 ... EEPROM, 108 ... SR
AM, 109 ... DRAM, 110 ... I / OBUS, Q1
... EPROM memory cells, Q2, Q3 ... Peripheral circuit M
ISFET, Q4 ... Storage element in memory cell of EEPROM, Q5, Q6 ... MIS of peripheral circuit of EEPROM
FET, Q7, Q9 ... CPU MISFET, Q8 ... M
ISFET, 6 ... First gate insulating film, 7A, 7B, 7C
... gate electrodes made of a first conductive film, 8A, 8C ...
A second gate insulating film on the floating gate electrode, 8
D ... CPU and first gate insulating film in I / O region, 9A,
9C, 9D ... Gate electrodes made of second-layer conductive film, 1
0 ... Thin silicon oxide film, 11A, 11B, 11C ... Low concentration layers of source and drain, 12 ... Side wall, 1
3A, 13B, 13C ... Source and drain high-concentration layers,
20 ... EEPROM n-type source and drain, 21 ... Thick gate insulating film, 22 ... Tunnel insulating film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/04 H01L 27/10 381 27/088 27/08 321A 27/092 321D 27/10 461 27/04 C 481 27/11 27/115 29/788 29/792 F term (reference) 5F038 AC05 AC17 EZ16 EZ20 5F048 AB01 AB03 AC03 AC10 BA01 BB05 BB08 BB12 BB16 BC06 BE03 BG01 BG12 BG13 BH07 DA25 5F083 AD21 BS27 EP02 EP22 EP23 EP32 EP63 EP ER25 JA35 JA36 PR33 PR36 PR43 PR44 PR53 PR54 ZA06 ZA07 ZA12 ZA13 5F101 BA01 BB05 BD07 BE02 BE05 BE06 BH04 BH21

Claims (10)

[Claims] 1. A first memory array comprising a plurality of electrically writable and erasable nonvolatile memory cells provided at intersections of a plurality of data lines and a plurality of word lines, and the plurality of nonvolatile memories. A first memory unit having a first control circuit for controlling cells, a CPU connected to the memory unit via an internal bus and operating at a power supply voltage, and a write or erase operation for the nonvolatile memory cell In the same semiconductor chip, a voltage control circuit for generating a voltage higher than the power supply voltage is built in, and the first control circuit uses the power supply voltage and the voltage generated by the voltage control circuit as operating power supplies, The semiconductor integrated circuit device characterized in that the film thickness of the gate insulating film of the first MISFET in the first control circuit is larger than the film thickness of the gate insulating film of the second MISFET in the CPU. . 2. An analog / digital converter including a capacitive element is further built in the semiconductor chip, and the capacitive element includes a first electrode, a second electrode, the first and second electrodes.
A dielectric film between the non-volatile memory cell and an electrode, wherein the dielectric film is thicker than the tunnel insulating film in the non-volatile memory cell, and the first electrode is floating in the non-volatile memory cell. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed of a conductive film in the same layer as the gate electrode. 3. The semiconductor integrated circuit device according to claim 2, wherein the second electrode is formed of a conductive film in the same layer as a control gate electrode in the nonvolatile memory cell. 4. A second memory array comprising a plurality of electrically writable non-volatile memory cells provided at intersections of a plurality of data lines and a plurality of word lines, and the plurality of non-volatile memory cells. A second memory unit having a second control circuit for controlling is further built in the semiconductor chip, and the structure of the non-volatile memory cell in the first memory array and the non-volatile memory cell in the second memory array. Differently, the second control circuit uses the power supply voltage and a voltage generated by the voltage control circuit as an operating power supply, and the thickness of the gate insulating film of the third MISFET in the second control circuit is the same as that in the CPU. 4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a thickness larger than that of the gate insulating film of the 2MISFET. 5. An insulating film having a first width and a second width is formed between a control gate electrode of the nonvolatile memory cell in the first memory cell array and a semiconductor substrate, and the first and second insulating films are formed. The semiconductor integrated circuit device according to claim 4, wherein the control gate electrodes of the non-volatile memory cells in the two memory cell arrays are formed in the same layer. 6. A CPU is provided at an intersection of a plurality of data lines and a plurality of word lines,
A memory unit having a plurality of memory cells each having an electrically writable and erasable floating gate electrode and a control gate electrode, and a control circuit for controlling the plurality of memory cells; and injecting or emitting electrons into the floating electrode. A voltage control circuit for generating a first voltage for performing is built in the same semiconductor chip, the first voltage is higher than a voltage supplied to the semiconductor chip, and the voltage control circuit is , A first MISF in a control circuit for generating the first voltage and controlling the plurality of memory cells
The thickness of the ET gate insulating film is the second MIS in the CPU.
A semiconductor integrated circuit device having a thickness larger than that of a gate insulating film of an FET. 7. The control gate electrode and the second
7. The semiconductor integrated circuit device according to claim 6, wherein the gate electrode of the MISFET is formed of the same conductive film. 8. The film thickness of the gate insulating film of the first MISFET is larger than the minimum value of the film thickness of the insulating film between the floating electrode in the memory cell and the semiconductor substrate. Item 8. A semiconductor integrated circuit device according to any one of items 7. 9. The semiconductor according to claim 1, wherein the semiconductor chip further includes an SRAM, and the CPU and the MISFET in the SRAM are formed by the same manufacturing method. Integrated circuit device. 10. The first control circuit includes an address decoder and a data input / output circuit coupled to the plurality of data lines and having a latch circuit. 7. A semiconductor integrated circuit device according to item 1.