JP3356795B2 - Generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a generator, and more particularly to a generator having an automatic parallel function for automatically matching output phases when a plurality of generators are connected in parallel and operated. It is.

[0002]

2. Description of the Related Art In a case where a plurality of generators are connected in parallel and operated, if the output voltages of the respective generators are not synchronized, a current difference from one generator to the other generator is caused by a voltage difference. Flows, and an overcurrent may flow into one of the generators, possibly destroying the components. Therefore, it is necessary to synchronize the output voltages of the respective generators.

For this reason, even when the generators of the same standard are operated in parallel, signal wiring for confirming the operation state of each other is required.
As shown in JP-A-782, it is necessary to devise a method of making a phase coincidence point so that the automatic synchronizer works quickly and surely. Further, as shown in, for example, Japanese Utility Model Application Laid-Open No. 62-145440, By using a special parallel operation adapter, one of the two units is operated as a master unit and the other unit is operated as a slave unit in parallel operation.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a special adapter or the like for matching the output phases of the respective generators in parallel operation. It is an object of the present invention to provide a generator which does not require a special device or a special operation.

[0005]

According to a first aspect of the present invention, there is provided a DC power supply circuit for outputting DC power.
An inverter circuit for converting the DC power output from the DC power supply circuit into AC power having a predetermined frequency, wherein an output target waveform signal of the AC power having the predetermined frequency serving as a reference for a switching operation of the inverter circuit. A target waveform forming means, an output voltage detecting means for detecting an AC output voltage output from the inverter circuit, an output current detecting means for detecting an AC output current output from the inverter circuit, Phase difference detecting means for detecting a phase difference between a zero crossing point of the output voltage waveform and a zero crossing point of the output current waveform, and, if the phase difference detected by the phase difference detecting means is a current delay, the delayed signal A new pulse is added to the reference pulse of the predetermined frequency, and when the phase difference is the current leading, Characterized by comprising a reference signal generating means for varying the frequency of the target waveform as the phase difference is reduced by thinning out a pulse to said reference pulse Te.

In the second invention, the addition and thinning of a new pulse in the reference signal generating means are performed by using the target waveform.
Is executed at predetermined intervals shorter than a half cycle of

[0007]

According to the first and second aspects of the invention, during parallel operation,
Since the output terminals of the generators operating in parallel are connected to each other, the output voltage detection means of the own device can detect the output voltage waveform of the partner device even if the own device is not generating power. The starting circuit starts to start its own device based on the detected zero cross point of the output voltage waveform of the partner device. If the phase of the output voltage of the own device and the output voltage of the partner device thus started are shifted from each other and a phase difference is generated, a relative current is generated, and this relative current is detected by the output current detecting means of the own device. Is detected. The own machine detects the phase difference between the AC output current detected by the output current detecting means and the AC output voltage detected by the output voltage detecting means by the phase difference detecting means. The reference signal generating means adds a new pulse to the reference pulse when the phase difference is current late, and thins out the reference pulse when the phase difference is current advance,
The phase difference is reduced by changing the frequency of the target waveform signal. Therefore, the above problem can be solved.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic overall configuration of an embodiment in which the present invention is applied to a small portable generator. In the figure, the output side of the alternator 1 is connected to the input side of the rectifying and smoothing circuit 2, the output side of the rectifying and smoothing circuit 2 is connected to the input side of the inverter circuit and the LPF 3, and the output side of the inverter circuit and the LPF 3 Is the voltage detection circuit 4
And a current detection circuit 5 connected to output terminals T1 and T1.

The output side of the voltage detection circuit 4 and the output side of the current detection circuit 5 are connected to the input side of the rectangular wave conversion circuits 6 and 7, and the output side of the rectangular wave conversion circuits 6 and 7 is connected to the phase difference detection circuit 8. I have. Further, the output side of the current detection circuit 5 is connected to a rise timing circuit (startup circuit) 11 via a comparison circuit 9 and a protection circuit 10. Phase difference detection circuit 8
Is an oscillation section 12, a frequency dividing circuit 13, and a sine wave forming circuit (target waveform forming means) 1 for outputting an output target waveform signal.
4, electronic volume circuit 15, low-pass filtering circuit (hereinafter, L
PF) 16 and a pulse width modulation circuit (hereinafter referred to as PW
Inverter circuit and LPF via M circuit 17)
3 is connected. In addition, the output side of the comparison circuit 9 is connected to the electronic volume circuit 15, and the rising timing circuit 11 includes a frequency divider 13, a sine wave generator 14,
Each is connected to the WM circuit 17.

Next, the operation of the generator shown in FIG. 1 will be briefly described.

The AC output from the AC generator 1 is rectified and smoothed by the rectifying and smoothing circuit 2 to become DC power. This DC power is converted into AC power of a predetermined frequency, for example, 50 Hz or 60 Hz, by an inverter circuit controlled by the PWM circuit 17 and the LPF 3, and is output from the output terminals T1 and T1 to the load. The output voltage appearing on the output line is detected by the voltage detection circuit 4, and the output voltage signal a output from the voltage detection circuit 4 has a sine wave shape as shown in FIG. The signal is input to the conversion circuit 6 and output to the rise timing circuit 11 and the phase difference detection circuit 8 as a rectangular wave signal b as shown in FIG. The signal b ′ output from the rectangular wave conversion circuit 7 according to the output current signal output from the current detection circuit 5 is a similar signal, and is input to the phase difference detection circuit 8.

The phase difference detection circuit 8 outputs both signals b and b '.
A phase difference voltage corresponding to the phase difference is output to the oscillation unit 12 and the output of the oscillation unit 12 is controlled. That is, the phase of the activated own machine and the phase of the other machine are compared to detect the advance or delay of the phase, and the detection result is output to the oscillation unit 12 as a leading signal or a lagging signal, as described later. Then, the frequency of the output signal from the oscillation unit 12 is finely adjusted. The pulse train signal output from the oscillating unit 12 is frequency-divided by the frequency dividing circuit 13 and input to the sine wave circuit 14 as a clock signal. The sine wave generating circuit 14 generates a stepped sine wave signal based on the clock signal, and the sine wave signal is generated by the electronic volume circuit 15.
Output to The electronic volume circuit 15 controls the passage of the sine wave signal and the degree of attenuation at the time of passage when the load current is in an overload state, and the sine wave signal thus controlled is supplied to the PWM circuit via the LPF 16. The PWM circuit 17 outputs a pulse width-modulated pulse using the sine wave signal having the predetermined frequency as a target waveform signal.

The gates of the FETs Q5 to Q8 constituting the inverter circuit and the bridge type inverter circuit of the LPF 3 are controlled by the pulse output from the PWM circuit 17, and a sine wave of a predetermined frequency which is a target waveform signal output from the LPF 16 It is output from output terminals T1 and T1 as AC power corresponding to the signal.

Next, each component of FIG. 1 will be described in detail with reference to FIGS. 3 to 15. Each of FIGS. 3 to 15 is a configuration diagram showing each component of FIG. 1 and its associated circuit.

In FIG. 3, reference numeral 1a denotes a three-phase output winding independently wound on a stator of the AC generator 1, and 1b denotes a single-phase auxiliary winding. The rotor (not shown) of the alternator 1 is formed with magnetic poles of multi-pole permanent magnets, and is configured to be rotationally driven by an engine (not shown). The output terminal of the three-phase output winding 1a is a bridge rectifier circuit 2 composed of three thyristors and three diodes.
a, and the output terminal of the bridge rectifier circuit 2a is connected to the smoothing circuit 2b. The bridge rectifying circuit 2a and the smoothing circuit 2b constitute a rectifying and smoothing circuit 2.

The output terminal of the single-phase auxiliary winding 1b is connected to a constant voltage supply device A1 having positive and negative output terminals E and F. The constant voltage supply device A1 includes two sets of rectifier circuits, a smoothing circuit, and a constant voltage circuit A1a. One set of each circuit works for current from one direction from the single-phase auxiliary winding 1b. For the current in the direction opposite to the direction, the other set of circuits operates, whereby positive and negative constant voltages are output to the output terminals E and F, respectively.

A2 is a thyristor control circuit, which includes a capacitor C1, resistors R1 to R3, and transistors Q1 and Q2.
And the like, and controls the input signal of the gate input circuit of each thyristor of the bridge rectifier circuit 2a according to the potential of the connection point between the resistors R1 and R2. Then, one end on the power input side is connected to the positive electrode output terminal E of the constant voltage supply device A1,
The other end is grounded together with the positive terminal of the smoothing circuit 2b, and the connection point K is connected to the output side of the engine speed detection circuit A3 shown in FIG.

The engine speed detection circuit A3 is shown in FIG.
Has a Zener diode D1 on the input side (G) of a constant voltage circuit A1a provided on the positive electrode output terminal E side of the constant voltage supply device A1 shown in FIG. 3, an inverting comparison circuit A3a, a NOR gate A3b, an inverter circuit A3c, and a transistor Q
3, the capacitor Q2, the capacitor C2, the diode D2, and the like. When the engine speed exceeds a certain number of revolutions, the potential of the transistor Q4 on the output side becomes "H" level, and when it is below, it becomes "L" level. Then, the anode side of the Zener diode D1 is connected via a resistor to the constant voltage supply device A1.
Is connected to the input terminal of the NOR gate A3b. The protection circuit 10 is connected to the input side of the NOR gate A3b. The protection circuit 10 includes a counter for detecting an overcurrent state of the generator. Is required), an "H" level signal is supplied to the NOR gate A3b. Further, the collector of the transistor Q4 is connected to the positive output terminal E of the constant voltage supply device A1, and its emitter is connected to the connection point K of the thyristor control circuit A2.

The output side of the smoothing circuit 2b is connected to the inverter circuit 3a shown in FIG. The inverter circuit 3a is configured by a bridge circuit including four FETs (field effect transistors) Q5 to Q8 and the like. FET Q5, Q
6, current detection resistors R7 and R8 are connected between the drain of the transistor 6 and the positive output line of the smoothing circuit 2b, respectively.
The output side of the inverter circuit 3a is connected to a low-pass filter (L
PF) 3b are connected to output terminals T1 and T1 to which a load (not shown) is connected. The LPF 3b includes coils L1 and L2 connected in series to the load, and a capacitor C3 connected in parallel to the load. The inverter circuit 3a and the LPF 3b are an inverter circuit and a LPF.
Construct F3. The connection points M and N between the current detection resistors R7 and R8 and the FETs Q5 and Q6 are connected to the current detection circuit 5
It is connected to the.

In FIG. 6, a current detecting circuit 5 inverts an input signal from point N, adds the inverted signal to an input signal from point M, amplifies the signal, and forms a sinusoidal waveform. Operational amplifier 5 for full-wave rectification of signal
2,53, diodes D7 and D8,
7, a resistor R9 for smoothing the output signal of D8, and a capacitor C
And an operational amplifier 54 for amplifying the output signal smoothed at 7. The output side of the current detection circuit 5 is connected to the input side of the rectangular wave conversion circuit 7 and to the input side of the comparison circuit 9.

The comparison circuit 9 comprises comparison circuits 91 and 92 and resistors R10, R11 and R12 connected in series between the positive output terminal E of the constant voltage supply device A1 of FIG. 3 and the ground. Connection point between resistors R10 and R11 and resistors R11 and R
Twelve connection points form the threshold values of the comparators 91 and 92, respectively. The output terminal 9T1 of the comparator 91 is connected to the current detection circuit 5
Is "H" only when the output voltage is higher than the threshold value of the comparator 91.
Level, and the output terminal 9T2 of the comparator 92 becomes “H” level only when the output voltage of the current detection circuit 5 is smaller than the threshold value of the comparator 92. The output terminals 9T1 and 9T2 of the comparison circuit 9 are connected to the control input terminal of the electronic volume circuit 15.

On the other hand, the rectangular wave conversion circuits 6 and 7 in FIG. 1 have the configurations shown in FIGS. 7 and 8, respectively.

The square wave converter 6 is a positive feedback amplifier using an operational amplifier. A sine wave signal having a phase corresponding to the phase of the AC output voltage is output from the voltage detection circuit 4 and is subjected to positive feedback amplification by the rectangular wave conversion circuit 6 to become a rectangular wave signal b having rapid rising and falling characteristics. Square wave conversion circuit 7
Is a high-amplification circuit using an operational amplifier. A sine wave signal having a phase corresponding to the phase of the load current is input from the current detection circuit 5 to the rectangular wave conversion circuit 7, and is output as a rectangular wave signal b 'having rapid rising and falling characteristics. .

FIG. 9 is a circuit diagram showing an example of the phase difference detection circuit in FIG.

The phase difference detecting circuit 8 has an exclusive OR circuit (hereinafter referred to as an XOR gate) 81,
The rectangular wave signals b, b from the rectangular wave conversion circuits 6, 7 are connected to the input side of the R gate 81 via connection terminals 8T1, 8T2.
'Is supplied. Further, the square wave signal b ′ from the square wave conversion circuit 7
The data is supplied to the data input terminal D of the flip-flop 84. Note that a capacitor 83 is provided between the output side of the buffer 82 and the ground.

On the other hand, the output side of the XOR gate 81 is connected to the CLK terminal of the D flip-flop 84, and the output of the output terminal Q bar and the rectangular wave signal b are transmitted to the XOR gate 8
5 is supplied to the input side. This XOR
The output side of the gate 85 is connected to the
Input NAND gates 87 and 88 are connected to the input side. Further, the output side of the XOR gate 81 is connected to the input side of the NAND gate 87 and directly to the two-input NAND gate 88.
Is connected to the input side. The output sides of the NAND gates 87 and 88 are connected to the oscillation section 12 shown in FIG. 1 via the connection terminals 8T3 and 8T4.

The rising timing circuit 11 shown in FIG.
Has a configuration as shown in FIG.

The rise timing circuit 11 has an inverter 111 connected to the output side of the rectangular wave conversion circuit 6 via a connection terminal 11T1.
2-input OR gate 112, 2-input NAND gate 113
And a two-input OR gate 114 are sequentially connected, and the output side of the OR gate 114 is connected to the CLK of the D flip-flop 115.
Connected to terminal. Further, the data terminal D of the D flip-flop 115 is connected to the reset terminal R of the binary counter 117 and the PWM circuit 1 via the inverter 116.
7, and the output terminal Q-bar is connected to the connection terminal 11T3 of the sine wave conversion circuit 14.

The output side of the inverter 116 is connected to the reset terminal RST of the binary counter 117. The clock terminal CLK of the counter 117 has 75
A pulse having a frequency of Hz (formed by dividing a constant frequency formed in the oscillation section 12) is supplied. An output terminal Q2 is connected to the input side of the OR gate 114. The output terminal Q3 is connected to the input side of the OR gate 112, respectively. The output side of the engine speed detection circuit A3 connected to the protection circuit 10 (FIG. 4) via the connection terminal 11T4 is connected to the NAND gate 113.
The input terminal of the inverter 116 is connected to the PWM circuit 17 via the connection terminal 11T5.

FIG. 11 is a circuit diagram showing an example of the oscillation section 12 in FIG.

The oscillating unit 12 includes a voltage-controlled oscillating circuit (hereinafter referred to as a VCO) 12 composed of a quartz oscillator or the like.
1 is provided. The output side of the VCO 121 is connected to the CLK terminal of the counter 123 via the inverter 122. The counter 123 is composed of a binary ripple counter, the RST terminal is grounded, and the output terminal Q
1 to Q12 are provided. Further, the inverter 12
2 is connected to one input side of each of NOR gates 125 and 126 via an inverter 124,
Their outputs are connected via an OR gate 127 to one input of a NAND gate 128. And
The output side of the NAND gate 128 is connected to the frequency divider 13 in FIG. 1 via the connection terminal 12T1.

On the other hand, the output terminal Q10 of the counter 123
Is connected to one input side of an AND gate 129a,
The output side of the AND gate 129a is connected to the data terminal D of the D flip-flop 129b. further,
Output terminal Q of D flip-flop 129b is connected to data terminal D of D flip-flop 129d via inverter 129c, and output terminal Q and output terminal Q of D flip-flop 129b are connected to NAND gate 129.
e is connected to the input side. The D flip-flop 129b, the inverter 129c, the D flip-flop 129d, and the NAND gate 129e constitute a conventionally known general one-shot multivibrator 129A. The output side of the one-shot multivibrator 129A, that is, the NAND gate 129e
Is connected to one input side of each of the OR gates 129f and 129g. The output side of the OR gate 129g is connected to the input side of the NOR gate 125, and the connection terminal 8T3 of the phase difference detection circuit 8 shown in FIG.
8T4 is connected to the input side of the NAND gate 129, and the output side of the NAND gate 129 is connected to the AND gate 1
29a is connected to the input side. Note that this oscillation unit 1
Reference numeral 2 constitutes a reference signal generating means for forming an output target waveform described later.

FIG. 12 is a circuit diagram showing an example of the frequency dividing circuit 13 in FIG.

The frequency dividing circuit 13 includes counters 131 and 13
2, an AND gate 133 and an OR gate 134. The output from the oscillation unit 12 of FIG. 11 is supplied to the clock terminal CLK of the counter 131 via the connection terminal 12T1. The output side of the AND gate 133, the frequency-divided output terminal Q6 of the counter 132, and the connection terminal 11T3 of the rise timing circuit 11 are connected to the input side of the OR gate 134. Also, the rising timing circuit 1
The 1 connection terminal 11T3 is also connected to the RST terminal of the counter 131. Divided output terminal Q4 of counter 132
Are connected to the sine wave conversion circuit 14 via the connection terminal 13T3. One input side of the AND gate 133 is connected to the 50/60 Hz switching circuit 135.

FIG. 13 is a circuit diagram showing an example of the sine wave conversion circuit 14 in FIG.

The sine wave conversion circuit 14 includes an up / down counter 141, an OR gate 142, and a multiplexer (4
051) 143, 3-input NAND gate 144, binary counter 145, inverter 146, voltage dividing resistor 14
7 and an inverter 148.

The terminal RST of the counter 141 is connected to the terminal RST of the counter 131 of FIG.
It is connected to the. Further, the output terminal Q3 of the counter 141 and the reset terminal RST of the counter 141 are connected to the input side of the OR gate 142, and the output side is connected to the terminal INH of the multiplexer 143. Output terminals Q0 to Q3 of the counter 141 are connected to terminals A, B, and C of the multiplexer 143, respectively.
It is connected to the input side of NAND gate 144. The output side of the NAND gate 144 is connected to the clock terminal CLK of the counter 145.

Further, the output terminal Q2 of the counter 145 is connected to one end of a voltage dividing resistor group 147 via an inverter 146. The connection points of the resistors forming the voltage dividing resistor group 147 are connected to the input terminals X0 to X7 of the multiplexer 143, respectively, and the other end of the voltage dividing resistor group 147 is grounded.

The output terminal Q1 of the counter 145 is connected in feedback to the terminal U / P of the counter 141 via the inverter 148. And the multiplexer 1
The output terminal X of 43 is connected to the electronic volume circuit 15 shown in FIG. 1 via the connection terminal 14T1, and the output terminal Q4 of the counter 145 is connected to the electronic volume 15 via the output terminal 14T2. The connection terminals 11T2 and 11T3 of the rise timing circuit 11 shown in FIG. 9 are connected to the terminals RST of the counters 145 and 141, respectively.

FIG. 14 is a circuit diagram showing an example of the electronic volume circuit in FIG.

The electronic volume circuit 15 includes an up / down counter 151, a multiplexer (4051) 152,
NOR gate 153, AND gate 154, inverter 155, NOR gates 156, 157, 158, 15
9, an operational amplifier 160, a voltage dividing resistor group 161 and the like. In addition, the output target waveform signal and the clock signal from the sine wave conversion circuit 14 are input from the connection terminals 14T1 and 14T2, respectively.
The output of 0 is output to the LPF 16 via the connection terminal 15T3. Further, one input side of the NOR gates 158 and 159 is connected to the output terminal 9T2 of the comparison circuit 9 shown in FIG. 6, and the other input side of the NOR gate 158 is connected to the output terminal 9T1 of the comparison circuit 9. The operation and the like of this electronic volume circuit are described in detail in Japanese Patent Application No. 3-184401 by the applicant of the present invention, and the description is omitted here.

FIG. 15 is a circuit diagram showing an example of the LPF 16, the PWM circuit 17, and the voltage detection circuit 4 in FIG.

The output side of the electronic volume circuit 15 is LP
It is connected to the inverting input terminal (-) of the operational amplifier of F16. The LPF 16 converts a step-like sine wave output from the electronic volume circuit 15 into a smooth sine wave. The output side of the LPF 16 is connected to the inverting input terminal (-) of the operational amplifier of the distortion correction circuit A6, and the output side of the voltage detecting circuit 4 is connected to the non-inverting input terminal (+) of the operational amplifier. The distortion correction circuit A6 corrects a sine wave level output from the electronic volume circuit 15 via the LPF 16 with a detection signal output from the voltage detection circuit 4, and outputs a corrected sine wave signal.

Further, 171 is a rectangular wave oscillation circuit,
The frequency of the rectangular wave oscillated by the rectangular wave oscillating circuit 171 is set to a value significantly higher than the frequency of the sine wave output from the LPF 16. Note that this frequency is formed by dividing the constant frequency formed in the oscillating unit 12.
The output side of the rectangular wave oscillation circuit 171 is connected to an integrating circuit 172, which integrates the rectangular wave and converts it into a triangular wave signal.

The output from the LPF 16 and the distortion correction circuit A6
The sine wave signal corrected by the above and the triangular wave signal output from the integration circuit 172 are superimposed and supplied to the inverter 170 (pulse width modulation circuit). Inverter 170 has a predetermined threshold, and outputs a signal of “L” level when a signal having a level exceeding the threshold is input, and outputs “H” when a signal of a level lower than the threshold is input. It outputs a level signal to form a so-called pulse width modulation (PWM circuit) signal, and is constituted by, for example, a C-MOS gate IC having a fixed threshold value for an input signal to a gate terminal.

The output side of the inverter 170 is input to one input terminal of the NAND gate 174 via the inverter 173 and is also input directly to one input terminal of the NAND gate 175 as it is (the AND gate 177 will be described later). . The output terminal J of the NOR gate 172 of the engine speed detection circuit 17 shown in FIG. 10 is connected to the other input terminal of the NAND gate 174 and the input terminal of the NAND gate 175.

The output terminal of the NAND gate 174 is connected to a first push-pull amplifier comprising transistors Q9 and Q10. The collector of the transistor Q9 is
The collector of the transistor Q10 is connected to the positive output terminal E of the constant voltage supply A1, and the negative output terminal F of the constant voltage supply A1.

The output terminal of the first push-pull amplifier circuit is connected to a connection point between the anode of the diode D7 and the cathode of the diode D8. The cathode of the diode D7 is connected to the positive output terminal E of the constant voltage supply A1, and the anode of the diode D8 is connected to the negative output terminal F of the constant voltage supply A1. The diodes D7 and D8 are for absorbing a surge generated by a pulse transformer described later.

The anode of the diode D7 and the diode D
The connection point 8 with the cathode is connected to one end of each of primary coils L3 and L4 of the pulse transformers A and C via a capacitor C4 for cutting low frequency components. The other ends of these primary coils L3 and L4 are connected to the negative output terminal F of the constant voltage supply device A1. The capacitor C4 is set to a constant value that allows only a high frequency PWM circuit carrier frequency signal and does not allow a low frequency component to pass.

Similarly, the output terminal of the NAND gate 175 is connected to a second push-pull amplifier comprising transistors Q11 and Q12. The output terminal of the second push-pull amplifier is connected to the anode of the diode D9 and the diode D9. It is connected to the connection point of D10 with the cathode. This connection point is connected to the primary side coil L5 of the pulse transformers B and D via a capacitor C5 set to a constant value such that only the carrier frequency signal of the PWM circuit passes and the low frequency component does not pass similarly to the capacitor C4 described above. , L6.

Next, the FETs Q5 to Q5 of the inverter circuit 3a
A drive circuit connected to each gate terminal of Q8 will be described.

One end on the secondary side of the pulse transformer A is
, A resistor R5, a demodulating capacitor C6,
FET through a parallel circuit of resistor R6 and diode D13
Connected to the gate terminal of Q5, while the pulse transformer A
Is connected to the source terminal of the FET Q5. Capacitor C6, resistor R6 and diode D1
3 is connected to the other end on the secondary side of the pulse transformer A via a series circuit of zener diodes D5 and D6. The diode D13 is connected so that the anode is on the gate terminal side of the FET Q5, and the Zener diodes D5 and D6 are connected so that the anodes face each other. Between the secondary sides of the pulse transformers B, C, and D and the gate terminals of the corresponding FETs Q6 to Q8, the secondary side of the pulse transformer A and F
A circuit exactly the same as the circuit provided between the gate terminal of ETQ5 is provided.

The two output lines of the inverter circuit 3a are connected to the input terminals G of the voltage detection circuit 4 shown in FIG.
Connected to. That is, the input terminal G is connected to the resistor R1
3, one end of a series circuit of R14 and one end of a series circuit of resistors R15 and R16 are connected. On the other hand, the other ends of these resistance series circuits are connected to the positive output terminal E of the constant voltage supply device 5. Connection point of resistors R13 and R14 and resistor R1
5 and R16 are connected to the positive input terminal and the negative input terminal of the operational amplifier 41 via resistors R17 and R18, respectively, and a high frequency component cutting capacitor C8 is connected between the two connection points. Is connected. The positive input terminal of the operational amplifier 41 is grounded via a high frequency component cutting capacitor C9. Further, the output terminal of the operational amplifier 41 is connected to the non-inverting terminal (+) of the distortion correction circuit A6 and the input side of the rectangular wave conversion circuit 6 via a resistor.

The detailed operations (A) and (B) of this embodiment having the above components will be described with reference to FIGS.

(A) Operation of Starting Automatically with Phase Matching First, the case of starting alone will be described. Since there is no output voltage input to the voltage detection circuit 4 at the time of the start operation of the isolated operation, a rectangular wave signal for adjusting the timing for starting the target waveform output is obtained from the output b of the operational amplifier of the rectangular wave conversion circuit 6. Cannot be obtained, and it is also unknown whether the signal is at the “H” level or the “L” level.
That is, the operational amplifier output of the square wave conversion circuit 6 is 0
[V], because it is unclear which of the “H” level and the “L” level will be rectangularly converted due to the offset of the output of the operational amplifier itself. In this embodiment, when the output b of the rectangular wave conversion circuit 6 is not a rectangular wave signal at the time of the start operation, and is either the “H” level or the “L” level, it can be independently activated by the rise timing circuit 11. .

In FIG. 10 and FIG. 16A, when a signal b of, for example, "H" level is input from the rectangular wave conversion circuit 6 to the rising edge timing circuit 11 to the connection terminal 11T1 (the signal b of "L" level). Figure 1 for some cases
6 (b). ), The signal b of which is
, And becomes an “L” level signal W1 to be input to one terminal of the OR gate 112. On the other hand, in a state where the engine is stopped (or before the rotation speed rises to the predetermined rotation speed), the output signal W of the engine rotation speed detection circuit A3 is output.
2 is at the “L” level, and therefore the inverter 11
6 becomes “H” level, the reset terminal R of the D flip-flop 115 and the binary counter 1
The reset signals RST are input to the reset terminals RST, and are maintained in a reset state. Next, when the engine starts and its rotation speed reaches a predetermined rotation speed, the output signal W2 of the engine rotation speed detection circuit 118 changes from the "L" level to the "H" level (at the time of FIG. 16A). t1). In response, the output signal W3 of the inverter 116 becomes “L” level, and is input to the reset terminal R of the D flip-flop 115 and the reset terminal RST of the binary counter 117. As a result, the reset states of the D flip-flop 115 and the binary counter 117 are released.

On the other hand, the clock terminal CL of the counter 117
Since a pulse having a frequency of 75 Hz is externally supplied to K, the output terminal Q2.
The 4 Hz signal W5 is further output from the output terminal Q3, and the 4.7 Hz signal W4 having a double cycle is output. Therefore, at time t2, the input side of the OR gate 112 receives the “L” level signal W1 and the signal W4, and the output thereof becomes the “L” level signal W6. Further, at time t2, the signal W6 at the "L" level and the signal W2 at the "H" level are input to the NAND gate 113, so that the output signal W7 is at the "H" level.

As a result, the OR gate 114 outputs “H”
The level signal W7 and the aforementioned 9.4 Hz signal W5 are input, and at time t2, the output signal W8 goes to “H” level and is input to the clock terminal CLK of the D flip-flop 115. On the other hand, since the above-mentioned "H" level signal W2 is input to the data terminal D of the D flip-flop 115, the "H" level signal W9 is output to the output terminal Q bar of the D flip-flop 115 at time t2. Is output. Then, the "H" level signal W9
And "L" level signal W3 are connected to connection terminals 11T3, 11T.
The signal is supplied to the sine wave conversion circuit 14 via T2.

At time t3, signal W4 attains "H" level, so that output signal W6 of OR gate 112 attains "H" level and output signal W7 of NAND gate 113 attains "L" level. On the other hand, since the signal W5 is at the “L” level, the output signal W8 of the OR gate 114 is changed from the “H” level to the “L” level, but the output signal W9 of the D flip-flop 115 remains at the “H” level. is there.

At time t4, the signal W5 changes from "L" level to "H" level, the output signal W8 of the OR gate 114 changes from "L" level to "H" level, and the clock terminal CLK of the D flip-flop 115 Is input to That is, since the clock of the D flip-flop 115 changes from the “L” level to the “H” level, the inverted output signal W9 changes from the “H” level to the “L” level.
As a result, the signal W9 and the signal W3 become “L” level, and the sine wave forming circuit 1 is connected via the connection terminals 11T3 and 11T2.
4 to release the reset state of the counters 141 and 145 of the sine wave conversion circuit 14 shown in FIG.

FIG. 16 (b) shows a start-up operation when an "L" level signal b is input to the connection terminal 11T1 from the rectangular wave conversion circuit 6, and the signal b is inverted by the inverter 111, The signal becomes an “H” level signal W1 and is input to one terminal of the OR gate 112. When the output signal W2 of the engine speed detection circuit 3A changes from "L" level to "H" level (time t1 in FIG. 16B), the D flip-flop 115 and the binary counter The reset state of 117 is released.

The clock terminal CLK of the counter 117
As described above, a pulse having a frequency of 75 Hz is supplied from the outside, and a signal W5 of 9.4 Hz is output from the output terminal Q2.
However, since a 4.7-Hz signal W4 is further output from the output terminal Q3, at time t1, the input side of the OR gate 112 receives the "H" level signal W1 and the "L" level signal W4. And the output signal W
6 is at the “H” level. Further, at time t1, the NAND gate 113 supplies the signal W6 of "H" level.
And the signal W2 are input, the signal W7 at the output thereof becomes "L" level.

As a result, at time t1, the OR gate 11
4, the signal W7 of "L" level and the signal W5 of 9.4 Hz are input, and the signal W8 becomes "L" level and D
The clock is input to the clock terminal CLK of the flip-flop 115. On the other hand, the data terminal D of the D flip-flop 115
, The “H” level signal W2 is input, and at time t1, the “H” level signal W9 is output to the output terminal Q bar of the D flip-flop 115. Then, the "H" level signal W9 and the "L" level signal W3 are supplied to the sine wave conversion circuit 14 via the connection terminals 11T3 and 11T2.

At time t2, the signal W5 changes from "L" level to "H" level, the output signal W8 of the OR gate 114 changes from "L" level to "H" level, and the clock terminal CLK of the D flip-flop 115 Is input to Therefore, the inverted output signal W9 changes from “H” level to “L” level. As a result, similarly to the case where the output of the rectangular wave conversion circuit 6 is at the “H” level, the signals W9 and W3
Become "L" level and the connection terminals 11T3, 11T2
Is supplied to the sine wave conversion circuit 14 via the, and the activation of the present power supply device is started.

Next, a case will be described in which the output terminal of the generator to be started from now is connected to the output terminal of the generator whose power generation has already been obtained, and the generator is started in the parallel operation in the parallel connection state. At the time of parallel operation, the self-machine is started by ascertaining timing so as to synchronize with the output voltage waveform of the partner machine whose power generation output has already been obtained. In this embodiment, the synchronization timing is defined as a zero cross point at the time of a negative → 0 → positive change in the output voltage waveform of the partner device. In other words, a generator (referred to as its own machine) that starts a power generating operation later on a generator (referred to as a counterpart machine) that is generating power first is a counterpart machine illustrated in FIG. 0 when output voltage waveform (sine wave) changes from negative voltage to positive voltage
The point in time [V] (so-called zero cross point) is detected, and FIG.
As shown at 0 (B), the output of the own device is started from this point.

In FIG. 10 and FIG. 16 (c), a rectangular wave signal b based on the output voltage waveform of the other device is connected to the connection terminal 11T.
When the signal b is input to 1, the signal b is inverted by the inverter 11 to become a signal W1 and input to one terminal of the OR gate 112. Before time t1, the input side of the OR gate 112 has a signal of the frequency of the output voltage of the counterpart device, for example, a signal W1 of 50 Hz and a signal W of the "L" level.
4 is input, and the output signal W6 becomes a signal of 50 Hz.

Here, at time t1, when the output signal W2 of the engine speed detection circuit 3A changes from "L" level to "H" level, the reset states of the D flip-flop 115 and the binary counter 117 are released. At the same time, the signal W of 50 Hz is supplied to the NAND gate 113.
6 and the "H" level signal W2 are input, and the output signal W7 changes from the "H" level to the "L" level.
As a result, at time t1, the “L” level signal W7 and the “L” level signal W5 are input to the OR gate 114, and the signal W8 becomes “L” level, and the clock terminal CLK of the D flip-flop 115 Is entered. On the other hand, D
Since an “H” level signal W2 is input to the data terminal D of the flip-flop 115, an “H” level signal W9 is output to the output terminal Q bar of the D flip-flop 115 at time t1. Then, the "H" level signal W9 and the "L" level signal W3 are connected to the connection terminal 11T.
The signal is supplied to the sine wave conversion circuit 14 via 3, 11T2.

At time t2, the output voltage waveform of the counterpart device becomes a zero cross point at the time of a change from negative → 0 → positive, and signal W1 changes from “H” level to “L” level, so that signal W6 changes to “L” level. Level. Further, as a result of the signal W7 changing from the “L” level to the “H” level, the signal W8 changes from the “L” level to the “H” level and is input to the clock terminal CLK of the D flip-flop 115. Since the signal W2 at the "H" level is input to the data terminal D of the D flip-flop 115, at time t2, the signal W9 from the output terminal Q bar of the D flip-flop 115 changes from the "H" level to the "L" level. Become a level. And the signal W
9 and the signal W3 become "L" level, and the connection terminal 11T
The power is supplied to the sine wave conversion circuit 14 via 3, 11T2, and the activation of the power supply device is started.

In the present embodiment, as described above, in order to enable start-up at the time of independent operation, a signal W4 having a frequency of 4.7 Hz and a signal W5 having a frequency of 9.4 Hz are used as a start-up timing signal (self-timing). I was interrupted as
In order to prevent the timing signal from adversely affecting the start-up during the parallel operation, the operation is performed such that the detection of the output voltage waveform of the partner device always takes priority during the parallel operation. That is, when the output signal W2 of the engine speed detection circuit 3A changes from the “L” level to the “H” level, the other machine is in operation, and the voltage detector 4 detects, for example, 50 Hz.
Is detected and the signal b is input to the inverter 111 as a rectangular wave of 50 Hz as shown in FIG. 16C, the frequency of the start timing signal is set lower than the frequency of the output voltage waveform of 50 Hz. Therefore, as shown in FIG. 16C, the OR gates 112 and 114 output the output signals W6 and W8 in which the signal of 50 Hz is prioritized over the above-mentioned start timing signal.

(B) Automatic adjustment of phase shift during operation During the parallel operation, the phase difference between the voltage phase of the other apparatus being started and the voltage phase of the own apparatus, that is, the voltage detection circuit 4 and the current detection circuit 5 The operation for adjusting the deviation between the detected voltage phase and the current phase is as follows.

First, although the operation of the phase difference detection circuit 8 in FIG. 9 will be described later, if there is no difference between the two phases, an "H" level signal is output from both terminals 8T3 and 8T4. If there is a deviation, the terminal 8T
3 and a pulse train signal from the terminal 8T4 when the current is advanced. And
This output signal is transmitted through connection terminals 8T3 and 8T4 as shown in FIG.
Is supplied to the oscillating unit 12 shown in FIG.

In FIG. 11, the oscillation pulse signal (5 MHz) from the OSC 121 of the oscillation section 12 is inverted by the inverter 122, and the clock signal C shown in FIG.
It is supplied to the clock terminal CLK of the counter 123 as LK bar. As a result, the output terminal Q1 of the counter 123
From the frequency (2.5 MHz) of the oscillation signal.
z) is output, and the output terminal Q10 outputs a signal obtained by dividing the signal F1 by 1/512 (about 5K).
Hz) is output.

The signal F1 is input to one input terminal of the NOR gate 126 and to each clock terminal CLK of the D flip-flops 129b and 129d, and the output terminal Q1
The signal from 0 is input to one input terminal of the AND gate 129a. Further, the output of the inverter 122 is inverted by the inverter 124 to become an inverted signal F2 of the clock signal CLK bar (FIG. 17). Further, the signal F2 and the signal F1 are input to the NOR gate 126,
The output of the OR gate 126 is the signal F3 (2.5 MHz)
(FIG. 17).

When there is no difference between the voltage phase and the current phase, for example, when an "H" level signal is input from the phase difference detection circuit 8 to both of the connection terminals 8T3 and 8T4, each of the OR gates 129f and 129g "H" level is supplied to one input terminal. Accordingly, the output of the OR gates 129f and 129g is constant at the "H" level regardless of the output level of the NAND gate 129e at the preceding stage (output of the one-shot multivibrator 129A). That is, the signal F6 input to one input terminal of the NAND gate 128 and the signal input to one input terminal of the NOR gate 125 both become “H” level. As a result, the signal F4 output from the NOR gate 125 is
The “L” level is constant regardless of the level of the signal F2. Therefore, the output signal F5 of the OR gate 127
Is output to the next-stage NAND gate 128 without changing the signal F3.

At this time, since the signal F6 at the "H" level is input to the other input side of the NAND gate 128 as described above, the signal F7 output from the NAND gate 128 is obtained by inverting the signal F3. Signal, which is output from the oscillation unit 12 via the connection terminal 12T1 to the frequency divider 1
Output to 3 side.

After that, as described above, the signal F7 passes through the frequency dividing circuit 13, the sine wave converting circuit 14, the electronic volume circuit 15, the LPF 16, and the PWM circuit 17, and is converted into the signal F7 by the LPF of the inverter and the LPF 3. The corresponding sine-wave AC power is output from the output terminals T1 and T1.

However, during the actual parallel operation, the operation is not continued in a state where the voltage phases of the other apparatus and the own apparatus are in phase and the frequencies are the same as in the above-described normal state. The operation is continued while the adjustment operation of the phase matching is delicately repeated within a range of ± 0.1 Hz.
Therefore, the adjustment operation of the phase matching will be described next.

In this embodiment, the signal F shown in FIG.
A new pulse is added to each of the three pulses every predetermined number of times (once every 500 pulses) or thinned out to adjust the phase matching. That is, in the case of the current lag, a new pulse is added to the reference pulse signal F3 to slightly increase the frequency,
In the case of the current advance, the frequency of the signal F3 is slightly reduced by thinning out the pulse of the signal F3. Hereinafter, this point will be described in detail.

(B-1) Adjustment operation at the time of current lag In the parallel operation, if there is a phase shift between the voltage phase of the activated own machine and the voltage phase of the other machine, the phase shift is advanced. A phase difference also occurs between the voltage phase and the current phase detected by the voltage detection circuit 4 and the current detection circuit 5 corresponding to the phase difference of the delay. For example, when the detected current phase is later than the voltage phase, the following adjustment operation is performed.

When the current is delayed, the rectangular wave signal b and the rectangular wave signal b '(current delayed) as shown in FIG. 18A are respectively applied to the connection terminals 8T1 and 8T2 of the phase difference detection circuit 8 in FIG. Supplied. Then, from the output side of XOR81,
A signal S whose pulse width is the phase difference between the signals b and b '
81 (FIG. 18A) is output. Thus, the magnitude of the phase difference between the signals b and b 'is detected. The signal S81 is supplied to the clock terminal CLK of the D flip-flop 84.
And one input terminal of each of NAND gates 87 and 88. At the same time, the signal b 'is delayed by the buffer 82 and the capacitor 83 so that the D flip-flop 8
4 is input to the data terminal D.

The reason why the signal b 'is delayed by the buffer 82 and the capacitor 83 and input to the data terminal D of the D flip-flop 84 is that the signal S81 is input to the D flip-flop 84 as a clock before being input to the D flip-flop 84. This is to prevent the output of the output terminal Q bar from becoming inaccurate when the signal b 'is input to the data terminal of the above.

From the output terminal Q bar of the D flip-flop 84, the signal whose phase is advanced among the signals b and b ', that is, the signal b is output. Therefore, XOR85
Since the same pulse train as the signal b is input to both input sides, the output S85 of the XOR 85 becomes "L" level (FIG. 18A), which is the other input terminal of the NAND gates 87 and 88. Is input to

As a result, a signal S87 of, for example, 100 Hz having a pulse width of the phase difference as shown in FIG. 18A is obtained from the output side of the NAND gate 87.
NAND gate 88 outputs a signal S at a constant "H" level.
88 is output. These NAND gates 87, 88
Are supplied to the connection terminals 8T3 and 8T4 of the oscillation unit 12 shown in FIG.

In FIG. 11, the NA of the phase difference detection circuit 8 is
When the outputs S87 and S88 of the ND gates 87 and 88 are supplied to the connection terminals 8T3 and 8T4, respectively,
Of the OR gate 129f receives an "H" level signal S88 from the NAND gate 88, so that it is independent of the output level of the preceding NAND gate 129e (the output of the one-shot multivibrator 129A). Instead, the signal F6 output from the OR gate 129f is kept at the "H" level.

On the other hand, both signals S8 from the phase difference detection circuit 8
7, S88 are supplied to the NAND gate 129. Therefore, the output of the NAND gate 129 becomes an inverted signal (100 Hz) of the signal S87 and is supplied to one input side of the AND gate 129a. AND gate 1
As described above, a signal of 1/512 frequency division of the signal F1 is input to the other input side of the signal 29a.
The D gate 129a has a significantly different frequency of 100 Hz.
And the pulse of about 5 KHz. The output pulse of the AND gate 129a is a one-shot multivibrator (D flip-flop 129).
b) The output of the one-shot multivibrator (NAND gate 129e) is supplied to
It is supplied to one input terminal of the R gate 129g. At the same time, the signal S87 (100 Hz) is input to the other input terminal of the OR gate 129g. As a result, OR
The output signal F4 of the NOR gate 125 via the gate 129g is, as shown in FIG. 19A, every 5 kHz (5 kHz for 2.5 MHz: once every 500 times).
It becomes the “H” level (P1 in FIG. 19A). These signals F3 and F4 are input to the OR gate 127,
As shown in FIG. 19A, the output of the R gate 127 outputs a signal F5 obtained by adding a pulse P1 to the signal F3.
Is output. This operation is performed every 5 KHz during the time when the connection terminal 8T3 is at the "L" level.

After that, the signal F5 is supplied to the NAND gate 128 together with the signal F6 of the "H" level, and becomes a signal F7 which is an inverted signal of the signal F5, and is connected to the connection terminal 12T1.
Is output to the frequency dividing circuit 13 side. The signal F7 is frequency-divided by the frequency divider 13 and further converted into a sine wave by the sine wave generator 14 in accordance with the pulse addition. As a result, the electronic volume circuit 15, the LPF 16, the PWM circuit 17,
Then, a sine wave signal whose frequency is slightly increased is output to the output terminal T1 via the inverter and the LPF3.

(B-2) Adjustment operation at the time of current advance If, in parallel operation, the current phase detected by the voltage detection circuit 4 and the current detection circuit 5 is advanced with respect to the voltage phase, the following is performed. Adjustment operation is performed.

When the current is advanced, a rectangular wave signal b and a rectangular wave signal b 'as shown in FIG. 18B are supplied to the connection terminals 8T1 and 8T2 of the phase difference detection circuit 8 in FIG. As a result, from the output side of the XOR 81, FIG.
A signal S81 as shown in FIG. 3B is output, and the signal whose phase is advanced out of the signals b and b ', that is, the signal b' is output from the output terminal Q bar of the D flip-flop 84. Further, the output S85 of the XOR 85 becomes "H" level (FIG. 18B).

As a result, a signal S88 of, for example, 100 Hz having a pulse width of the phase difference as shown in FIG. 18B is output from the output side of the NAND gate 88, and "H" is output from the NAND gate 87. "A constant level signal S87 is output. These NAND gates 87,
The outputs S87 and S88 of the oscillating unit 12 shown in FIG.
Are supplied to the connection terminals 8T3 and 8T4, respectively.

In FIG. 11, when the outputs S87 and S88 of the phase difference detecting circuit 8 are supplied to the connection terminals 8T3 and 8T4, respectively, one input terminal of the OR gate 129g of the oscillating unit 12 is connected to the NAND gate 87. Of the NAND gate 1 of the previous stage is input.
29e output (one-shot multivibrator 129
A output irrespective of the level) OR gate 12
The output signal of 9g is kept at the "H" level.

On the other hand, both signals S8 from the phase difference detection circuit 8
7, S88 are supplied to the NAND gate 129, and the output of the NAND gate 129 becomes an inverted signal (100 Hz) of the signal S88, and is supplied to one input side of the AND gate 129a. The other input side of the AND gate 129a has a frequency of 5 KHz as in the case of the current lag.
Is input, the AND gate 129a takes the AND of the 100 Hz pulse and the 5 KHz pulse whose frequencies are significantly different. This AND gate 1
The output pulse of 29a is supplied to the one-shot multivibrator 129A (D flip-flop 129b),
Further, the output (NAND gate 129e) of the one-shot multivibrator 129A is connected to an OR gate 129f.
Is supplied to one of the input terminals. At the same time, the other input terminal of the OR gate 129f is connected to the signal S88 (10
0 Hz) is input. As a result, the OR gate 129f
19 becomes "L" level (P2) every 5 KHz as shown in FIG. 19 (b).

On the other hand, as described above, the OR gate 129
Since the output signal of g becomes "H" level constant, the output F4 of the NOR gate 125 becomes "L" level constant and OR
The signal is supplied to one input side of the gate 127. Further, the other input side of the OR gate 127 has the signal F
3 and thus the output signal F of the OR gate 127
5 is the same pulse signal as the signal F3 (FIG. 19)
(B)). This signal F5 and the signal F6 are NAND
As shown in FIG. 19B, a signal F7 obtained by thinning out the pulse P2 from the signal F3 is output from the output side of the NAND gate 128.
This operation is performed every 5 KHz during the time when the connection terminal 8T4 is at the “L” level.

Thereafter, the signal F7 is supplied to the connection terminal 12T.
1 is output to the frequency dividing circuit 13 side, is frequency-divided by the frequency dividing circuit 13, and is further converted into a sine wave by the sine wave forming circuit 14 in accordance with the above-described pulse thinning. As a result, the electronic volume circuit 15 , The LPF 16, the PWM circuit 17, the inverter, and the LPF 3, the sine wave signal whose frequency is slightly reduced is output to the output terminal T1.

As described above, in the present embodiment, the phase adjustment is adjusted by adding a new pulse or thinning out the signal F3 shown in FIG. 17 once every 500 times. However, in the present invention, the counter 123
By changing the connection point between the gate and the AND gate 129a, it is possible to change the degree of the adjustment of the phase matching.

Thus, the frequency of the target waveform can be varied in a wide range, for example, twice to 1/2, so that the time until the phases match can be shortened. Also,
It is also possible to optimally set the degree according to various situations.

[0097]

The generators according to the first and second aspects of the present invention are configured as described above, so that the output phases of the respective generators when the output terminals of the generators operating in parallel are connected to each other are quickly matched. Becomes possible. That is, a phase difference occurs
As soon as pulses are added / decimated,
Since the wave number is changed, a quick pair when a phase difference occurs
Response, and the time until the output phase matches
Can be shortened. In addition, an adapter or the like for phase adjustment is not required for parallel operation. Furthermore, sufficient synchronization can be obtained over a wide range of phase fluctuation, and smooth synchronous operation can be continued.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic overall configuration of an embodiment of a generator according to the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment.

FIG. 3 is a main part circuit diagram showing an example of an AC generator, a rectifying and smoothing circuit, and the like of the embodiment.

FIG. 4 is a circuit diagram showing an example of an engine speed detection circuit of the embodiment.

FIG. 5 is a circuit diagram showing an example of the inverter circuit and the LPF of the embodiment. FIG. 3 is a circuit diagram illustrating an example of a rectangular wave conversion circuit of an AC output voltage signal according to the embodiment.

FIG. 6 is a circuit diagram showing an example of a current detection circuit and a comparison circuit of the embodiment.

FIG. 7 is a circuit diagram showing an example of the rectangular wave conversion circuit of the embodiment.

FIG. 8 is another circuit diagram showing an example of the rectangular wave conversion circuit of the embodiment.

FIG. 9 is a circuit diagram showing an example of the phase difference detection circuit of the embodiment.

FIG. 10 is a circuit diagram showing an example of a rise timing circuit of the embodiment.

FIG. 11 is a circuit diagram showing an example of the oscillation section of the embodiment.

FIG. 12 is a circuit diagram showing an example of a frequency divider 13 of the embodiment.

FIG. 13 is a circuit diagram showing an example of a sine wave conversion circuit of the embodiment.

FIG. 14 is a circuit diagram showing an example of the electronic volume of the embodiment.

FIG. 15 is a circuit diagram illustrating an example of an LPF, a PWM circuit, a voltage detection circuit, and the like of the embodiment.

FIG. 16 is a time chart for explaining the operation of the embodiment.

FIG. 17 is another time chart for explaining the operation of the embodiment.

FIG. 18 is another time chart for explaining the operation of the embodiment.

FIG. 19 is another time chart for explaining the operation of the embodiment.

FIG. 20 is an operation explanatory diagram showing a rise in output voltage when starting in parallel operation.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 AC generator 2 Rectifier smoothing circuit 3 Inverter circuit and LPF 4 Voltage detection circuit 5 Current detection circuit 6 Rectangular wave conversion circuit 7 Rectangular wave conversion circuit 8 Phase difference detection circuit 9 Comparison circuit 10 Protection circuit 11 Rise timing circuit 12 Oscillator 13 Frequency divider circuit 14 Sinusoidal circuit 15 Electronic volume circuit 16 LPF 17 PWM circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-24987 (JP, A) JP-A-49-74348 (JP, A) JP-A-58-70048 (JP, U) JP-A-62 145440 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H02J 3/38-3/42 H02M 7/48

Claims (2)

(57) [Claims] 1. A generator comprising: a DC power supply circuit that outputs DC power; and an inverter circuit that converts the DC power output from the DC power supply circuit to AC power having a predetermined frequency. Target waveform forming means for forming an output target waveform signal of the AC power having the predetermined frequency as a reference, output voltage detecting means for detecting an AC output voltage output from the inverter circuit, and output from the inverter circuit Output current detection means for detecting an AC output current; a zero-cross point of the detected output voltage waveform and an output current
A phase difference detecting means for detecting a phase difference between the zero cross point of the waveform and a phase difference detected by the phase difference detecting means. A reference signal for changing the frequency of the target waveform so that the phase difference is reduced by thinning out the pulse with respect to the reference pulse by the advanced signal when the phase difference is a current leading phase. A generator comprising: a generator. 2. The addition and thinning-out of a new pulse in the reference signal generating means is performed in a half cycle of the target waveform.
2. The generator according to claim 1, wherein the generator is executed at predetermined intervals shorter than a predetermined interval .