JP2002291255A - Inverter system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter system which connects multiple inverter units in series in the AC side. SOLUTION: In a master inverter which constitutes the inverter system, the phases of the inverter inside voltage and the load voltage in the slave side inverter is indicated, and the inverter inside voltage and the load voltage in the slave side inverter are coordinated with those of the master side inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter system in which a plurality of inverters for converting a DC voltage to an AC voltage are connected in series on the AC side to operate.

[0002]

2. Description of the Related Art Conventionally, an inverter is well known as a device for converting a DC voltage into an AC voltage, and is used, for example, for converting an output from a solar cell into an AC voltage.

[0003] A plurality of such inverters are connected in parallel to supply power to a load cooperatively. At this time, the load sharing is adjusted among the plurality of inverters. (Eg, Patent No. 2)
No. 6,789,91 or JP-A-2000-32764).

[0004] Further, in adjusting the load sharing described above, the present inventors disclose Japanese Patent Application No. 2000-125561 as an example in which not only active power sharing but also reactive power sharing can be adjusted. Filed.

[0005]

As described above, the inverters are operated in parallel, but the operation of connecting a plurality of inverters in series on the AC side has not been performed. That is, two inverters are connected in series on the AC side to obtain a higher AC voltage on the AC side,
No power was supplied to the load under the so-called single-phase three-wire system on the AC side.

This is because it is difficult to synchronize the output waveforms (AC voltage waveforms) of the two inverters connected in series on the AC side.

Of course, for such a reason, a plurality of inverters connected in series on the AC side are connected to one set of inverter systems, while a single inverter or another set of inverters is used as a counterpart. There has been no realization of an inverter system in which a plurality of sets of systems are connected in parallel on the AC side and power is supplied to a load in cooperation.

An object of the present invention is to provide an inverter system in which a plurality of inverters are connected in series on the AC side. Further, the inverter system is connected in parallel on the AC side by using the inverter system connected in series. It is an object of the present invention to provide an inverter system that can connect and cooperate to supply power to a load.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In the illustrated case, two inverters are connected in series on the AC side.

Reference numerals 110 and 120 in the figure denote inverters, 111-i and 121-i denote control elements, respectively, and 112 and i.
122 is a choke coil (filter), 113,
123 is a capacitor (filter), 114-i, 1
24-i is an output terminal of the filter, 115 and 125 are control element control units, 116 and 126 are phase detection units, respectively.
Reference numerals 117 and 127 denote PWM control units, 118 and 128 denote output current detecting means, 119 and 129 denote internal voltage detecting means, 130 denotes a common load, and 140-i denotes a drive circuit.

The inverters 110 and 120 respectively provide control element control units 115 and 125 and a drive circuit 140-1 to control terminals (eg, a transistor gate or base) of the control elements 111-i and 121-i.
By applying a pulse width modulated control signal (PWM control signal) via the control circuit 140-2 and 140-2, a desired output voltage is generated at a desired frequency (phase) as conventionally known. Each output AC voltage is connected to a choke coil (112 or 122) and a capacitor (113 or 12).
3) The power is supplied to the load 130 after being connected in series through the filter.

FIGS. 2A and 2B are diagrams for explaining an equivalent circuit of the inverter. Inverters 110 and 12 respectively
0 and are each equivalent, the input side of the voltage (the filter input voltage, i.e. the inverter internal voltage) of the inverter of the filter 112 and 122 E ₁ and the impedance of the filter Z _L1
And can be represented by a series circuit.

[0013] Then by taking the cooperation between the inverter internal voltage E _1-1 and E _1-2 each, i.e. in the internal voltage E _1-1 and E _1-2 are for example, the same voltage E _1, the same by to take the same phase under the frequency, between the terminal 140 and the terminal 142 shown, it is possible to obtain a voltage 2E ₁ (FIG. 2 (a)), also shown in the terminal 140 and the terminal 141 it can be operated in a single-phase three-wire to obtain respectively the voltage E ₁ between and between the terminal 141 and the terminal 142 in the (Figure 2 (b)).

In the coordination at this time, as described above,
One of the inverters is used as a master and the other is used as a slave, and the slave follows up under an instruction from the master. The signal line 150 shown in FIG.
Represents a master-slave signal line for coordinating the two inverters.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the present invention, the invention described in Japanese Patent Application No. 2000-125561 (prior invention), which was filed earlier, and the parallel operation of inverters will be described with reference to FIGS. Analyze.

FIG. 3 shows an equivalent circuit in which inverters are operated in parallel. That is, the first inverter 110 and the second inverter 210 are connected to the output terminals 114 and 214 of the filters via the filters, respectively, and are connected to the common load 1.
30.

[0017] FIG. 4 is an explanatory diagram enumerating symbols relating to FIG. 3, for example, E ₁ and E ₂ is the input voltage to the inverter 110 side and the inverter 210 side filter (internal voltage of the inverter), E _L1 And E _L2 represent voltages applied to the respective filters.

FIG. 5 shows an inverter 110 and a load 13.
0, the respective vector diagrams of the filters on the inverter 210 and inverter 110 side are shown. When we make an equation based on V

[0019]

(Equation 1)

The active power supplied by the inverter 110 is P ₁ , and the reactive power is Q ₁ . If the sign of the delay reactive power is positive

[0021]

(Equation 2)

Similarly, if the active power supplied by the inverter 210 is P ₂ and the reactive power is Q ₂ ,

[0023]

(Equation 3)

When the active power difference P ₂ -P ₁ supplied by the inverters 210 and 110 is obtained,

[0025]

(Equation 4)

The inverters 110 and 210 are of the same type.
Since it is a barta, X_L1≒ X_L2, R ₁≒ R_Two, Z_L1≒ Z
_L2And E_L1And E_L2Is a small value
E₁≒ E_Two≒ V and a substantially constant value.

[0027]

(Equation 5)

[0028]

[0029]

(Equation 6)

## EQU1 ## Similarly, the reactive power difference Q ₂ −Q ₁ supplied by the inverter 210 and the inverter 110 is obtained.

[0031]

(Equation 7)

## EQU1 ## Here, the power balance of each inverter when only the parallel operation phase is controlled will be examined.

In this case, the phase of the inverter is controlled by slightly changing the frequency. In other words, the higher the frequency, the faster the phase, and the lower the frequency, the later.

FIG. 6 is a diagram showing the relationship between the output active power P and the frequency f. The relationship between the two is expressed by the following relationship: f = f ₀ −k · P, and shows a mode in which the output active power P is detected and the frequency f is controlled.

The stability condition of the parallel operation of the inverters is that the frequencies of all the inverters are equal, and f = f ₀ -k ₁ · P ₁ = f ₀ -k ₂ · P ₂ (1) P _{2 -P 1 = VI S (θ 2} -θ 1) ...... (2) the above equation (2) of the theta ₂ - [theta] ₁ is changed, sharing of P ₁ and P ₂ are determined. Then, P ₁ , which satisfies both equations (1) and (2),
It will be operated in P _2.

FIG. 8 shows an equivalent circuit in a case where two inverters are connected in series on the AC side and cooperate with the inverter internal voltage in each inverter. Reference numerals 110, 112, 113, 120, 122, and 123 in the figure respectively correspond to FIG. 1, reference numeral 310 denotes an equivalent inverter, and reference numeral 312 denotes an equivalent choke coil. If the illustrated capacitors 113 and 123 are relatively small, equivalent capacitors corresponding to these capacitors may be omitted from the equivalent circuit.

In FIG. 8, inverter internal voltages _E1-1 and E1-1 of inverters 110 and 120 are respectively shown.
It is shown that the phases are substantially equal (frequency is equal) between _1-2 .

Under such circumstances, the two inverters 110 and 120 can be represented as one substantially equivalent inverter (equivalent inverter 310).

In FIG. 1, when the inverter 110 is used as a master, the phase detector 116 detects a phase difference φ ₁ between the voltage E ₁ and the output current I ₁ and supplies the phase difference φ ₁ to the PWM controller 117. PWM control unit 117 generates the aforementioned PWM control signal receives the voltage E ₁ and the output current I ₁ and the phase difference phi _1. The slave-side inverter 120 follows an instruction from the master side via the master-slave signal line 150.

Under the configuration shown in FIG. 1, master-side inverter 110 with master-slave signal line 150 interposed
The following control can be performed between the control and the slave inverter 120. That is, FIG.
In (a) and (b): (A) Only the master-side inverter 110 determines the generation timing and frequency of its own inverter internal voltage _E1-1 . Then, the determined generation timing and frequency are instructed to the slave inverter 120. The slave inverter 120 side to follow the instruction, and a generation timing and frequency of the inverter internal voltage E _1-2, fit to the instruction.

(B) If any trouble occurs on one of the master side and the slave side and stops due to the operation of a safety circuit or the like, the other side is also forcibly stopped.

A set of inverters having the configuration shown in FIG.
In the case where the system is operated in parallel with another set of other inverter systems on the right side, not shown in FIG. 1, each set of inverter systems may be operated as described above with reference to FIGS. In between, it is necessary to adjust the active power and to share the active power in a desired manner. In other words, the equivalent inverters 310 shown in FIG. 8 are operated in parallel, and the control mode for sharing the active power at that time corresponds to the case described with reference to FIGS. 3 to 7. Becomes

At this time, the following control can be performed in the control between the master-side inverter 110 and the slave-side inverter 120 shown in FIG. 1 via the master-slave signal line. (C) The combined power in one set of inverter systems is proportional to, for example, the output power of master-side inverter 110. Therefore, electric power is detected only by the master-side inverter 110, and the slave-side inverter 120 is controlled correspondingly.

(D) The master-side inverter 110 receives a signal from the slave-side inverter 120 regarding the output power (either active power or reactive power or both) of the slave-side inverter 120. Master-side inverter 110 performs control in a set of inverter systems in which master-side inverter 110 and slave-side inverter 120 are connected in series based on the added power obtained by adding the output power of master-side inverter 110. Do. That is, control is performed such that the sharing of the active power and the sharing of the reactive power with the other inverter system are desired.

(E) Even in a configuration in which the plural sets of inverter systems are operated in parallel, as described in the above item (B), in any one of the sets of inverter systems, the master side and the slave side When one of the inverter systems stops, the corresponding inverter system is stopped.

When a set of inverter systems in which the master inverter 110 and the slave inverter 120 are connected in series on the AC side operate in parallel with the other inverter system, the AC side can be called a single-phase three-wire system. Expressions can be configured.

FIG. 9 shows a configuration diagram employing a single-phase three-wire configuration. Reference numerals 110, 112, 113, 120,
Reference numerals 122, 123 and 130 correspond to FIG.
0, 212, 213, 220, 222, and 223 are reference numerals 110, 112, 113, 120, 122, 123,
11 in the counterpart inverter system corresponding to
0, 112, 113, 120, 122 and 123 are shown.

FIGS. 10 and 11 each show an embodiment in which a single-phase three-wire configuration is employed. In FIG. 10, one set of masters (master # 1) faces the other set of masters (master # 2) and one set of slaves (slave # 1) is the other set of slaves. (Slave # 2).

In FIG. 11, one set of masters (master # 1) is connected to the other set of slaves (slave # 1).
2) and one set of slaves (slave #)
1) faces the other set of masters (master # 2).

The output power from the [0050] Inverter (either master or slave) is proportional to the phase difference with respect to the voltage V applied to the load size and the inverter internal voltage E ₁ of the inverter internal voltage E _1. Therefore, among the inverters mutually to be operated in parallel, being equal the inverter internal voltage ₁ and the inverter internal voltage E ₂ at the inverter side of the respective effective power sharing in the inverter side of the respective inverter internal voltage E at the inverter side of the respective
₁ (also E ₂ ) depends only on the phase difference θ ₁ (also θ ₂ ) with respect to the voltage V. When the said phase difference theta ₁ and the phase difference theta ₂ are equal, also equal sharing of active power.

The choke coils L ₁₁ , L ₁₂ , L ₂₁ , L ₂₂
Are all equal, one set of master-side inverter 110 and the other set of master-side inverter 2
If the respective inverter internal voltages E ₁ and E ₂ are equal and the phase differences θ ₁ and θ ₂ are equal, the output powers of the respective master-side inverters 110 and 210 are equal. The inverter internal voltage and the phase difference of the slave inverter 120 are controlled to be equal to the inverter internal voltage E ₁ and the phase difference θ ₁ of the master inverter 110, and the inverter internal voltage and the phase difference of the slave inverter 220 are controlled by the master inverter. If the inverter 210 is controlled to be equal to the inverter internal voltage E ₂ and the phase difference θ ₂ , the output powers of the slave inverters 120 and 220 are equal.

Therefore, in each set of master-side inverters, the frequency (in other words, the phase difference) is determined based on the active power of its own output or the active power of the sum of the output active power of the slave-side inverters. By controlling, it becomes possible to control the sharing of the active power.

The difference between the master side and the slave side shown in FIG. 10 and FIG. 11 is only that which is the subject of control.

FIG. 12 is a diagram showing a mode of connection of a load. In the case shown, the load 130C is the load 130A or the load 130A.
In this case, a terminal voltage twice as large as that in the case of B is applied.

However, the configuration shown in FIG. 12 corresponds to the configuration as shown in FIG. FIG. 13 shows an equivalent circuit of the configuration of FIG.

Therefore, in the case of the configuration shown in FIG.
The parallel load of the loads 130A and 130C-1 in FIG. 13 corresponds to the load 130-1 in FIG.
It can be considered that the parallel load of the loads 130B and 130C-2 corresponds to the load 130-2 in FIG. In other words, in the case of the configuration shown in FIG.
It is sufficient to perform control under the same mode as the control mode described with reference to FIG.

Considering the reactive power, from equation 7, R ₁ = R ₂ ≠ 0, that is, cos φ _L ≠ 0, the reactive power Q ₂ -Q ₁ depends on the phase difference. Considering the reactive power of the load make a simultaneous equations with Q _L = Q ₁ + Q ₂ above equation and Equation 7 putting the Q _L, Q ₁ = Q ₂ becomes by controlling the phase, the output of the inter-device mutual The current balance can always be equalized.

FIG. 14 is a detailed block diagram of the present invention. FIG. 14 shows the configuration of a set of inverter systems. The difference between the code corresponding to the master-side inverter and the code corresponding to the slave-side inverter is a difference obtained by simply adding a dash (') to the slave-side.

In FIG. 14, for example, 100 V · 50
1 shows an electrical configuration of a portable AC power generator 21 that generates an AC power supply of 1 Hz or 60 Hz. The portable AC generator 21 includes a three-phase AC generator 22 driven by an engine (not shown), and a single-phase inverter unit 23 connected to a subsequent stage.

The alternator 22 includes a fuel (gasoline) for the engine in addition to the rotor and the armature (both not shown).
A stepping motor 24 is provided for controlling the rotation speed of the engine by controlling the supply amount. Armature has Y
Connected main windings 25u, 25v, 25w and auxiliary winding 2
6 are wound, and the main winding terminals 27u, 27v, 2
7w and the auxiliary winding terminals 28a, 28b are connected to input terminals 29u, 29v, 29w and input terminals 30a, 30b of the inverter unit 23, respectively.

On the other hand, the inverter unit 23 is configured as follows. That is, the input terminals 29u,
A rectifier circuit 33 is connected between 9v, 29w and the DC power supply lines 31, 32. A smoothing capacitor 34 is connected between the DC power lines 31 and 32,
An inverter circuit 37 and a filter circuit 38 are cascaded between the output terminals 1 and 32 and the output terminals 35 and 36. Note that the rectifier circuit 33 corresponds to a DC power supply circuit in the present invention.

The rectifier circuit 33 has a configuration in which thyristors 39 to 41 and diodes 42 to 44 are connected in the form of a so-called three-phase mixed bridge.
7 has a configuration in which transistors 45 to 48 (corresponding to switching elements) and free-wheel diodes 49 to 52 are connected in a so-called full bridge form.

The filter circuit 38 includes an inverter circuit 37
Output terminal 53 and output terminal 3 of inverter unit 23
5 and a capacitor 56 connected between the output terminals 35 and 36 of the inverter unit 23. Inverter circuit 37
Is directly connected to the output terminal 36 of the inverter unit 23, and a current transformer 57 for detecting an output current is provided in a current path from the output terminal 54 to the filter circuit 38. .

Further, the inverter unit 23 includes a control power supply circuit 58, a control circuit 59, and a drive circuit 60. The control power supply circuit 58 includes the input terminal 30
a, an AC voltage induced in the auxiliary winding 26 is input through the terminals 30 and 30b, the DC voltage is rectified and smoothed, and a control DC voltage (for example, 5 V, ± 15 V) for operating the control circuit 59 is generated. Has become. The AC voltage induced in the auxiliary winding 26 is also input to the control circuit 59 to detect the engine speed.

The control circuit 59 includes the microcomputer 6
1 (hereinafter referred to as microcomputer 61), DC power supply detection circuit 6
2. It comprises an output voltage detection circuit 63, an output current detection circuit 64, and a PWM circuit 65. Microcomputer 61
Although not specifically shown, CPU, RAM, ROM,
The input / output port, the A / D converter, the timer circuit, the oscillation circuit, and the D / A converter are configured as one-chip ICs.

The DC power supply detection circuit 62 is connected to the DC power supply line 31.
And a DC voltage Vdc between the DC voltage V.sub.32 and the detected DC voltage V.sub.dc, and outputs the detected DC voltage to the microcomputer 61 as a DC voltage detection signal. In this case, the microcomputer 61 controls the thyristors 39 to 41 based on the DC voltage detection signal so that the DC voltage Vdc becomes a predetermined voltage, for example, 180V.

The output voltage detecting circuit 63 includes a voltage dividing circuit for dividing the voltage between the output terminals 53 and 54 of the inverter circuit 37, and a filter for removing a carrier wave component from the divided rectangular wave voltage. , And outputs the detected output voltage Vs to the microcomputer 61 and the PWM circuit 65 as an output voltage detection signal.

The output current detection circuit 64 (corresponding to output current detection means) converts the output current detected by the current transformer 57 into a predetermined voltage level, and outputs the detected output current Is.
Is output to the microcomputer 61 and the PWM circuit 65 as an output current detection signal.

The PWM circuit 65 executes PWM control to generate drive signals G1 to G4 for the transistors 45 to 48. The drive signals G1 to G4 are applied to the bases of the transistors 45 to 48 via the drive circuit 60, respectively.

The output frequency of the microcomputer 61 is set to 50 Hz by a switch input from a switch input unit (not shown).
It can be set to any of 60 Hz. For example, when an AC power supply of 50 Hz and 100 V is to be generated, a sine wave reference signal Vsin having the same frequency as the set output frequency is supplied to the PWM circuit 65. I have.
However, the sine wave reference signal Vsin is adjusted so that the detection output voltage Vs of the output voltage detection circuit 63 becomes equivalent to 100 V output, that is, output voltage feedback control is performed. . Further, as will be described later, the sine wave reference signal Vsin is also for adjusting the output frequency based on the output active power.

As shown in FIG. 15A, the PWM circuit 65 uses the sine wave reference signal Vsin and a carrier wave Sc composed of, for example, a triangular wave of 16 kHz (in the drawing, the frequency is extremely reduced for convenience). The high-frequency voltage Vo having a rectangular waveform shown in FIG.
0 Hz or 60 Hz).
Generate G4. The generated frequency is, for example, 50 Hz.
Is achieved by shifting the frequency of the sine wave reference signal Vsin, which is configured to be shiftable in a range of ± △ with respect to. The high-frequency voltage Vo thus generated is filtered by the filter circuit 38 to remove high-frequency components, thereby forming, for example, an AC output Voac of 100 V, 50 Hz or 60 Hz, as shown in FIG.

The microcomputer 61 functions as an active power detecting means, a phase angle detecting means, a phase detecting means and a control means. Hereinafter, these functions will be described together with their functions.

When the operation is started, the microcomputer 61
The output frequency is controlled according to the control flowchart shown in FIG. That is, in step Q1, the first zero cross of one cycle of the output voltage Vo (see FIG. 17, timing t0) is detected. In this case, since the effective zero crossing between the sine wave reference signal Vsin and the output voltage Vo ideally coincides with each other, the microcomputer 61 starts the first cycle of the sine wave reference signal Vsin (timing to change to the plus side). Is determined at the zero-cross timing t0. Then, in step Q2, it is detected whether the instantaneous value Is of the current is positive or negative. That is, it detects whether the current is a leading phase or a lagging phase with respect to the voltage, and thereby detects whether a phase angle φ described later is a leading phase or a lagging phase. In this case, since the determination on the instantaneous value Is of the current is based on the first determination, the instantaneous value of the current in this case is represented by Is.
(1).

Thereafter, an instantaneous value Is (n) (where n is 1 to 6) is detected from the detected output current signal Is at six (equally spaced) timings during a half cycle (step Q3). ). Then, in step Q4, the instantaneous active power P
(N) is calculated. That is, the instantaneous value Is (n) of the current and the sine wave reference signal Vsin (n) at each of the detection opportunities (1) to (6) in FIG. 17 (this is known in advance).
And then memorize this. In the next step Q5, the square of the instantaneous value I (n) is obtained and stored. 6
When the cycle is completed (“YES” in step Q6), the process proceeds to step Q7, and the active power P is calculated (detected). In this case, the active power P is P = P (1) +.
(6) Required.

Next, the process proceeds to step Q8, where the current effective value I is obtained. This current effective value I is I = ((Is (1) ² +... Is (6) ² ) / 6) ^1/2
Is required.

In the next step Q9, a phase angle φ is obtained. That is, since the relation between the apparent power I × E and the active power P is P = (I × E) cos φ (φ is the phase angle), cos φ = P / (I × E), and from this cos φ Determine the phase angle φ.

In this case, in step Q2, if a positive value is detected, the phase angle φ is detected as a leading phase, and if a negative value is detected, the phase angle φ is a lagging phase. That has been detected.

In the next step Q10, the phase angle φ
And the output frequency is set by the leading or lagging phase. This setting is performed based on the data table shown in FIG. In other words, when the phase angle φ is a leading phase, the frequency is set to decrease in accordance with the magnitude of the phase angle φ, and when the phase angle φ is a lagging phase,
The frequency is set to increase in accordance with the magnitude of the phase angle φ. For example, when the phase angle φ is 0 °, 5
When the phase angle φ becomes 90 degrees based on 0.0 Hz, 5
The frequency is set to 0.1 Hz, and the interval is set linearly.

Further, as described above, the microcomputer 61 has an output voltage control function of detecting the DC voltage Vdc and adjusting the output voltage regardless of the on / off control of the thyristors 39 to 41. That is, as shown in steps R1, R2, and R3 in the flowchart of FIG. 19, the control is performed so that the output voltage is increased when the Vdc becomes, for example, 180 V or more. That is, control is performed so that the amplitude of the sine wave reference signal Vsin is increased to increase the output voltage. For example, 180V to 1V
When the frequency increases, the output frequency is controlled to increase by 0.01 Hz.

A case where such portable AC generators are connected in parallel to supply power to a load will be described. For example, one of the two portable AC generators is a portable AC generator A, and the other is a portable AC generator B. Now, for some reason (for example, load fluctuation), the output frequency of one AC generator A instantaneously becomes, for example, 49.96 Hz.
, A cross current flows from the other AC generator B having an output frequency of 50.00 Hz to one AC generator A. Also, when the output voltage of the AC generator B is higher than the output voltage of the AC generator A, a cross current flows from the AC generator B to the AC generator A.

In this case, in the AC generator B, the phase of the current is delayed with respect to the voltage (the phase angle of the delayed phase). Conversely, in the AC generator A, the current is advanced with respect to the voltage (advanced phase angle).

Here, in this embodiment, when the phase angle of the lag phase is reached, the output frequency is controlled so as to increase.
When the phase angle of the leading phase is reached, the output frequency is controlled so as to decrease. Therefore, the AC generator A is controlled to further lower the output frequency, and the AC generator B is controlled to further increase the output frequency. As a result, power is generated from the AC generator B to the AC generator A. As a result, the voltage Vdc, which is the main circuit voltage of the inverter circuit 37 of the AC generator A, increases. Then, as described with reference to FIG.
Is controlled to increase the output voltage. As a result, the flow of the cross current into the AC power generation device A is reduced, and as a result, the cross current between the power supply devices A and B is eliminated.

In this case, according to this embodiment, the active power P including the phase angle φ element between the output voltage and the output current is detected, and the phase angle φ is calculated based on the detected active power P. Therefore, even when the output current or the detection signal Is of the output current detection circuit 64 serving as the output current detection means has a waveform distortion, an almost accurate phase angle φ can be detected. That is, the detection accuracy of the phase angle φ can be improved.

Therefore, the frequency control of the output voltage can be properly performed based on the phase angle with high detection accuracy, and the output current balance between the devices can be improved when the parallel operation is performed. Is always equal.

In particular, according to this embodiment, since the active power is detected during the half cycle of the AC voltage, the active power can be detected in a short time, and Frequency control can be performed quickly. However, the active power may be detected in one cycle of the AC voltage.

Next, FIG. 20 and FIG. 21 show flowcharts for control relating to reactive power. The output frequency is set according to the magnitude of the reactive power and the leading and lagging phases of the reactive power. That is, FIG.
Steps S1 to S in the flowchart of FIG.
8 is the same as step Q1 to step Q8 in FIG. In step S9, cos φ is obtained, and in step S10
Then, sin φ is obtained from cos φ, and the reactive power is calculated (reactive power calculating means). It should be noted that whether the reactive power is a leading phase or a lagging phase can be determined from the determination result of step S2 (reactive power phase detecting means). Instantaneous value of current I
When (1) is positive, it is a leading phase, and when negative, it is a lagging phase.

In step S11, the frequency is set based on the magnitude and phase of the reactive power with reference to the data table shown in FIG. As an example, when the reactive power of the leading phase is -2800 W (this is -90 in terms of the phase angle φ).
(Equivalent to °) corresponds to 49.9 Hz.

In the above description, the phase of the inverter internal voltage of the master inverter and that of the slave inverter are equal. However, the phase of the inverter internal voltage of the master inverter and the phase of the inverter internal voltage of the slave inverter are equal. Can be set to, for example, π / 3 or 2π / 3.

[0089]

As described above, according to the present invention, it is possible to provide an inverter system in which a plurality of inverters are connected in series on the AC side. Then, the set of inverter systems can be operated in parallel.

[Brief description of the drawings]

FIG. 1 shows a principle configuration diagram of the present invention.

FIG. 2 is a diagram illustrating an equivalent circuit of an inverter.

FIG. 3 shows an equivalent circuit in which inverters are operated in parallel.

FIG. 4 is an explanatory diagram listing symbols related to FIG. 3;

FIG. 5 is a vector diagram of a filter of an inverter.

FIG. 6 is a diagram showing a relationship between an output active power P and a frequency f.

FIG. 7 is a diagram illustrating active power output from each inverter.

FIG. 8 shows an equivalent circuit in a case where two inverters are connected in series on the AC side and cooperate with the inverter internal voltage in each inverter.

FIG. 9 shows a configuration diagram employing a single-phase three-wire configuration.

FIG. 10 shows an embodiment in which a single-phase three-wire configuration is adopted.

FIG. 11 shows an embodiment in which a single-phase three-wire configuration is employed.

FIG. 12 is a diagram showing a mode of connection of a load.

FIG. 13 shows an equivalent circuit of the configuration of FIG.

FIG. 14 shows a detailed configuration diagram of the present invention.

FIG. 15 is a waveform chart of each part.

FIG. 16 is a flowchart illustrating control related to active power.

FIG. 17 is a diagram showing a sine wave reference signal and a detection output current.

FIG. 18 is a diagram illustrating a relationship between a phase angle φ and a frequency in the case of control related to active power.

FIG. 19 shows a flowchart for controlling a DC side voltage Vdc with respect to control relating to active power.

FIG. 20 is a flowchart illustrating control related to reactive power.

FIG. 21 is a diagram showing a relationship between a phase angle φ and a frequency in the case of control relating to reactive power.

[Explanation of symbols]

 110, 120: Inverter 111, 121: Control element 112, 122: Choke coil (filter) 113, 123: Capacitor (filter) 114, 124: Output terminal of filter 115, 125: Control element control section 116, 126: Phase Detector 117, 127: PWM controller 118, 128: output current detector 119, 129: internal voltage detector 130: common load 150: signal line between master and slave

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masao Iku 3 Hayakawa, Hayakawa, Nitta-cho, Nitta-gun, Gunma Prefecture Inside Nitta Plant of Sawafuji Electric Co., Ltd. (72) Inventor Yuji Nakamura, Nitta-cho, Nitta-gun, Gunma 3 Hayakawa Hayakawa 3 Sawafuji Electric Co., Ltd. Nitta Plant (72) Inventor Takimoto, etc. 991 Anatacho, Seto City, Aichi Prefecture Higashishiba Aichi Plant F term (reference) 5H007 AA04 AA06 CA01 CA03 CB05 CC01 CC05 DA03 DA04 DA05 DB01 DB12 DC02 DC04 DC05 EA02

Claims (6)

[Claims] A plurality of inverters are connected in series on each AC side, and at least one inverter connected in series becomes a master, and the master becomes the master. An inverter system, wherein the inverter internal voltage of the inverter, the generation timing and frequency of the voltage are determined, and operating conditions are instructed to the other slave inverters. 2. The inverter system according to claim 1, wherein the inverter serving as a master detects its own output active power and / or output reactive power and determines the frequency of the internal voltage of the inverter. . 3. The inverter which has become a master, the active power of the sum of its own output active power and the output active power of a slave inverter, and / or the output invalid power of its own inverter and the inverter which has become a slave. 2. The inverter system according to claim 1, wherein a frequency of the internal voltage of the inverter is determined based on a reactive power of a sum of the power and the reactive power. 4. An inverter system according to claim 1, wherein said one set of inverter systems is operated in parallel with one or more other sets of inverter systems. Claim 1.
Or an inverter system according to any one of claims 2 and 3. 5. The inverter as a master constituting one set of inverter systems according to claim 1 is connected in parallel with an inverter as a master or an inverter as a slave of another set of inverter systems. The inverter system according to claim 4, wherein: 6. When one of an inverter serving as a master and an inverter serving as a slave constituting the set of inverter systems according to claim 1 stops, the other inverter is forcibly stopped. The inverter system according to any one of claims 1 to 5, wherein the inverter system comprises: