JP3356014B2 - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JP3356014B2 JP3356014B2 JP21428197A JP21428197A JP3356014B2 JP 3356014 B2 JP3356014 B2 JP 3356014B2 JP 21428197 A JP21428197 A JP 21428197A JP 21428197 A JP21428197 A JP 21428197A JP 3356014 B2 JP3356014 B2 JP 3356014B2
- Authority
- JP
- Japan
- Prior art keywords
- bond
- chip
- substrate
- semiconductor element
- crawling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims description 20
- 230000009194 climbing Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000002788 crimping Methods 0.000 description 3
- 230000009193 crawling Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ボンドによって基
板に固着される半導体素子に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device fixed to a substrate by a bond.
【０００２】[0002]
【従来の技術】フリップチップなどのバンプ付の半導体
素子（以下、「チップ」という）を基板に実装する方法
として、ボンドを用いる方法が広く用いられている。こ
の方法は、電極が形成された基板の表面にボンドを塗布
し、このボンド上にバンプ付チップを搭載し、その後圧
着ツールによりバンプ付チップのバンプを基板の電極に
圧着するとともに、ボンドを熱硬化させてバンプ付電子
部品を基板に固着させるものである。ここで用いられる
ボンドとして、一般にエポキシ樹脂などの熱硬化性樹脂
が多用される。2. Description of the Related Art A method using a bond is widely used as a method for mounting a semiconductor device with a bump such as a flip chip (hereinafter, referred to as a "chip") on a substrate. In this method, a bond is applied to the surface of the substrate on which the electrodes are formed, a chip with bumps is mounted on the bond, and then the bumps of the chip with bumps are pressed against the electrodes of the substrate by a pressing tool, and the bond is heated. This is to cure and fix the electronic component with bump to the substrate. In general, a thermosetting resin such as an epoxy resin is frequently used as the bond used here.
【０００３】[0003]
【発明が解決しようとする課題】ところが、チップを基
板に塗布されたボンド上に搭載してチップを介してボン
ドを加熱する際に、ボンドがチップの側面に沿って這い
上ることがある。この這い上りは、常温では高粘度の液
体であるボンドが加熱されることにより粘度が低下し、
硬化に至る前に表面張力によりチップの側面に沿って上
昇するものである。そして這い上ったボンドはチップの
上面を吸着している吸着ツールの下面に付着し、その後
硬化すると除去が困難であり、またチップの正常な吸着
を妨げるという問題点があった。However, when the chip is mounted on the bond applied to the substrate and the bond is heated via the chip, the bond may crawl along the side surface of the chip. This creeping up, the viscosity is reduced by heating the bond which is a high viscosity liquid at normal temperature,
It rises along the side of the chip due to surface tension before hardening. Then, the crawled bond adheres to the lower surface of the suction tool that is suctioning the upper surface of the chip, and it is difficult to remove the hardened bond after curing, and there is a problem that normal suction of the chip is hindered.
【０００４】そこで本発明は、熱圧着時にボンドが這い
上って吸着ツールに付着することのない半導体素子を提
供することを目的とする。Accordingly, an object of the present invention is to provide a semiconductor element in which a bond does not crawl during thermocompression and adhere to a suction tool.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体素子は、
ボンドにより基板に固着され、下面に形成されたバンプ
を基板の電極に導通させることによって基板に実装され
る半導体素子であって、側面に前記ボンドの熱圧着時の
這い上りを阻止する這い上り阻止部が形成されている。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor element which is fixed to a substrate by a bond and is mounted on the substrate by conducting a bump formed on the lower surface to an electrode of the substrate, wherein the side surface prevents the bond from climbing during thermocompression bonding. A part is formed.
【０００６】[0006]
【発明の実施の形態】上記構成の本発明によれば、半導
体素子の側面にボンドの這い上りを阻止する這い上り阻
止部を形成することにより、熱圧着時にボンドが這い上
って圧着ツールに付着するのを防止することができる。According to the present invention having the above-described structure, by forming a crawling-up preventing portion for preventing the bond from climbing up on the side surface of the semiconductor element, the bond crawls up at the time of thermocompression bonding to form a crimping tool. Adhesion can be prevented.
【０００７】（実施の形態１）図１は、本発明の実施の
形態１の半導体素子の実装状態の側断面図、図２
（ａ），（ｂ）は同半導体素子の製造工程の説明図であ
る。図１において、半導体素子であるチップ１の下面に
はバンプ２が設けられている。チップ１は基板３に実装
されており、バンプ２は基板３の上面に形成された電極
４に導通して接合されている。チップ１の下面と基板３
の間にはボンド５が充填されている。ボンド５はチップ
１を基板３に実装する前に予め基板３上に塗布するか、
またはチップ１の実装後にチップ１と基板３の隙間に注
入されたものである。(Embodiment 1) FIG. 1 is a side sectional view showing a mounted state of a semiconductor device according to Embodiment 1 of the present invention.
(A), (b) is explanatory drawing of the manufacturing process of the same semiconductor element. In FIG. 1, bumps 2 are provided on the lower surface of a chip 1 which is a semiconductor element. The chip 1 is mounted on a substrate 3, and the bump 2 is electrically connected to an electrode 4 formed on the upper surface of the substrate 3. Lower surface of chip 1 and substrate 3
The gap 5 is filled with the bond 5. The bond 5 is applied on the substrate 3 in advance before mounting the chip 1 on the substrate 3 or
Alternatively, it is injected into a gap between the chip 1 and the substrate 3 after the chip 1 is mounted.
【０００８】チップ１の側面には段付加工がなされてお
り、これにより側面上部から側方へ突出するボンドの這
い上り阻止部６がつば状に突設されている。ボンド５は
常温では高粘度の液体であるが、チップ１を基板３に熱
圧着する際、ボンド５を熱硬化させるために加熱すると
粘度が低下し、チップ１の外にはみ出したボンド５がチ
ップ１の側面に沿って表面張力により上昇する。しかし
チップ１の側面上部には段付形状の這い上り阻止部６が
突設されているため、這い上ったボンド５の先端部がこ
の段付部に到達すると、それ以上にボンド５が上昇する
ことはなく、したがってボンド５がチップ１の上面を吸
着している圧着ツール７の下面に付着することがない。[0008] The side surface of the chip 1 is stepped, so that a bond crawling-up preventing portion 6 protruding laterally from the upper side of the side surface is provided in a brim-like shape. The bond 5 is a liquid having a high viscosity at room temperature. However, when the chip 1 is thermocompressed to the substrate 3, the viscosity decreases when the bond 5 is heated to thermally cure the bond 5. 1 rises along the side surface due to surface tension. However, since a step-shaped crawling-up prevention portion 6 is protrudingly provided on the upper side surface of the chip 1, when the tip end of the crawled bond 5 reaches this stepped portion, the bond 5 is further raised. Therefore, the bond 5 does not adhere to the lower surface of the crimping tool 7 that is holding the upper surface of the chip 1.
【０００９】次に図２を参照して這い上り阻止部６の形
成方法について説明する。図２（ａ）において、１１は
ウェハであり、チップはウェハ１１から所定部分を切り
出すことにより製造される。図２（ａ）に示すように、
ウェハ１１にはまず刃先幅Ｂ１のカッタ１３により深さ
Ｄの溝形状の切り込み１２が加工される。次いで図２
（ｂ）に示すように、切り込み１２の内部に、刃先幅Ｂ
２がＢ１よりも小さいカッタ１５により、更に切り込み
１４が形成される。これによりウェハ１１は切断され、
切断面には（Ｂ１−Ｂ２）／２の幅の段付を有する這い
上り阻止部６が形成される。Next, a method of forming the crawling-up preventing portion 6 will be described with reference to FIG. In FIG. 2A, reference numeral 11 denotes a wafer, and a chip is manufactured by cutting a predetermined portion from the wafer 11. As shown in FIG.
First, a groove-shaped cut 12 having a depth D is formed on the wafer 11 by a cutter 13 having a blade edge width B1. Then Figure 2
As shown in (b), the cutting edge width B
A notch 14 is further formed by the cutter 15 in which 2 is smaller than B1. Thereby, the wafer 11 is cut,
A crawling-up preventing portion 6 having a step width of (B1-B2) / 2 is formed on the cut surface.
【００１０】（実施の形態２）図３は本発明の実施の形
態２の半導体素子の実装状態の側断面図、図４は同半導
体素子の製造工程の説明図である。実施の形態１では、
チップの側面に形成される這い上り阻止部として段付形
状を用いているが、本実施の形態２では、側面をテーパ
状としたものである。(Embodiment 2) FIG. 3 is a side sectional view showing a mounted state of a semiconductor device according to Embodiment 2 of the present invention, and FIG. 4 is an explanatory view of a manufacturing process of the semiconductor device. In the first embodiment,
Although a stepped shape is used as the crawling-up preventing portion formed on the side surface of the chip, in the second embodiment, the side surface is tapered.
【００１１】図３において、チップ１’の側面にはテー
パ状の這い上り阻止部６’が形成されている。這い上り
阻止部６’はチップ１’の上面が外側に張り出したオー
バーハングのテーパ形状となっており、この形状によっ
てボンド５の這い上りを阻止する。In FIG. 3, a tapered crawling-up preventing portion 6 'is formed on the side surface of the chip 1'. The crawling-up preventing portion 6 'has an overhang tapered shape in which the upper surface of the chip 1' projects outward, and this shape prevents the bond 5 from climbing up.
【００１２】次に図４を参照して這い上り阻止部６’の
形成方法について説明する。図４において、ウェハ１
１’を切断してチップ１’を切り出すに際し、テーパ状
の刃先形状を有するカッタ１７を用いる。ウェハ１１’
にテーパ溝１６を加工することにより、切り出されたチ
ップ１’の側面にはテーパ状の這い上り阻止部６’が形
成される。Next, a method of forming the crawling-up preventing portion 6 'will be described with reference to FIG. In FIG. 4, the wafer 1
When cutting out the chip 1 'by cutting 1', a cutter 17 having a tapered cutting edge shape is used. Wafer 11 '
By forming the tapered groove 16 at the side, a tapered crawling-up preventing portion 6 'is formed on the side surface of the cut chip 1'.
【００１３】本発明は上記実施の形態１および２に限定
されないのであって、這い上り阻止部６の形状は、要は
ボンド５の表面張力による這い上りを阻止できるような
形状であればよく、例えば側面から突出する突起部を有
する形状であってもよい。The present invention is not limited to the first and second embodiments. The shape of the crawling preventing portion 6 may be any shape as long as it can prevent the bond 5 from crawling due to the surface tension. For example, it may have a shape having a protrusion protruding from the side surface.
【００１４】[0014]
【発明の効果】本発明によれば、半導体素子の側面にボ
ンドの這い上りを阻止する這い上り阻止部を設けたの
で、熱圧着時にボンドが加熱され粘度が低下して表面張
力により半導体素子の側面を這い上って吸着ツールの下
面に付着することを防止でき、したがって、付着したボ
ンドが吸着ツールの下面で固化して半導体素子の正常な
吸着を妨げることがなく、また吸着ツールの保守・清掃
の労力を削減することができる。According to the present invention, a crawling-up preventing portion is provided on the side surface of a semiconductor element for preventing the bond from climbing up, so that the bond is heated during thermocompression bonding, the viscosity is reduced, and the surface tension of the semiconductor element is reduced. It can be prevented from climbing up the side and sticking to the lower surface of the suction tool. Therefore, the adhered bond does not solidify on the lower surface of the suction tool and hinder normal suction of the semiconductor element. Cleaning effort can be reduced.
【図１】本発明の実施の形態１の半導体素子の実装状態
の側断面図FIG. 1 is a side sectional view showing a mounted state of a semiconductor element according to a first embodiment of the present invention;
【図２】（ａ）本発明の実施の形態１の半導体素子の製
造工程の説明図 （ｂ）本発明の実施の形態１の半導体素子の製造工程の
説明図FIG. 2A is an explanatory view of a manufacturing process of the semiconductor device according to the first embodiment of the present invention; and FIG. 2B is an explanatory view of a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
【図３】本発明の実施の形態２の半導体素子の実装状態
の側断面図FIG. 3 is a side sectional view showing a mounted state of a semiconductor element according to a second embodiment of the present invention;
【図４】本発明の実施の形態２の半導体素子の製造工程
の説明図FIG. 4 is an explanatory diagram of a manufacturing process of the semiconductor device according to the second embodiment of the present invention.
１、１’チップ ２ バンプ ３ 基板 ４ 電極 ５ ボンド ６、６’ 這い上がり阻止部 ７ 圧着ツール DESCRIPTION OF SYMBOLS 1, 1 'chip 2 Bump 3 Substrate 4 Electrode 5 Bond 6, 6' Crawl-up prevention part 7 Crimping tool
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭51−128260（ＪＰ，Ａ) 特開 昭63−143851（ＪＰ，Ａ) 特開 平７−66326（ＪＰ，Ａ) 特開 平８−31773（ＪＰ，Ａ) 実開 昭62−112153（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/28 H01L 21/60 311 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-51-128260 (JP, A) JP-A-63-143851 (JP, A) JP-A-7-66326 (JP, A) JP-A 8- 31773 (JP, A) Japanese Utility Model 62-112153 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/28 H01L 21/60 311
Claims (1)
されたバンプを基板の電極に導通させることによって基
板に実装される半導体素子であって、側面に前記ボンド
の熱圧着時の這い上りを阻止する這い上り阻止部が形成
されていることを特徴とする半導体素子。1. A semiconductor element mounted on a substrate by bonding a bump formed on a lower surface to an electrode of the substrate by being fixed to the substrate by a bond, wherein a side surface of the semiconductor element is crawled during thermocompression bonding of the bond. A semiconductor element, wherein a crawling-up preventing portion is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21428197A JP3356014B2 (en) | 1997-08-08 | 1997-08-08 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21428197A JP3356014B2 (en) | 1997-08-08 | 1997-08-08 | Semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1154666A JPH1154666A (en) | 1999-02-26 |
| JP3356014B2 true JP3356014B2 (en) | 2002-12-09 |
Family
ID=16653144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21428197A Expired - Fee Related JP3356014B2 (en) | 1997-08-08 | 1997-08-08 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3356014B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006073843A (en) * | 2004-09-03 | 2006-03-16 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| JP4812525B2 (en) * | 2006-06-12 | 2011-11-09 | パナソニック株式会社 | Semiconductor device, semiconductor device mounting body, and semiconductor device manufacturing method |
| JP2013191721A (en) * | 2012-03-14 | 2013-09-26 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
| JP2014011289A (en) * | 2012-06-29 | 2014-01-20 | Ibiden Co Ltd | Electronic component and manufacturing method of electronic component |
| JP2017120800A (en) * | 2015-12-28 | 2017-07-06 | 富士通株式会社 | Semiconductor device, semiconductor device manufacturing method, and electronic device |
-
1997
- 1997-08-08 JP JP21428197A patent/JP3356014B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1154666A (en) | 1999-02-26 |
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