JP3355979B2 - LCD drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD for driving an LCD
The present invention relates to an LCD drive circuit for performing various displays on D.

[0002]

2. Description of the Related Art As an example of this type of LCD driving circuit, there is a driving circuit as shown in FIG. This drive circuit is LC
LCD driver 2 for driving D1 and LCD driver 2
And a CPU 10 for outputting display data to the CPU. The LCD driver 2 is provided with a data input terminal DB for inputting data, a terminal R / W for inputting signals indicating data read / write, an input terminal E for inputting a signal for capturing input data, and the like. . CPU1
0 is a Z80 CPU, a data output terminal DB for outputting data, and an address terminal A for outputting an address signal.
B, and an output terminal E for outputting a capture signal for causing the LCD driver 2 to capture output data.

[0005] Here, the CPU 10 sends the LCD driver 2
When the data is transmitted to the LCD 1 and displayed on the LCD 1, first, an address signal is transmitted from the address terminal AB to the address decoder 5 via the address bus, and the chip select signal C from the address decoder 5 to the three-state buffer 4
Send S. Then, the three-state buffer 4 enters a data write mode. When display data is subsequently output from the 8-bit data output terminal DB of the CPU 10, the display data is output to the LCD driver 2. At this time, an “L” level write signal is output from the output terminal R / W of the CPU 10 to the input terminal R / W of the LCD driver 2.

[0004] Further, following the write signal from the output terminal R / W, a capture signal E of "H" level is output from the output terminal E of the CPU 10 to the input terminal E of the LCD driver 2.
Then, if the signal given to the input terminal R / W is a “L” level write signal, the LCD driver 2
At the rise of the capture signal E, 8-bit display data of the data input terminal DB is captured. The acquired data is given to the LCD 1 to be displayed on the LCD 1. The input terminal RS of the LCD driver shown in FIG.
D1 is a terminal to which a signal RS for display scanning is input. In this example, the lowest address terminal A0 of the CPU 10
Is supplied.

FIG. 4 shows the timing when data is input to the LCD driver 2. FIG. 4 (a) shows the timing of the signal RS, and FIG. 4 (b) shows the timing of the input terminal R /.
The timing of the "L" level R / W signal (ie, write signal) input to W is shown. FIG. 4 (c)
4 shows the timing of the capture signal E input to the input terminal E, and FIG. 4D shows the timing of the 8-bit parallel data DB0 to DB7 data input to the data input terminal DB.

That is, when inputting display data, the LCD driver 2 scans the input data of the data input terminal DB when the signal of the input terminal R / W indicates a write state (ie, "L" level). The data is captured as valid data at the falling point of the capture signal E shown in FIG. By outputting the fetched data to the LCD 1, the LCD 1
1 is displayed according to the input data.

[0007]

When this LCD drive circuit is used in a low power consumption public telephone connected to a telephone line and operated only by a station power supply, the LCD and the driver originally have low power consumption. Therefore, low power consumption of the CPU is required. For this reason, the above-mentioned Z80 type CPU having a sleeping mode is used,
The PU performs the processing intermittently without performing the processing at all times, and stops the processing operation after the processing is completed to enter the sleeping mode. The current consumption of the CPU in the sleeping mode is about 1.5 mA when the power supply voltage is 5 V.

[0008] In recent years, such public telephones include, for example, I
In order to make a call using a C card or the like,
The provision of a C card interface is being considered. When such an interface is provided in a public telephone, the power consumption of the public telephone further increases, and the public telephone cannot operate on the office power supply. Therefore, the CPU must be replaced with a CPU with lower power consumption.

The CPU to be newly introduced is an Intel CPU and consumes about 20 μA when the power supply voltage is 5 V in the sleeping mode.
Even if the card interface is provided in the public telephone, the public telephone can be operated only by the office power supply. However, from this newly introduced Intel CPU, LCD
When sending display data to the driver 2, this CP
In U, it is difficult to output each control signal in accordance with the input timing of the LCD driver 2, and the LCD
There was a problem that the driver could not be controlled. Therefore, an object of the present invention is to control the LCD driver with a simple configuration when outputting data from the low power consumption CPU to the LCD driver to drive the LCD.

[0010]

In order to solve such a problem, the present invention provides an LCD, a first input terminal for inputting data, and a second input terminal for inputting signals indicating data read / write. And a third input terminal for inputting a data capture signal for capturing data, and when the data capture signal of the third input terminal falls, the signal of the second input terminal is written. When a state is indicated, data of the first input terminal is taken in, an LCD driver for driving the LCD and displaying the data, a first output terminal for outputting data, and a second output terminal for generating a write signal when outputting data. And a CPU having a third output terminal for outputting a chip select signal for selecting an LCD driver, and driving the LCD driver by the CPU.
A driving circuit for connecting a first output terminal of the CPU to a first input terminal of the LCD driver to output data from the CPU to the LCD driver; and a chip select signal from the third output terminal of the CPU. Means for supplying a signal indicating a write state of data to a second input terminal of the LCD driver; and a third circuit of the LCD driver for inverting a write signal from a second output terminal of the CPU as the capture signal.
And a means for supplying to the input terminal of (1). As a result, data output control to the LCD driver can be performed with a simple configuration. Also, a buffer which gives the data from the CPU to the LCD driver in the data write mode by the chip select signal and a write signal from the second output terminal of the CPU and a chip select signal from the third output terminal are transmitted to the buffer. Means for inputting, inverting each input signal, and applying a logical product output of the inverted signals to the third input terminal of the LCD driver as the capture signal. Therefore, only when the LCD driver is selected by the chip select signal, the display data is taken into the LCD driver, so that erroneous display of the LCD due to noise or the like can be prevented.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an LCD drive circuit according to the present invention. In FIG.
The driving circuit is composed of LCD1 and LC when display data is input.
LCD driver 2 for driving D1 and LCD driver 2
, A three-state buffer connected to a data bus between the LCD driver 2 and the CPU 3, an address decoder 5 for decoding an address of the CPU 3 and generating a chip select signal CS, It comprises a CS and a NOR circuit NOR which inputs a write signal of the CPU 3 and supplies it to the LCD driver 2.
The CPU 3 is an Intel CPU and has a sleeping mode. The current consumption in the sleeping mode is about 20 μA when the power supply voltage is 5V.

The LCD driver 2 has a data input terminal DB for inputting display data, an input terminal R / W for inputting signals indicating data read / write, and an input terminal for inputting a signal for input data input. E, LCD
Input terminal R for inputting an RS signal for display-scanning 1
S is provided. The timing of the signal of each input terminal when the display data is input from the CPU 3 is as shown in FIG.

Here, when the CPU 3 sends data to the LCD driver 2 for display on the LCD 1, the CPU 3 first sends an address signal for selecting the LCD driver 2 to the address decoder 5 from an address terminal AB connected to an address bus. At the same time, the display data is output from the 8-bit data output terminal DB to the LCD driver 2 via the data bus. At this time, an "L" level write signal indicating data write is output from the write terminal WR (bar).

The address decoder 5 converts the input address signal into one "L" level chip select signal CS.
The output is to the three-state buffer 4, the input terminal R / W of the LCD driver 2, and one input terminal of the NOR circuit NOR. The 3-state buffer 4 is always in a read mode in which data is sent to the CPU 3 side.
When the “L” level chip select signal CS is applied, the mode is changed to a write mode in which display data from the CPU 3 is transmitted to the LCD driver 2. Then, the display data from the CPU 3 is output to the data input terminal DB of the LCD driver 2 according to the chip select signal CS.

When the NOR circuit NOR receives the above-mentioned "L" level chip select signal CS and the "L" level write signal from the CPU 3, the NOR circuit NOR inverts these input signals and respectively inverts the inverted signals. AND and
This logical product signal is applied to the input terminal E of the LCD driver 2. When the logical product signal is input, the LCD driver 2 inputs the data at the rising edge of the logical product signal if the signal given to the input terminal R / W (that is, the chip select signal CS) is at “L” level. The 8-bit display data of the terminal DB is taken in. The acquired data is provided to the LCD 1 to be displayed on the LCD 1.

FIG. 2 is a timing chart showing the timing of each signal provided from the CPU 3 to the LCD 2.
The operation of the main part of the present invention will be described in more detail based on this timing chart. Here, as shown in FIG. 1, the lowest address terminal A0 of the CPU 3 is connected to an input terminal RS for inputting an RS signal for display scanning of the LCD 1, and the lowest address which constantly changes when the CPU 3 operates. The signal A0 is supplied to the LCD driver 2 as an RS signal (FIG. 2A).

When the CPU 3 sends data to the LCD driver 2 and causes the LCD 1 to display the data, first, the LCD 3
When an address signal for selecting the driver 2 is sent to the address decoder 5, the address decoder 5 outputs an "L" level chip select signal CS at the timing shown in FIG. This chip select signal CS is output until the selection of the LCD driver 2 ends, and as described above, the three-state buffer 4 and the LCD
The signal is transmitted to the input terminal R / W of the driver 2 and one input terminal of the NOR circuit NOR. After that, a write signal of “L” level is output from the write terminal WR of the CPU 3 at the time shown in FIG. This write signal is output until the time point and sent to the other input terminal of the NOR circuit NOR.

In the NOR circuit NOR, when a chip select signal CS and a write signal from the CPU 3 are input, each of these input signals is inverted to obtain a logical product of the inverted signals. As a result, as shown in FIG.
Is the logical product output of the NOR circuit NOR, and is applied to the input terminal E of the LCD driver 2. The LCD driver 2 has already been output from the CPU 3
The 8-bit data (DB0 to DB) reaching the data input terminal DB from the state buffer 4 shown in FIG.
7) is fetched at the rise (time) of the logical product signal from the NOR circuit NOR in FIG.

As described above, a general low-cost and low-power consumption terminal having a data output terminal DB for outputting a data signal, an address output terminal AB for outputting an address signal, and a write terminal WR (bar) for outputting a write signal indicating data writing. When outputting data to the LCD driver 2 using the CPU 3 with low power, an address decoder 5 that decodes an address signal from the CPU 3 and outputs a chip select signal CS for selecting the LCD driver 2, and an LCD
A three-state buffer 4 that outputs data from the CPU 3 to the LCD driver only when data is output to the driver 2, and outputs a low signal in response to the chip select signal CS and the write signal.
A NOR circuit NOR for outputting a capture signal for capturing the display data to the CD driver 2 is provided so as to generate the output timing of each control signal shown in FIG. 2 which matches the data input timing of the LCD driver 2 in FIG. It was done. As a result, data output control to the LCD driver 2 can be performed with a simple configuration.

In this embodiment, the NOR circuit NO
R and the chip select signal and the write terminal W of the CPU.
Although the write signal from R (bar) is input and a data fetch signal is output to the LCD driver 2, the fetch signal from the NOR circuit NOR shown in FIG. )
Since the write signal of FIG. 2C is inverted, a signal obtained by simply inverting the write signal of FIG. 2C by an inverter may be generated as a capture signal. If the CPU 3 is a CPU having an output port, the address decoder 5 for generating the chip select signal CS from the address signal is omitted, and when the display data is output, the output port is set to “L” level to generate the chip select signal. Alternatively, it may be output to the LCD driver 2 or the like.
Alternatively, the three-state buffer 4 may be omitted, and the data output terminal DB of the CPU 3 and the data input terminal DB of the LCD driver 2 may be directly connected. Also, this L
The CD drive circuit is used for a public telephone operated by the office power supply, but can be applied not only to a public telephone operated by the office power supply but also to other devices requiring low power consumption. .

[0021]

As described above, according to the present invention, when display data is sent to the LCD driver by the low power consumption CPU and displayed on the LCD, the first output terminal of the CPU and the first output terminal of the LCD driver are used. Connected to the input terminal of
Means for outputting data from U to the LCD driver;
The chip select signal from the third output terminal of the PU is set to LC
Means for supplying a signal indicating a data write state to the second input terminal of the D driver; and inverting the write signal from the second output terminal of the CPU and taking this signal as an L signal.
Since the means for supplying to the third input terminal of the CD driver is provided, data can be transmitted to the LCD driver and displayed on the LCD with a simple configuration. Also, a buffer which gives the data from the CPU to the LCD driver in the data write mode by the chip select signal and a write signal from the second output terminal of the CPU and a chip select signal from the third output terminal are transmitted to the buffer. Means for inputting and inverting each of the input signals, and applying a logical product output of the inverted signals to the third input terminal of the LCD driver as a capture signal. Only when the display is performed, the display data is taken into the LCD driver, so that erroneous data is not taken in due to noise or the like, and thus erroneous display of the LCD can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an LCD drive circuit according to the present invention.

FIG. 2 is a timing chart showing the timing of each signal output from the drive circuit to an LCD driver.

FIG. 3 is a block diagram showing a configuration of a conventional LCD drive circuit.

FIG. 4 is a timing chart showing the timing of each signal when data is input to the LCD driver.

[Explanation of symbols]

1 LCD, 2 LCD driver, 3 CPU, 4 3
State buffer, 5 ... address decoder, NOR ... NOR circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/13 505 G09G 3/18

Claims (2)

(57) [Claims] 1. An LCD, a first input terminal for inputting data, a second input terminal for inputting a signal indicating data read / write, and a third input terminal for inputting a capture signal for capturing data. And when the signal of the second input terminal indicates a data write state at the time of falling of the capture signal of the third input terminal, captures the data of the first input terminal. An LCD driver for driving the LCD panel to display the captured data, a first output terminal for outputting data, a second output terminal for generating a write signal when outputting data, and a chip for selecting the LCD driver. An LCD drive circuit comprising a CPU having a third output terminal for outputting a select signal, wherein the LCD drives a LCD driver by the CPU; Means for outputting data from and connecting the first input terminal of the D-driver CPU to the LCD driver, the chip select signal L
Means for supplying a signal indicating a write state of data to a second input terminal of the CD driver, and means for inverting a write signal from a second output terminal of the CPU and supplying the inverted signal to a third input terminal of the LCD driver An LCD drive circuit comprising: 2. The buffer according to claim 1, wherein the chip select signal causes a data write mode, and a buffer for supplying data from the CPU to an LCD driver, a write signal from a second output terminal of the CPU, and a third output. Means for inputting each signal of the chip select signal from the terminal, inverting each input signal, and providing a logical product output of each inverted signal to the third input terminal of the LCD driver as the capture signal. An LCD driving circuit, comprising: