JP3350669B2 - Semiconductor output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor output circuit constituting an output stage of a bipolar integrated circuit.

[0002]

2. Description of the Related Art A semiconductor output circuit according to the present invention is a bipolar type integrated circuit in which an output circuit is integrated together with a main circuit such as a signal processing circuit, and is connected to the output circuit by a signal from the main circuit such as a signal processing circuit. To turn on and off the external load circuit.

(First Conventional Example) FIG. 1 is a specific equivalent circuit diagram showing a first conventional example of an output circuit used in a bipolar integrated circuit. In this output circuit 1, a current adjusting resistor 12 (a resistance value is represented by R1) having one end connected to a reference line 11 of a reference potential Vs (> 0) and an input terminal 13 are connected to a base. Resistance 12
Of which the collector and the emitter are respectively connected to the other end of the ground and the ground line 14 of the ground potential Vg (= 0 volt)
An input transistor 15, an npn output transistor 17 having a base connected to a connection point of the resistor 12 and the collector of the input transistor 15, an emitter connected to the ground line 14, and a collector connected to the output terminal 16. I have.

When a low signal (for example, a signal of voltage Vg) is input from the main circuit (not shown) to the input terminal 13, the input-side transistor 15 is kept off and the collector-emitter between the collector and the emitter is maintained. Is opened, the voltage of the reference potential Vs is applied to the base of the output transistor 17 through the resistor 12, and the output transistor 17 is turned on. At this time, the base resistor 12 and the output transistor 17, saturation _{I B = (Vs- [V BE} ] sat) / R1 ... base current flows in _{(1) ([V BE]} sat is the output transistor 17 At the base-emitter voltage). Accordingly, a load circuit (not shown) connected between the collector and the emitter of the output transistor 17 is turned on, and a current flows through the load circuit.

Here, the magnitude of the current required by the load circuit is represented by I
r, when the amplification factor of the output transistor 17 and h _FE (>> 1), the output transistor 17 during on-must supply a large base current I _B than Ir / h _FE, the resistance value R
Since one becomes the base current I _B is reduced significantly, the resistance R1 there is an upper limit. That is, I _B > (Ir / h
From _F E) and the above formula (1), the resistance value R1 should satisfy the _{{(Vs- [V BE] sat} ) h FE / Ir}> R1 ... (2).

When a high signal (for example, a signal having a reference potential Vs) is input from the main circuit to the input terminal 13, a current flows between the base and the emitter, and the input transistor 15 is turned on. When the input-side transistor 15 is turned on, the base voltage of the output transistor 17 drops to the collector-emitter voltage (saturation voltage) Vsat = [V _CE ] sat in the saturation region of the input-side transistor 15, so that the output transistor 17 is turned off. And the load circuit is turned off.

However, in the output circuit 1 having such a configuration, even when the output transistor 17 is turned off, the current (Vs-Vsat) / R1 is supplied to the resistor 12 through the collector and the emitter of the input-side transistor 15. … (3) flows. As described above, the resistance value R1 has an upper limit in relation to the load circuit current, and the value of the resistor 12 cannot be increased arbitrarily. There is a problem that the consumption current I _OFF = (Vs−Vsat) / R1 (4) cannot be reduced. In particular, when used in a device driven by a charging battery, if the current consumption (power consumption) in the off state is large, the use time of the portable device is shortened, which is a fatal disadvantage.

(Second Conventional Example) FIG. 2 is a specific equivalent circuit diagram showing a second conventional example of an output circuit used in a bipolar integrated circuit. This output circuit 2
1 uses a constant current source 18 instead of the resistor 12 in the output circuit 1 of FIG. This output circuit 2 includes a resistor 1
2 is replaced by the constant current source 18 and operates in the same manner as the output circuit 1 of FIG.

[0009] However, even in this output circuit 2, the output transistor 17 during the off current flows I ₀ between the collector and the emitter of the input-side transistor 15 by the constant current source 18. The current I ₀ supplied by the constant current source 18 is also Ir /
Since a value larger than h _FE is required, the output circuit 1 of FIG.
Similarly, there is a problem that the current consumption when the load circuit (output transistor 17) is off is large.

(Third Conventional Example) FIG. 3 shows a conventional example of an output circuit which solves such a disadvantage that the current consumption when the output is off is large. In this output circuit 3, a resistor 19 (one end of which is represented by R2) connected to one end of the reference line 11 of the reference potential Vs, and a current adjusting resistor 20 (one end of which is also connected to the reference line 11) A resistor 21 having one end connected to the ground line 14 (represented by R4), an input terminal 13
And the other end of the resistor 19 and the ground line 14
The base is connected to a connection point between an npn input-side transistor 15 having a collector and an emitter connected thereto, a resistor 19 and a collector of the input-side transistor 15, and a resistor 20 on a reference line 11 side and a resistor 21 on a ground line 14 side. The base is connected to a connection point between the resistor 21 and the emitter of the transistor 22, the emitter is connected to the ground line 14, and the collector is connected to the output terminal 16. And an npn output transistor 17.

When a low signal is input to the input terminal 13 from the main circuit, the input side transistor 15 is kept off, so that the voltage of the reference potential Vs is applied to the base of the transistor 22 in the middle stage. 22 is turned on, and current flows between the resistor 20 and the collector and emitter of the transistor 22 and between the resistor 21 and the base and emitter of the output transistor 17. Accordingly, the output transistor 17 is turned on, and the load circuit connected between the collector and the emitter of the output transistor 17 is turned on.

When a high signal is input to the input terminal 13, the input-side transistor 15 is turned on. When the input side transistor 15 is turned on, the input side transistor 1
5, the collector-emitter voltage (= base voltage of the transistor 22) drops to the saturation voltage Vsat, so that the transistor 22 is turned off and the output transistor 17
Also turns off.

In the output circuit 3 having such a configuration, when the output transistor 17 is turned on, the current I ₂ = (Vs−2 [V _BE ] sat) / R2 which flows through the resistor 19 is applied to the load circuit current Ir of (5). Contributes to I ₂ · h _FE ² , and the current I ₃ = (Vs−Vsat− [V _BE ] sat) / R3 (6) contributes to the load circuit current Ir of I ₃ · h _FE. Becomes Therefore, the current by the resistance value R2 of the resistor 19 is increased to be negligibly small contribution of the current I ₂ flowing through the resistor 19, to sufficiently reduce the value R3 of the resistor 20 I
₃ , the required load circuit current Ir can be obtained. On the other hand, when the output transistor 17 is off, no current flows through the resistor 20, and only current flows through the input transistor 15 to the resistor 19. , The total current consumption I _OFF = (Vs−Vsat) / R2 (7) in the resistors 19 and 20 can be reduced.

However, such an output circuit 3 has a problem that the switching operation speed is reduced. That is, since the transistor 22 in the middle stage is driven in the saturation region during the ON operation, carriers (particularly, electrons) are accumulated in the base region (called a carrier accumulation effect). For this reason, even if the input-side transistor 15 switches from off to on, the output transistor 22 does not turn off until the carriers stored in the transistor 22 are almost completely discharged, and the output transistor 17 does not turn on.
Is delayed more than the input-side transistor 15, and the switching operation speed of the output transistor 17 from on to off is reduced.

(Fourth Conventional Example) FIG. 4 shows another conventional example in which the current consumption when the output is turned off is reduced. This output circuit 4 uses a current mirror circuit 23 composed of two pnp transistors 24 and 25.
The bases of two pnp transistors 24 and 25 are connected, the respective emitters are connected to the reference line 11 of the reference potential Vs, the current mirror circuit 23 in which the base and the collector of one transistor 24 are directly connected, and the input terminal 13 is used as the base. Npn input-side transistor 15 whose emitter is connected to ground line 14, and a resistor 2 connected between the collector of one transistor 24 of current mirror circuit 23 and the collector of input-side transistor 15.
6. A resistor 27 connected between the collector of the other transistor 25 constituting the current mirror circuit 23 and the ground line 14, a collector and a resistor 27 of the transistor 25
And an npn output transistor 17 having a base connected to the connection point, an emitter connected to the ground line 14, and a collector connected to the output terminal 16.

In the output circuit 4, the input terminal 13
When a high signal is input to the input side transistor 15 to turn on the input side transistor 15, both transistors 2 of the current mirror circuit 23 are turned on.
4 and 25 are turned on, current flows through both resistors 26 and 27, and the base voltage of the output transistor 17 becomes (Vs-Vsa
t), the output transistor 17 is turned on.

On the other hand, when a low signal is input to the input terminal 13 and the input transistor 15 is turned off, both transistors 24 and 25 of the current mirror circuit 23 are also turned off, so that the output transistor 17 is also turned off. At this time, since no current flows through the resistors 26 and 27, the current consumption I _OFF when the output is turned off can be extremely reduced.

However, a pnp transistor (current mirror circuit 2) manufactured in a bipolar integrated circuit is used.
3 has a lower operation speed than the npn transistor due to its structure (lateral structure), so that even in the output circuit 4, the output transistor 1
7 has a low on / off operation speed.

[0019]

As described above,
The conventional semiconductor output circuit has a problem that the current consumption when the output is turned off is large or the operation speed is slow.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example. It is an object of the present invention to provide a high-speed switching operation of an output transistor from ON to OFF and OFF to ON operation, and furthermore, an output OFF operation. It is an object of the present invention to provide a semiconductor output circuit in a bipolar integrated circuit which consumes a small amount of current (power consumption) at the time.

[0021]

A semiconductor output circuit according to the present invention has a first resistor connected at one end to a high potential line, an input terminal connected to a base, and a low resistance connected to the other end of the first resistor. A first n connected between the collector and the emitter between the first n
a pn transistor and a second terminal having one end connected to a high potential line.
And a second np having a base connected to the base of the first transistor and an emitter connected to the low potential line.
an n-transistor, a base connected to a connection point between the other end of the first resistor and the collector of the first transistor, and a base connected between the other end of the second resistor and the collector of the second transistor; A base is connected to a connection point between the collector of the second transistor and the emitter of the third transistor, the emitter is connected to a low potential line, and the collector is output. An npn output transistor connected to the terminal;
It is composed of

In this semiconductor output circuit, when the output transistor is turned on, the first transistor is turned off and the third transistor is driven in a saturation region. When the output transistor is turned off, the first transistor is turned off. And driving the third transistor in the unsaturated region.

[0023]

In the semiconductor output circuit of the present invention, when a low signal is input to the input terminal, the first transistor and the second transistor are turned off, so that the third transistor and the output transistor are turned off. Is turned on, and when a load circuit is connected to the output transistor, the load circuit is closed.

When a high signal is input to the input terminal, the first transistor and the second transistor are turned on. At this time, the first transistor is set to be turned on in a non-saturated state, and the second transistor is set to be turned on in a saturated state, so that the third transistor is set to be kept on in a non-saturated state. can do. At this time, the base voltage of the output transistor is
The transistor is turned off because of its saturation voltage. Therefore, when a load circuit is connected to the output transistor, the load circuit is opened.

Here, the current flowing in the load circuit when the output transistor is turned on is the current (× h _FE) flowing in the first resistor.
² ) and the current (× h _FE ) flowing through the second resistor. Therefore, even if the value of the first resistor is increased and the contribution from the current flowing through the first resistor is reduced, the value of the second resistor is reduced and the contribution from the current flowing through the second resistor is sufficiently increased. By increasing the current, it is possible to flow a current of a necessary level to the load circuit. Thus,
If a first resistor having a sufficiently large resistance is used and a second resistor having a resistance as small as necessary is used, when the output transistor is turned off, both the first resistor and the second resistor have currents. Flows, but the overall current consumption can be reduced. That is, since the value of the first resistor can be increased, the current consumption by the first resistor becomes very small. When the first and third transistors are driven in an unsaturated state, the current flowing through the second resistor is smaller than the current flowing through the first resistor. As a result, the current consumption when the output is turned off can be reduced as compared with the first conventional example and the second conventional example.

Also, according to the present invention, since the second transistor is connected to the base of the output transistor, the output transistor can be quickly turned off by turning on the second transistor when the output is off, The switching speed of the output transistor from ON to OFF can be increased. That is, it is possible to prevent the on / off switching speed of the output transistor from being reduced by the carrier accumulation effect of the third transistor.

Further, when the output transistor is off, the first
If the third transistor is turned on in the non-saturated state and the third transistor is kept in the saturated state when the output is on and off in the off state, respectively, when the output is switched from off to on, As the off speed of the first transistor increases, the off operations of the first transistor and the second transistor are performed simultaneously in parallel. As a result, the output transistor can be quickly turned on, and the switching speed of the output transistor from off to on can be increased.

Further, since the semiconductor output circuit of the present invention is composed of only npn transistors, even if it is manufactured in a bipolar integrated circuit, it is possible to increase the switching speed without lowering the operation speed. it can.

[0029]

FIG. 5 shows an embodiment of the present invention. The semiconductor output circuit 31 according to the present invention is an output circuit of a bipolar type integrated circuit manufactured by using a semiconductor manufacturing process in a semiconductor substrate such as a silicon wafer, and FIG. 3 shows an equivalent circuit.

(Construction) The semiconductor output circuit 31 includes two resistors 32 and 33 (resistors R6 and R7, respectively) and four bipolar npn transistors 34 and
35, 36, and 37. The input-side transistor 34 has a base connected to the input terminal 38, an emitter connected to a low-potential (ground potential Vg) ground line 39, and a collector connected to the resistor 32. One end of the resistor 32 is connected to the collector of the input-side transistor 34, and the other end is connected to a high potential (reference potential Vs) reference line 40. The base of the transistor 35 is connected to the base of the input transistor 34 (or the input terminal 38), and the base of the transistor 36 is connected to the connection point between the collector of the input transistor 34 and the resistor 32. The transistors 35 and 36 have the collector of the transistor 35 connected to the emitter of the transistor 36, the emitter of the transistor 35 is connected to the ground line 39, and the collector of the transistor 36 is connected to the resistor 33. The other end of the resistor 33 connected to the collector of the transistor 36 is connected to the reference line 40.
The output transistor 37 has a base connected to a connection point between the collector of the transistor 35 and the emitter of the transistor 36, an emitter connected to the ground line 39, and a collector (open collector) connected to the output terminal 41. The input terminal 38 is connected to a main circuit such as a signal processing circuit in the integrated circuit, and the output terminal 41 is connected to an external load circuit.

Here, the transistor 35 is connected to the input terminal 3
It is designed to perform an on (saturation region) and off switching operation according to the high and low of the signal input to 8. On the other hand, the input-side transistor 34 is designed to be turned on (unsaturated region) and turned off by the high and low of the signal input to the input terminal 38. The transistor 36 is designed to turn on in a non-saturation region and a saturation region, respectively, according to the high and low levels of a signal input to the input terminal 38. The output transistor 37 is designed to perform off / on (saturation region) switching operation according to the high / low of a signal input to the input terminal 38.

The state when the output is off will be described in detail as follows. Figure 6 is the base current I _B is in the case of a constant collector-emitter voltage V _CE - is a curve showing the relationship between the collector current I _C. Input-side transistor 34 and transistor 35, V _CE -I _C for because both connected to the base to the input terminal 38 equals the base voltage, therefore the same base current as shown in FIG. 6 (I _B = const.)
Works on curves. The transistor 35 is designed to turn on in a saturation region (for example, point Q2) when the input is high (output is off), and is designed so that the collector-emitter voltage V _CE = Vsat the collector current I _C = I _C2 (8) I have. Input side transistor 34
Is in an unsaturated region (for example, Q
(One point), and the collector-emitter voltage V _CE = Vsat + [V _BE ] nonsat collector current I _C = I _C1 (9) Here, Vsat = [V _CE ] s
at is the saturation voltage when the transistor 35 is on, [V _BE ] nons
at is the base-emitter voltage in the unsaturated region of the transistor 36. In addition, the collector current satisfies I _C1 > I _C2 (10). As a result, when the input is high (output is off), a voltage of [V _CE ] nonsat is applied between the base and the emitter of the transistor 36, and the transistor 36 is not turned off even when the output is off, and is kept in an on state without saturation. Dripping.

(Operation at Output On) In this output circuit 31, when a low signal is input to the input terminal 38,
The input side transistor 34 and the transistor 35 are both turned off, and the reference potential Vs is applied to the base of the transistor 36 through the resistor 32. As a result, the transistor 36
Base current flows from the base-emitter of the output transistor 37 to the base-emitter of the output transistor 37,
And the output transistor 37 is turned on. Further, when the transistor 36 is turned on, a large base current flows to the output transistor 37 through the resistor 33, and the output terminal 41
The load circuit connected to is closed and the large load circuit current Ir
Flows.

At this time, since the transistor 36 is on in the saturation region, the current I ₇ flowing through the resistor 33 is I ₇ = (Vs−Vsat− [V _BE ] sat) / R7. Here, Vsat is the saturation voltage of the transistor 36, and [V _BE ] sat is the base-emitter voltage of the output transistor 37 operating on in the saturation region. The current required for the load circuit and Ir, if the amplification factor of the output transistor 37 and h _FE, as the base current I _B of the output transistor 37, since the Ir / h _FE or more current is required, as a resistor 33 is, I _7> than _{(Ir / h FE) {(} Vs-Vsat- [V bE] sat) h FE / Ir}> R7 ... (11) and small and may be used as the resistance value R7 so.
On the other hand, the resistance value R6 of the resistor 32, the transistor 36 may be set so can safely base current I _B in the output transistor 37 in the output ON. This condition is that if the amplification factors of the transistor 36 and the output transistor 37 are both h _FE , the current I ₆ flowing through the resistor 32 becomes
Since it suffices that I ₆ > (Ir / h _FE ² ), I ₆ = {(Vs−2 [V _BE ] sat) / R6}> Ir / h _FE ² , and the resistance R6 satisfies the condition ｛(Vs− 2 [V _BE ] sat) h _FE ² / Ir｝> R6 (12) Here, [V _BE ] sat is the base-emitter voltage of the transistor 36 and the output transistor 37 during the saturation operation. Therefore, comparing the expressions (11) and (12), the value R6 of the resistor 32 is about _hFE times larger than the value R7 of the resistor 33 and the value R1 of the resistor 12 of the conventional output circuit 1 of FIG. For example, a value of h _FE ≒ 100) can be used.

(Operation when output is off) Also, the input terminal 38
When a high signal is applied to the input side transistor 34
And the transistor 35 is turned on. Here, the input-side transistor 34 is turned on in the non-saturation region (point Q1 in FIG. 6) as shown by the equation (9), and the transistor 35 is turned on in the saturation region (the point in FIG. 6) as shown in the equation (8). Since the transistor is turned on at the point Q2), the voltage of [V _BE ] nonsat is also applied to the base of the transistor 36, and the transistor 36 is kept off in the non-saturation region without being turned off. On the other hand, when the transistor 35 is turned on, the base voltage of the output transistor 37 is reduced to Vsat. Therefore, even if the transistor 36 is on, the output transistor 37 is turned off, and the load circuit connected to the output transistor 37 is opened. .

In this output off state, since the input side transistor 34 and the transistors 35 and 36 are on, current flows through both of the resistors 32 and 33. The current consumption is about 2 / h compared to the current consumption of the output circuit 1 or the output circuit 2 of the conventional example.
_{It is} about _FE . That is, since the resistance value R6 of the resistor 32 can be set to about h _FE as compared with the conventional circuit (see the equation (12)), the current consumption in the resistor 32 is about 1 / h _FE . Also,
Since the current I _C2 flowing through the transistor 35 is smaller than the current I _C1 flowing through the input-side transistor 34 (see equation (10)), it is estimated that the current consumed by the resistor 33 is substantially equal to the current consumed by the resistor 32. And the current consumption when the output is turned off by the resistors 32 and 33 is at most about 2 / h of the conventional circuit.
_FE, and if h _FE = 100, 1/5 of the conventional circuit
The current consumption is about 0.

(Comparison of Current Consumption of Output Circuit of Present Invention and Conventional Output Circuit) The current consumption of the conventional output circuit 1 (FIG. 1) and the output circuit 2 (FIG. 2) and the consumption of the output circuit 31 of the present invention. Compare with current. Assume that the value of the current required in the load circuit is Ir = 100 mA, the amplification factor of each transistor is h _FE = 100, and the reference potential Vs = 5 V
And In the saturated state, it is assumed that the saturation voltage Vsat of each transistor is 0.1 V and [V _BE ] sat is 0.7 V.
First, consider the conventional output circuit 1 of FIG. To flow to the output transistor 17 during on-current of Ir = 100 mA, the base current of the output transistor 17 becomes _{I B = Ir / h FE =} 100/100 = 1 [mA] necessary. Since the base voltage [V _BE] sat of the output transistor 17 at this time is 0.7 V, in order to flow of 1mA base current I _B, the resistance value _{R1 = (Vs- [V BE]} sat) / I B = (5−0.7) /1=4.3 [kΩ] At this time, when the input-side transistor 15 is turned on and the output is turned off, the collector voltage of the input-side transistor 15 becomes the saturation voltage Vsat.
I _OFF = (Vs-Vsat) / R1 = (5-0.1) / 4.
3 = 1.14 [mA]. Next, considering the conventional output circuit 2 of FIG.
In order to supply a base current of 1 mA to the output transistor 17, it is necessary to use a constant current source 18 of 1 mA. Therefore, the current consumption is also 1 mA. Next, consider the output circuit 31 of the present invention. When the output transistor 37 is turned on, Ir
= To flow a current of 100mA, referring to (11), R7 = (Vs-Vsat- [ V BE] sat) h FE / Ir = (5-0.1-0.7) × 100 / 100 = 4.2 [kΩ]. Next, the (12) With reference to formula, R6 = (Vs-2 [ V BE] sat) h FE 2 / Ir = (5-2 × 0.7) × 100 2/100 = 360 [kΩ] . When the output is off, the base of transistor 36
Assuming that the emitter-to-emitter voltage [V _BE ] nonsat = 0.7 V, the consumption current I ₆ in the resistor 32 is I ₆ = (Vs−Vsat− [V _BE ] nonsat) / R6 = (5−0.1−0. 7) /360=0.012 [mA]. The current I _C1 flowing through the output transistor 34
≒ I ₆ and the current I _C2 ≒ I ₇ flowing through the transistor 35 are:
Since the transistor 35 is saturated, I _{C 2} = (1
/ 10) I _C1 , then I ₇ = (1/10) I ₆ = 0.1 × 0.012 = 0.001 [mA]. Therefore, the current consumption as a whole is I ₆ + I ₇ = 0.013 [mA]. Therefore, according to the output circuit 31 of the present invention, it can be seen that the current consumption is extremely small as compared with the conventional circuit.

Next, the output of the output circuit 31 is turned on.
Consider the switching operation speed at the time of off. Input terminal 3
When the input signal at 8 is low and the transistor 36 is on, the transistor 36 is saturated, and carriers are stored in the transistor 36 when it is on, like the transistor 22 of the conventional output circuit 3. . However, when the input signal at the input terminal 38 is switched to high, the transistor 35 is quickly saturated and turned on, and the base voltage of the output transistor 37 is reduced to Vsat, so that whether or not carriers are accumulated in the transistor 36 is determined. , The output transistor 37 is quickly turned off. Therefore, compared with the conventional output circuit 3 (FIG. 3),
The switching speed when the output is turned on → off can be increased.

The switching operation speed when the output is turned off → on in the output circuit 31 will be described. In the conventional output circuit 3 (FIG. 3), when the output is off, the input side transistor 15 is completely saturated and turned on. Therefore, when the input signal is switched from high to low, the input side transistor 15 becomes saturated. From OFF to OFF, and then the transistor 22 is saturated from OFF to ON and turned ON.
Therefore, it takes time for the input-side transistor 15 to turn off from the saturated state, and furthermore, the input-side transistor 1
It takes time until the transistor 22 is turned on because of the sequential operation of the transistor 5 and the transistor 22, and as a result, the speed at which the output transistor 17 is turned on is reduced. On the other hand, in the output circuit 31 according to the present invention, when the output is off, the transistor 34 is turned on in an unsaturated state, so that when the input signal of the input terminal 38 switches from high to low, the input side transistor 34 Switch off time is shortened. Further, since the transistor 36 is kept on both when the output is on and when the output is off, when the input signal switches from high to low, the operation of switching off the input side transistor 34 and the operation of the transistor 35
Is switched off from the saturated state at the same time. As a result, according to the output circuit 31 of the present invention, the speed at which the output is switched from off to on can be shorter than that of the conventional circuit.

The transistors 34, 35, 36, 3
7 uses npn transistors, so that the switching speed does not become slow due to the use of pnp transistors as in the conventional output circuit 4 (FIG. 4).

(Application Example) The output circuit according to the present invention can output an ON / OFF signal from an output circuit and apply a hysteresis to a circuit preceding the output circuit. This is suitable for use in a situation where the hysteresis must be applied first and the response speed is required on the output circuit side.

More specifically, good results can be obtained by using the A / D conversion circuit having a hysteresis operation as shown in FIG. In A / D conversion circuit of FIG. 7, an analog input signal S1 is input to the non-inverting input terminal of the comparator 51, the reference voltage V ₀ is applied from the reference voltage generating circuit 52 to the inverting input terminal. From the output terminal of the comparator 51, the input signal S1 and the reference voltage V
_A high (H) or low (L) comparison signal S2 is output according to the magnitude of ₀ . The comparison output of the comparator 51 is fed back to the reference voltage generation circuit 52 via a hysteresis circuit 53 connected to the output terminal. Thus, the reference voltage V ₀ output from the reference voltage generation circuit 52 is set to V ₀₊ or V ₀₊ according to the high or low of the comparison signal S2 output from the comparator 51 by the operation of the hysteresis circuit 53.
₀₋ (V ₀₊ ≠ V ₀₋ ), and the output of the comparator 51 is subjected to hysteresis. The output side of the output circuit 54 connected to the output terminal of the comparator 51 is turned off or on in response to the high or low of the comparison signal S2.

In the case of such a circuit configuration, as shown in FIG. 8, the comparison signal S2 output from the comparator 51
(FIG. 8A) is fed back through the hysteresis circuit 53 and the reference voltage generation circuit 52, and the reference voltage V ₀ (FIG.
It is necessary to make the speed of the output signal S3 (FIG. 8C) of the output circuit 54 slower than the speed of changing (b)). Therefore, the output circuit 54
In the conventional output circuit 54, the delay time ΔT is considerably large, and the response speed at which the input signal S1 appears as the output signal S3 of the output circuit 54 is increased. Was slow. On the other hand, if the delay in the output circuit 54 is eliminated, the output signal S
The output from the output circuit 54 is faster than the feedback of 2 so that a desired circuit operation cannot be obtained.

On the other hand, if the semiconductor output circuit 31 according to the present invention is used as the output circuit 54, the response speed at the time of ON / OFF can be increased, so that the output circuit 44
By adjusting the delay time ΔT at the appropriate time, the delay time at the output circuit 44 can be made as short as possible within a range slower than the hysteresis side.
When the output circuit 44 (output transistor) is off, the delay time ΔT adjusted in this way is slower than that of the output circuit 1 of FIG. 1, and when the output circuit 44 (output transistor) is on, the output of FIG. It is set to be faster than the circuit 1.

[0045]

According to the present invention, as described above,
There is no problem that the current consumption increases when the output is turned off as in the first conventional example and the second conventional example.
The problem that the switching speed at the time of the output on / off switching operation becomes slow as in the prior art and the fourth prior art is also solved. That is, according to the present invention, there is provided a semiconductor output circuit in a bipolar integrated circuit in which the switching speed of an output transistor from on to off operation and off to on operation is high, and current consumption (power consumption) when output is off is small. can do.

[Brief description of the drawings]

FIG. 1 is a specific equivalent circuit diagram showing a first conventional example of a semiconductor output circuit.

FIG. 2 is a specific equivalent circuit diagram showing a second conventional example of a semiconductor output circuit.

FIG. 3 is a specific equivalent circuit diagram showing a third conventional example of a semiconductor output circuit.

FIG. 4 is a specific equivalent circuit diagram showing a fourth conventional example of a semiconductor output circuit.

FIG. 5 is a specific equivalent circuit diagram showing a semiconductor output circuit according to one embodiment of the present invention.

FIG. 6 is a diagram for explaining an operation of the semiconductor output circuit of the above.

FIG. 7 is a diagram showing an application circuit of the semiconductor output circuit according to the present invention.

FIG. 8 is an explanatory diagram of the application circuit.

[Explanation of symbols]

 32 (first) resistor 33 (second) resistor 34 input-side transistor (first transistor) 35 (second) transistor 36 (third) transistor 37 output transistor 38 input terminal 39 ground line (low potential) Line) 40 Reference line (high potential line) 41 Output terminal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-297123 (JP, A) JP-A-3-216017 (JP, A) JP-A-62-283716 (JP, A) 13227 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (2)

(57) [Claims] A first resistor having one end connected to a high potential line; an input terminal connected to a base; and a collector and an emitter connected between the other end of the first resistor and the low potential line. A first npn transistor, a second resistor having one end connected to a high potential line, a base connected to the base of the first transistor,
A second npn transistor having an emitter connected to a low potential line, a base connected to a connection point between the other end of the first resistor and a collector of the first transistor, and a second end of the second resistor A third npn transistor having a collector and an emitter connected between the collector of the second transistor and the collector of the second transistor; a base connected to a connection point between the collector of the second transistor and the emitter of the third transistor; N whose emitter is connected to the low potential line and whose collector is connected to the output terminal
and a pn output transistor. 2. When the output transistor is on, the first transistor is turned off and the third transistor is driven in a saturation region. When the output transistor is off, the first transistor and the third transistor are turned off. The semiconductor output circuit according to claim 1, wherein the semiconductor output circuit is driven in a saturation region.