JP3350356B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an improvement for realizing a double-window display without using an expensive dual-port memory having a large number of pins.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a configuration of a conventional image processing apparatus as a background of the present invention. The image processing device 171 combines a so-called double-window image, in which the thinned images are displayed in parallel on a single screen from two input image signals, that is, the main and sub image signals S1 and S2. And the output image signal S3
Output as

In FIG. 10, reference numeral 151 denotes an image conversion unit;
1 is a dual port RAM, 51 and 52 are horizontal filter / thinning units, 53 and 54 are line buffers,
Reference numerals 5 and 56 denote a vertical filter / thinning section, 59 a multiplexer, and 61 a control section.

[0004] The image converter 151 includes a main image signal S
1, a vertical synchronization signal Vsync1, a horizontal synchronization signal Hsync1, a dot clock DCLK1, a sub-image signal S2,
The vertical sync signal Vsync2 and horizontal sync signal Hsync of the sub-image
2. The dot clock DCLK2 is input at the same time.

When the main image signal S 1 passes through the horizontal filter / thinning section 51, it is thinned out along a line (scanning line), and further passes through the line buffer 53 and the vertical filter / thinning section 55. , Are thinned out in the arrangement direction of the lines. That is, the multiplexer 5
9, the main image signal S1 is thinned at a predetermined thinning rate for both the horizontal and vertical components.

The sub-image signal S2 is also thinned out at a predetermined thinning rate by the horizontal filter / thinning unit 52, line buffer 54, and vertical filter / thinning unit 56. The thinning rates of both the image signals S1 and S2 are set so that both can be displayed in parallel on a single screen as the output image signal S3. For example, if the thinning rate of the main image signal S1 is 2/3, the sub image signal S2
Is set to 1/3 or a smaller value.

One of the image signals S1 and S2 after thinning output from both the vertical filter / thinning units 55 and 56 is appropriately selected by the multiplexer 59,
The data is written to the dual port RAM 71. at the same time,
The thinned image signals S1 and S2 already written
Are read out as output image signals S3 in an order in which they can be displayed in parallel on the same screen. Dual port R
The operation of the AM 71 and the multiplexer 59 is controlled by the control unit 6
1 is controlled.

[0008] The output image signal S
3 in addition to the vertical synchronizing signal Vsync3, the horizontal synchronizing signal Hsync1 and the dot clock DCLK1 accompanying the main image signal S1, respectively.
The horizontal synchronization signal Hsync3 and the dot clock DCLK3 are also output at the same time.

By operating as described above, the image processing device 171 can display the main image signal S1 and the sub image signal S2 on a single screen in a double window format.

[0010]

As described above, in the conventional image processing apparatus 171, the dual port R
AM71 is used. The dual port RAM 71 has a pin for a write signal and a pin for a read signal independently, and each is independently connected to the image conversion unit 151. Therefore, when the image conversion unit 151 is incorporated into a single semiconductor chip, the number of pins of the image conversion unit 151 becomes large, and there is a problem that the size of the device becomes large.

Further, the dual-port RAM 71 is expensive, which causes a problem that the manufacturing cost of the entire image processing device 171 increases.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems in the conventional apparatus, and provides an image processing apparatus which realizes double window display without using an expensive dual port memory having a large number of pins. The purpose is to do.

[0013]

According to a first aspect of the present invention, a main image signal and a sub image signal input from the outside are thinned out at respective thinning rates, so that the main image signal after thinning and the thinned main image signal are thinned out. A thinning unit that outputs a thinned sub image signal, a selecting unit that selects and outputs one of the thinned main and sub image signals that are output from the thinning unit, and that is selectively output from the selecting unit. Said
After thinning, the main and sub image signals can be written sequentially.
The main and sub image signals after thinning are read out from the storage medium as output image signals in an order that the main and sub image signals after thinning can be projected in parallel on the same screen. A first and a second buffer respectively inserted in a path of the thinned main and sub image signals from the thinning unit to the selection unit, and the storage unit; A third buffer interposed in a path of the output image signal from the medium to the outside; and a control unit that controls the selection unit and the storage medium, wherein the control unit includes the output image signal. Is read out from the storage medium at a speed twice or more as high as the output speed of the output image signal to the outside, and the storage of the thinned main and sub image signals is performed. Writing to the body, in the read is not idle time performed, as carried out in two or more times the speed of the delivery speed, and executes the control, the control unit,
One scan line of the output image signal from the third buffer
After half of the output is completed, one new scan line is
3 from the storage medium as input to the
The timing of reading of the output image signal, characterized by the this <br/> be further controlled.

[0014]

The devices according to the second and third aspects of the present invention are input from outside.
Each of the input main image signal and sub image signal is
By thinning at each thinning rate,
Output post-main image signal and sub-image signal after thinning
A thinning unit, and the post-thinning menu output from the thinning unit.
Select to output one of the in and sub image signals
Section and the thinned-out menu selectively output from the selection section.
And sub-image signals are sequentially written into the memory.
And the main and sub image signals after the thinning are provided.
In order that they can be projected in parallel on the same screen,
After decimating the main and sub image signals from the storage medium
Can be read out as an output image signal and sent out
In the image processing apparatus, from the thinning unit to the selecting unit
Paths of main and sub-image signals after the thinning
First and second buffers respectively interposed,
Of the output image signal from the storage medium to the outside.
A third buffer interposed in the path, the selection unit and the
A control unit for controlling the storage medium, further comprising:
The control unit reads the output image signal from the storage medium.
However, the speed of sending the output image signal to the outside is twice or more.
The main and sub image signals after the thinning
Is written to the storage medium but the read is not performed
In the idle time, it is performed at a speed of twice or more of the sending speed.
As described above, performing the control , the control unit, every time an overtaking occurs between the main and sub vertical synchronizing signals input accompanying the main and sub image signals input from the outside, respectively, By skipping a field older than the newest field among fields that have been completely written to the storage medium, one of which corresponds to the overtaken side in the main and sub image signals after the thinning, For each field of the main image and the sub-image signal after the thinning, the control is further executed so that the newest field which has been completely written to the storage medium is always read.

The devices according to the fourth and fifth aspects of the present invention are provided from outside.
Each of the input main image signal and sub image signal is
By thinning at each thinning rate,
Output post-main image signal and sub-image signal after thinning
A thinning unit, and the post-thinning menu output from the thinning unit.
Select to output one of the in and sub image signals
Section and the thinned-out menu selectively output from the selection section.
And sub-image signals are sequentially written into the memory.
And the main and sub image signals after the thinning are provided.
In order that they can be projected in parallel on the same screen,
After decimating the main and sub image signals from the storage medium
Can be read out as an output image signal and sent out
In the image processing apparatus, from the thinning unit to the selecting unit
Paths of main and sub-image signals after the thinning
First and second buffers respectively interposed,
Of the output image signal from the storage medium to the outside.
A third buffer interposed in the path, the selection unit and the
A control unit for controlling the storage medium, further comprising:
The control unit reads the output image signal from the storage medium.
However, the speed of sending the output image signal to the outside is twice or more.
The main and sub image signals after the thinning
Is written to the storage medium but the read is not performed
In the idle time, it is performed at a speed of twice or more of the sending speed.
As described above, performing the control , the control unit, every time an overtaking occurs between the main and sub vertical synchronizing signals input accompanying the main and sub image signals respectively input from the outside, One write corresponding to the overtaken side of the main and sub image signals after the thinning is paused for one field, and then the field immediately before the pause is repeated until a new field is written and readable. Further performing the control such that the most recent field that has been completely written to the storage medium is always read for each field of the thinned main and sub image signals by reading out the data. It is characterized by.

According to a sixth aspect of the present invention, there is provided an apparatus according to any of the second to fifth aspects.
In the image processing apparatus according to any one of the aspects of the invention, the control unit includes:
The main and sub image signals input from the outside
Main and sub vertical
Each time an overtaking occurs during the period signal,
One of the image and sub-image signals
Pauses one field for one field, and then
Pause until the field is written and ready to be read.
By repeatedly reading the previous field,
Subsequent main and sub image signal fields
The most recently completed writing to the storage medium.
Set the controls so that the field is always read.
It is characterized in that it is executed .

According to a seventh aspect of the present invention, there is provided the apparatus according to any one of the first to sixth aspects.
The image processing apparatus according to any one of the preceding claims , wherein the storage medium
Is connected to the control unit and the first to third buffers.
A single-port RAM capable of reading and writing at a speed of twice or more the transmission speed, and having a storage capacity of at least two fields of the output image signal. And

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

<1. First Embodiment> FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to a first embodiment. This image processing device 1
21 synthesizes a so-called double-window image, in which the thinned-out images are displayed in parallel on a single screen, from the two input image signals, the main and sub-image signals S1 and S2, as an output image signal S3. Output.

<1-1. Outline of Configuration and Operation> As shown in FIG. 1, the image processing apparatus 121 includes an image conversion unit 101 and a RAM 21 coupled to the image conversion unit 101 and functioning as a storage medium. Then, the image conversion unit 101 includes a horizontal filter / thinning units 1 and 2, line buffers 3 and 4, a vertical filter
It includes thinning units 5 and 6, line buffers (first and second buffers) 7 and 8, multiplexers 9 and 10, a line buffer (third buffer) 11, and a control unit 12. A single-port RAM is used for the RAM 21. Preferably, EDO (Extend;
ed Data Out) type DRAM is used.

The vertical filter / decimation unit 5 includes a filter unit 5
a and a thinning-out section 5b. Similarly, the vertical filter / thinning section 6 includes a filter section 6a and a thinning-out section 6b.
b. The horizontal filter / thinning unit 1
2, the line buffers 3 and 4 and the vertical filter / decimation units 5 and 6 as a whole constitute a thinning unit that performs both the horizontal and vertical decimation for both image signals S1 and S2. Note that all the device parts of the image conversion unit 101 are desirably built in a single semiconductor chip.

The image conversion unit 101 has a main image signal S
1 and the sub-image signal S2, and a vertical synchronization signal V of the main image accompanying the main image signal S1.
sync1, horizontal synchronization signal Hsync1, dot clock DCLK1,
Further, the vertical synchronizing signal Vsync2, the horizontal synchronizing signal Hsync2, and the dot clock DCLK2 of the sub-image accompanying the sub-image signal S2 are simultaneously inputted. Dot clocks DCLK1,
DCLK2 is a signal used for sampling the image signal, and is synchronized with the input image signals S1 and S2, respectively.

The main image signal S1 is input to the horizontal filter / thinning unit 1, where a pixel signal (signal for each pixel) as a unit constituting the main image signal S1 is interposed along a line (scanning line). Drawn. The main image signal that has been subjected to horizontal thinning by the horizontal filter / thinning unit 1 is
The data is sent to the vertical filter / thinning unit 5 and the line buffer 3. The vertical filter / thinning section 5 thins out lines (scanning lines), that is, thins out the vertical direction, based on the main image signal directly input from the horizontal filter / thinning section 1 and the main image signal passed through the line buffer 3. Is performed.

Similarly, the horizontal image and the vertical image are thinned out by the horizontal filter / thinning unit 2, the line buffer 4, and the vertical filter / thinning unit 6 for the sub-image signal S2.

The thinned main image signal A1 output from the vertical filter / thinning unit 5 is temporarily stored in a line buffer 7 having a storage capacity for one line, and then input to a multiplexer 9 as an image signal B1. You. Similarly, the thinned-out sub-image signal A2 output from the vertical filter / thinning unit 6 is temporarily stored in the line buffer 8, and then input to the multiplexer 10.

The line buffer 8 has two line buffers 8a and 8b each having a storage capacity for one line.
The image signal sent from the vertical filter / thinning unit 6 is distributed to one of the line buffers 8a and 8b on a line-by-line basis. The multiplexer 10 selects one of the image signals stored in one of the line buffers 8a and 8b, and sends it to the multiplexer 9 as an image signal B2.

The operations of the multiplexer 9 and the RAM 21 are controlled by the control unit 12. The multiplexer 9 receives the input main and sub image signals B
One of B1 and B2 is appropriately selected based on a control signal from the control unit 12 and transmitted to the RAM 21. Further, the RAM 21 stores the image signals B1 and B2 sent from the multiplexer 9 based on a control signal from the control unit 12. That is, the image signals B1 and B2 are appropriately selected by the multiplexer 9 and written into the RAM 21.

The main and sub image signals B 1 and B 2 written in the RAM 21 are read out as appropriate as an image signal C based on a control signal from the control unit 12 and input to the line buffer 11. The line buffer 11 temporarily stores the input image signal C and sequentially outputs the input image signal C to an external device as an output image signal S3.

The image conversion unit 101 outputs a vertical synchronizing signal Vsync3, a horizontal synchronizing signal Hsync3,
The dot clock DCLK3 is also output at the same time. These vertical synchronizing signal Vsync3, horizontal synchronizing signal Hsync3, and dot clock DCLK3 are the vertical synchronizing signal Vsync1, horizontal synchronizing signal Hsync1, and dot clock D accompanying the main image signal S1.
It is output in synchronization with CLK1.

<1-2. Thinning-Out Operation> FIG. 2 is an explanatory diagram showing an example of the operation of the image processing apparatus 121. In the operation example of FIG. 2, the main image signal S1 is thinned out by 2/3, and the sub image signal S2 is thinned out by 1/3, and an output image signal S3 for displaying them in parallel on a screen is synthesized. .
Hereinafter, the operation of each unit of the image processing apparatus 121 will be described based on the operation example of FIG.

FIG. 3 is a timing chart for explaining the operation of the vertical filter / thinning section 6 on behalf of the vertical filter / thinning sections 5 and 6. Vertical filter / thinning section 6
The filter unit 6a includes an image signal P1 from the horizontal filter / thinning unit 2, an image signal P2 delayed by one line by passing through the line buffer 4, and
An image signal P3 delayed by two lines is input simultaneously.
That is, as shown in FIG. 3, the image signal P2 is delayed by one period of the horizontal synchronization signal Hsync2 from the image signal P1, and the image signal P3 is delayed by two periods.

The filter section 6a calculates an average value of these three image signals P1, P2, P3 and outputs the average value as an image signal P4. FIG. 3 shows an example in which the arithmetic mean is calculated. However, in general, the weighted average may be added to each of them (calculation of a weighted average). The thinning unit 6b performs a thinning operation on the image signal P4. In order to obtain the output image signal S3 shown in FIG. 2, as shown in FIG. 3, 1/3 thinning is performed and the result is output as an image signal A2. That is,
Of the three lines of the image signal P4, only one line is extracted and the others are discarded.

Since the original three sub-image signals S2 are generally mixed in the image signal P4, all the sub-image signals S2 are included in the thinned image signal A2.
Are reflected at a certain rate. The image signal A2 thus obtained is sent to the line buffer 8.

The vertical filter / thinning section 5 operates similarly to the vertical filter / thinning section 6. However, the thinning rates are generally different. In order to obtain the output image signal S3 shown in FIG. 2, 2/3 thinning is performed in the vertical filter / thinning unit 5. The main image signal A1 thus obtained
Is sent to the line buffer 7.

In general, the vertical filter / thinning units 5, 6
Need not include the filter units 5a and 6a. At this time, the operations of the vertical filter / thinning units 5 and 6 are equivalent to the case where the filter units 5a and 6a calculate a weighted average in which all weights of components other than one component are set to zero.

Similarly, the horizontal filter / thinning units 1 and 2
Generally, a filter unit and a thinning unit are provided, and similar operations are performed on pixels on a line. Since the same operation is performed on the pixels on the line, a line buffer is not necessary, and instead, a plurality of pixels (3 in the operation example of FIG. 2) is used.
(A pixel).

<1-3. RAM write and read operations>
FIG. 4 illustrates the operation of each unit from the line buffers 7, 8 to the line buffer 11, including the write and read (ie, access) operations of the RAM 21, for obtaining the output image signal S3 of the form illustrated in FIG. It is a timing chart for performing.

As shown in FIG. 4, the main image signal A1 obtained by the 2/3 thinning-out is transmitted by the horizontal synchronizing signal H.
It stops for one cycle every three cycles of sync1. That is, for each cycle of the horizontal synchronizing signal Hsync1, the image signals x1 and x2 for one line are used as the main image signal A1.
Are sequentially transmitted, and the subsequent one cycle is paused. further,
After the image signals x3 and x4 for one line are sequentially transmitted, the operation is paused again for one cycle. Hereinafter, the same operation is repeated.

The transmission of the sub-image signal A2 obtained by the other 1/3 decimation is stopped for two periods for every three periods of the horizontal synchronization signal Hsync2. That is, for each cycle of the horizontal synchronizing signal Hsync2, the image signal y1 for one line is transmitted as the sub-image signal A2, and then the operation is paused for two cycles. Thereafter, after the image signal y2 for one line is transmitted, the operation is paused again for two cycles. Hereinafter, the same operation is repeated.

Since the horizontal thinning has already been performed, the number of pixel signals of the image signals x1, x2,... Is reduced to 2/3 of the number of pixel signals of one line of the main image signal S1. I have. Similarly, the number of pixel signals of the image signals y1, y2,... Is one of the number of pixels of one line of the sub-image signal S2.
/ 3.

The main image signal A1 is supplied to the line buffer 7
And then read out as an image signal B1 in a timely manner in accordance with the timing of writing to the RAM 21. Similarly, the sub-image signal A2 is temporarily stored in the line buffer 8, and is thereafter read out as the image signal B2 in a timely manner in accordance with the timing of writing to the RAM 21.

The image signal C read from the RAM 21 is
After being temporarily stored in the line buffer 11, it is read out as appropriate as the output image signal S3. The output image signal S3 illustrated in FIG. 4 corresponds to an image signal on a line near the line L1 in FIG. 2, that is, an image signal in a region where both the main image signal S1 and the sub image signal S2 are projected on the screen. I do.

In the output image signal S3 near the line L1, the horizontal synchronizing signal Hsync3 (= horizontal synchronizing signal Hs)
Synchronously with (ync1), the main image signal A1 thinned out by 2/3 and the sub image signal A2 thinned out by 1/3 are arranged on one line. That is, the image signal x1 'for one line of the main image signal A1 thinned out by 2/3,
x2 ′,..., and the sub-image signal A thinned out by 1/3
2 are (x1 ', y1'), (x2 ', y2'),...
, And are arranged on one line.

The image signals x1 ', x2',...
Represent the signal one frame before the image signal x1, x2,..., And represent the signal one frame before the image signal y1, y2,. ing.

Similarly to the output image signal S3, the image signal C
, (X1 ′, y1 ′), (x2 ′, y2 ′),.
Is read out from the RAM 21 in the following format. However, it is read at a speed that is at least twice as fast as the output speed of the output image signal S3. Output image signal S3 from line buffer 11
The reading of the image signal C from the RAM 21 is started after the output of the image data is half completed, so that the overtaking in the line buffer 11 having a storage capacity of one line can be prevented.

Then, during the remaining period t1 excluding the period t2 during which the image signal C is read, the image signals x1, x2,... RAM 21 for signals y1, y2,...
Is written. The writing of the image signals B1 and B2 is also performed at the speed 2 at which the image signals S1 and S2 are input.
It is performed at twice the speed. Therefore, the image signals B1, B
It is possible to set the time t1 required for writing 2 and the time t2 required for reading the image signal C without overlapping.

That is, since the number of signals for one line of the image signals B1 and B2 is one line of the output image signal S3, the writing is performed in the remaining time excluding the time when the output image signal S3 is output. Is possible. This means that R
A single-port RAM can be used as the AM 21. Note that there is a difference in the transmission speed between the main image signal A1 and the image signal B1, the sub-image signal A2 and the image signal B2, and the transmission speed between the image signal C and the output image signal S3. Are provided as line buffers 7, 8, and 11.

In the RAM 21, an EDO type DRAM is used.
But are particularly suitable. An EDO type DRAM can operate in a so-called hyper page mode. Normal DRAM has a high-speed page mode,
The hyper page mode of the EDO type is even faster.

In a standard DRAM rated at 70 nsec, the cycle (period) in the high-speed page mode is 45 nsec, whereas the cycle in the hyper page mode is 30 nsec. The standard image signal rate is 14.3MHz (= 7
0 nsec), the image signal can be accessed twice in the hyper page mode of EDO.

In general, it is sufficient that the read / write (access) speed of the RAM 21 is at least twice the speed of the output image signal S3. The storage capacity of the RAM 21 is equal to or larger than one frame (= 2 fields) of the output image signal S3.
That is, in the example of FIG. 2, it is only necessary that the signal has a magnitude equal to or larger than the signal amount corresponding to the area on the screen where the output image signal S3 is displayed.

Note that FIG. 4 exemplifies the image signal C and the output image signal S3 in the vicinity of the line L1 in FIG. On the other hand, an output image signal S3 on a line near the line L2 in FIG. 2 is represented by a timing chart in FIG. That is, the main image signal S1
In the vicinity of the line L2 where only the sub-image signal S2 is not displayed on the screen and the sub-image signal S2 is not displayed, the horizontal synchronization signal Hsy
In synchronization with nc3, only the image signals x1 ', x2',... are transmitted as output image signals S3, and the image signals y1 ',
are not transmitted.

The output image signal S3 on a line near the line L3 in FIG. 2, that is, the output image signal S3 in an area where neither the main image signal S1 nor the sub image signal S2 appears on the screen is shown in FIG. 6 is shown in the timing chart. That is, in this area, the output image signal S3 is not transmitted.

<2. Second Embodiment> As described above, in the image processing apparatus 121, the capacity of the RAM 21 can be set to one frame (= 2 fields) of the output image signal S3. By the way, the two vertical synchronizing signals V
Sync1 and Vsync2 are not always synchronized, and their periods are usually slightly different from each other. For this reason,
When the capacity of the RAM 21 is set to the minimum value of one frame, it is desirable to perform the following field conversion. Field conversion is performed by the RAM by the control unit 12.
It is easily realized by controlling the writing / reading to / from the memory 21.

FIG. 7 is a timing chart showing an example of field conversion in the image processing apparatus 121 provided with the RAM 21 having a storage capacity for two fields.
As shown in FIG. 7, in synchronization with the vertical synchronization signal Vsync1,
As the image signal B1, the image signal F1 of the first field and the image signal F2 of the second field are alternately stored in the RAM 21.
Written to Similarly, in synchronization with the vertical synchronizing signal Vsync2, the image signal f1 of the first field and the image signal f2 of the second field are alternately set as RA as the image signal B2.
M21 is written.

As shown in FIG. 4, the image signals F1 and F2 are thinned image signals x1 and x in one field.
, And similarly, image signals f1, f
2 is a thinned image signal y1, y in one field
It is a collection of 2, ... Therefore, the image signal F
1 and F2 and one of the image signals f1 and f2, the number of pixels is equal to that of the original input image signals S1 and S2.
2 less than one field. This is apparent from FIG. 2 showing the relationship between the image signals S1, S2, and S3.

As shown in FIG. 7, while one of the image signals F1 and F2 is being written to the RAM 21, the other of which has already been written is read. Similarly, while one of the image signals f1 and f2 is being written, the other of which has already been written is read. By doing so, the image signal F1 and the image signal f1 are read out in parallel, and the image signal F2 and the image signal f2 are read out in parallel.

However, even if the vertical synchronizing signal Vsync2 overtakes the vertical synchronizing signal Vsync1 as illustrated at time t3 in FIG. 7, the pair of (F1, f1) and (F2, f
The memory capacity of the RAM 21 is insufficient to maintain the pattern in which the pair 2) is alternately read. Therefore, after the time t3, in the image signals f1 and f2,
Reading is performed by selecting one of which has been written in the closest past. In other words, the vertical synchronization signal Vsync
The image signal f1 or f2 shifted by one cycle or more is discarded.

As a result, the reading of the image signal f1 is skipped for one field to read the image signal f2. Then, the image signal f
Reading is performed alternately between 1 and f2. Then, when the overtaking occurs again between the vertical synchronization signals Vsync1 and Vsync2, the reading for one field is similarly performed.
Hereinafter, the same operation is repeated.

Therefore, the vertical synchronization signals Vsync1, Vsyn
Each time an overtaking occurs between c2, a pattern in which a set of (F1, f1) and a set of (F2, f2) are alternately read, a set of (F1, f2) and a set of (F2, f1) Are alternately read out. That is, these two types of patterns are alternately repeated at a constant cycle.

As described above, the vertical synchronizing signals Vsync1, Vs
Each time an overtaking occurs between the signals ync2 and ync2, a field conversion is performed on the image signal on the overtaking side, so that R
The capacity of the AM 21 can be suppressed to two fields of the output image signal S3.

After time t3 in FIG. 7, that is, during a period in which the set of (F1, f2) and the set of (F2, f1) are alternately read, the output image signal S3 has
As shown in FIG. 8, the uppermost line (first scanning line) of the image signal f1 is discarded, and the uppermost line (second scanning line) of the image signal f2 is discarded.
RAM 21 so that scanning is performed from the second scanning line).
It is desirable that the image signals f1 and f2 from are read out. Then, it is desirable that the reading is performed so that the last line of the image signal f1 (the n-th scanning line in FIG. 8) is scanned in an overlapping manner.

The reading of the image signals f1 and f2 from the RAM 21 is performed in this manner, whereby the image signals f1 and f2 are read.
The arrangement order of the lines between 1 and f2 is kept the same as the order at the time of input to the RAM 21 except for the top line and the last line. Therefore, the output image (output image signal S3
Therefore, there is obtained an advantage that the image quality of the image projected on the screen is always kept good despite the field conversion.

<3. Third Embodiment> FIG. 9 is a timing chart showing still another example of the field conversion in the image processing apparatus 121 provided with the RAM 21 having a storage capacity for two fields. In this operation example, at a certain time t4, the vertical synchronization signal Vsync2 is changed to the vertical synchronization signal Vs.
When the signal ync1 is overtaken, the image signal f2 to be written as the image signal B2 is not written in the RAM 21. After that, the same image signal f1 is repeatedly read as the image signal C over two periods of the vertical synchronization signal Vsync2. Further, the overtaking vertical synchronizing signal Vsy
The writing of the image signal B2 is restarted from the second cycle of nc2.

Each time an overtaking occurs between the vertical synchronizing signals Vsync1 and Vsync2, the image signal on the overtaking side is subjected to the field conversion in the manner shown in FIG. 9 as in the case of the field conversion shown in FIG. Can be suppressed to two fields of the output image signal S3. Further, the image signals f1 and f1 in the manner shown in FIG.
The fact that the quality of the output image can always be kept good by reading f2 from the RAM 21 is the same as the field conversion in FIG.

Further, after an overtaking occurs between the vertical synchronization signals Vsync1 and Vsync2, the same image signal f1 is applied to the image signal C for two periods of the vertical synchronization signal Vsync2.
And the same sub-image is displayed in both the even and odd fields, so that the sub-image shifts by one line immediately after passing, as compared to the field conversion in FIG. There is an advantage that it is less noticeable. That is, an output image with higher image quality can be obtained as compared with the field conversion of FIG.

[0066]

According to the first aspect of the present invention, the first to the third
The provision of the buffer makes it possible to read and write to an external storage medium at a speed that is twice or more the speed at which the output image signal is sent to the outside. Further, this allows writing and reading to and from the storage medium at different times.

Since writing to and reading from the storage medium are performed at mutually different times, an inexpensive device such as a single-port RAM, in which pins for write data and pins for read data are shared, is used as the storage medium. It is possible to use. Further, since the number of pins provided in the image processing device for coupling with the storage medium can be reduced, the size of the device can be reduced. This is particularly useful when the image processing device is configured as a one-chip semiconductor device.

Then , after half of the output of one scan line of the output image signal from the third buffer is completed, a new scan line is input to the third buffer, so that the storage capacity of the third buffer is reduced. One scanning line is sufficient.

In the device according to the second and third aspects of the invention, every time an overtaking occurs between the main and sub vertical synchronizing signals,
Fields older than the newest field among the fields of the skipped image signal whose overwriting has been completed to be written to the storage medium are skipped, whereby each of the main and sub-image signals after the thinning is read. For a field, the most recent field that has been written to the storage medium is always read. As described above, the field conversion is performed each time passing occurs, so that the storage capacity of the storage medium is sufficient for two fields of the output image signal.

In the device according to the fourth and fifth aspects of the present invention, every time an overtaking occurs between the main and sub vertical synchronizing signals,
The writing of the post-thinning-out image signal on the overtaking side whose writing to the storage medium is completed is suspended for one field, and then the field immediately before the pause is repeated until a new field is written and readable. Read out. Thus, for each field of the main image and the sub-image signal after thinning, the newest field which has been completely written to the storage medium is always read. As described above, the field conversion is performed each time passing occurs, so that the storage capacity of the storage medium is sufficient for two fields of the output image signal.

Further, the same field is repeatedly read out after passing, and the same image is displayed in both fields. Therefore, when the present invention is carried out in combination with the sixth invention, the image of one line is Movement can be reduced visually.

In the device according to the sixth aspect of the present invention, the frame of the component of the output image signal, which is a thinned-out image signal corresponding to the overtaken side, in the period in which the field in the frame is inverted. Are skipped by the first scanning line. Thus, the order of the scanning lines is always kept normal except for the upper and lower ends on the screen between the fields in the frame. Therefore, a decrease in image quality due to the field conversion can be suppressed.

In the apparatus according to the seventh aspect of the present invention, since the storage medium for storing the main and sub image signals after thinning is provided, it is not necessary to separately prepare and connect the storage medium when using the image processing apparatus. That is, the labor involved in using the device is omitted. Further, since a single-port RAM is selected as a storage medium, the device can be made small and can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to a first embodiment.

FIG. 2 is an explanatory diagram illustrating an operation example of the device according to the first embodiment;

FIG. 3 is a timing chart illustrating the operation of a vertical filter / thinning section.

FIG. 4 is a timing chart showing an operation related to access to a RAM.

FIG. 5 is a timing chart of an output image signal.

FIG. 6 is a timing chart of an output image signal.

FIG. 7 is a timing chart showing the operation of the device according to the second embodiment.

FIG. 8 is an explanatory diagram showing the operation of the device according to the second embodiment.

FIG. 9 is a timing chart showing the operation of the device of the third embodiment.

FIG. 10 is a block diagram of a conventional device.

[Explanation of symbols]

 Reference Signs List 7 line buffer (first buffer) 8 line buffer (second buffer) 9 multiplexer (selection unit) 11 line buffer (third buffer) 12 control unit 21 RAM (storage medium, single port RAM) 101 image conversion unit (image processing) 121) Image processing device S1 Main image signal S2 Sub image signal A1 Main image signal (main image signal after thinning) B1 Image signal (main image signal after thinning) A2 Sub image signal (sub image signal after thinning) B2 Image signal (sub-image signal after thinning) C Image signal (output image signal) S3 Output image signal. Vsync1, Vsync2 Vertical sync signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 5/00-5/40 H04N 5/45

Claims (7)

(57) [Claims] A thinning section for thinning out each of a main image signal and a sub image signal input from the outside with a thinning rate, thereby outputting a main image signal after thinning and a sub image signal after thinning; A selection unit for selecting and outputting one of the main and sub-image signals after the thinning output from the thinning unit ;
The main and sub image signals after the thinning are output in sequence.
A storage medium that can be written to the next, and the main and sub image signals after thinning out from the storage medium in the order that the main and sub image signals after thinning can be projected in parallel on the same screen. An image processing apparatus that can read out an output image signal and transmit the readout image signal to an external device, wherein the first and second image signals are interposed in the paths of the main and sub image signals after the thinning from the thinning unit to the selecting unit. A buffer, a third buffer inserted in a path of the output image signal from the storage medium to the outside, a control unit that controls the selection unit and the storage medium,
The control unit, wherein the reading of the output image signal from the storage medium is performed at a speed of twice or more a transmission speed of the output image signal to the outside, and the thinned main image and the sub image are read out. writing to the signal of the storage medium, in the read is not idle time performed, as carried out in two or more times the speed of the delivery speed, and executes the control, the control unit, the third The output image signal from the buffer
After one half of the output of one scan line has been completed,
So that the scanning line is input to the third buffer,
The timing of reading the output image signal from the storage medium is
And an image processing apparatus for controlling the image processing. 2. A main image signal and an externally input main image signal.
And each of the sub-image signals
By thinning, the main image signal after thinning and the thinning
A thinning-out unit that outputs the post-sub-image signal and the thinning-out unit
Of the main and sub image signals after the thinning output
And a selection unit for selecting and outputting
The main and sub image signals after the thinning are output in sequence.
A next-writable storage medium, and
In and sub image signals are projected in parallel on the same screen
Main and sub-pictures after their decimation in the order possible
When an image signal is read out from the storage medium as an output image signal,
In the image processing apparatus which can be sent to the outside, the post-decimation main screen from the decimation section to the selection section is provided.
In the path of the image signal and the sub image signal, respectively.
First and second buffers and the output image signal from the storage medium to the outside
A third buffer interposed in the path of , a control unit for controlling the selection unit and the storage medium,
The control unit may further include: outputting the output image signal from the storage medium.
The reading is twice as fast as the sending speed of the output image signal to the outside.
The main and sub images after the thinning are performed at the above speed.
A signal is written to the storage medium, and the read is performed.
Within a free time, at a speed that is at least twice the sending speed
The control section executes the control so that the main and
Main and sub image signals
And each time an overtaking occurs between the sub-vertical sync signals,
Overtaken in main and sub image signals after decimating
Has been written to the storage medium.
Older than the newest field
By skipping over new fields,
For each field of the in and sub image signals,
The newest field that has been written to the storage medium
The above control is further executed so that the code is always read.
An image processing apparatus comprising: 3. The image processing apparatus according to claim 1 , wherein the control unit is configured to control the main and the external input.
Main and sub image signals
And each time an overtaking occurs between the sub-vertical sync signals,
Overtaken in main and sub image signals after decimating
Has been written to the storage medium.
Older than the newest field
By skipping over new fields,
For each field of the in and sub image signals,
The newest field that has been written to the storage medium
The above control is further executed so that the code is always read.
An image processing apparatus comprising: 4. A main image signal and an externally input main image signal.
And each of the sub-image signals
By thinning, the main image signal after thinning and the thinning
A thinning-out unit that outputs the post-sub-image signal and the thinning-out unit
Of the main and sub image signals after the thinning output
And a selection unit for selecting and outputting
The main and sub image signals after the thinning are output in sequence.
A next-writable storage medium, and
In and sub image signals are projected in parallel on the same screen
Main and sub-pictures after their decimation in the order possible
When an image signal is read out from the storage medium as an output image signal,
In the image processing apparatus which can be sent to the outside, the post-decimation main screen from the decimation section to the selection section is provided.
In the path of the image signal and the sub image signal, respectively.
First and second buffers and the output image signal from the storage medium to the outside
A third buffer interposed in the path of , a control unit for controlling the selection unit and the storage medium,
The control unit may further include: outputting the output image signal from the storage medium.
The reading is twice as fast as the sending speed of the output image signal to the outside.
The main and sub images after the thinning are performed at the above speed.
A signal is written to the storage medium, and the read is performed.
Within a free time, at a speed that is at least twice the sending speed
As described above, performing the control , the control unit, every time an overtaking occurs between the main and sub vertical synchronization signals that are respectively input together with the main and sub image signals input from the outside,
One write corresponding to the overtaken side of the main and sub image signals after the thinning is paused for one field, and then the field immediately before the pause is repeated until a new field is written and readable. By reading, for each field of the main image and the sub-image signal after the thinning, the newest field which has been completely written to the storage medium is always read.
An image processing apparatus, wherein the control is further performed. 5. The image processing apparatus according to claim 1 , wherein the control unit is configured to control the main and the external input.
Main and sub image signals
And each time an overtaking occurs between the sub-vertical sync signals ,
Overtaken in main and sub image signals after decimating
And the other side of writing is paused for one field.
After that, a new field is written and readable.
Until the field immediately before pausing is read repeatedly.
Therefore, each of the main and sub image signals after the thinning is
Field has been completely written to the storage medium.
So that the most recent field is always read
An image processing apparatus, wherein the control is further performed . 6. The image processing apparatus according to claim 2 , wherein the control unit is configured to generate a component constituting the output image signal.
In the main and sub image signals after the
On the other side of the frame
In the frame during the period when the field is inverted
Field is skipped by the first scan line.
On the screen between the fields in the frame
Except for the top and bottom edges of the frame, the order of the scan lines is always
The output image from the storage medium so that
An image processing apparatus further controlling reading of a signal . 7. The method according to claim 1, wherein:
In the image processing apparatus described above, the storage medium includes the control unit and the first to third storage units.
A single-port RAM coupled to a buffer, wherein the single-port RAM is at least twice the sending speed
Reading and writing at a speed of
An image processing apparatus having a storage capacity of at least two fields of an image signal .