JP3350013B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
In particular, the repetition frequency of the output signal is determined according to the phase comparison result between an input signal having a reference frequency (hereinafter referred to as a reference input signal) and an output signal having a dependent frequency (dependent frequency signal) to be dependent on the reference input signal. The present invention relates to a PLL circuit that changes the value.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 15, a PLL circuit includes a phase comparator 1 for comparing a phase with a reference input signal, and a voltage control for changing an oscillation frequency according to a result of the phase comparison. Oscillator (Voltage Controlled Oscilator;
The output signal 300 of the VCO 3 is used as a phase comparison target and is fed back to the phase comparator 1 side. In this case, the signal indicating the phase comparison result of the phase comparator 1 is a low-pass filter (Low Pass Filter).
The signal is converted into a smoothed voltage level by the LPF 2, and the oscillation frequency of the VCO 3 is changed and controlled by this voltage level.

The output signal 3 output from the VCO 3
00 becomes a dependent frequency signal 400 by being frequency-divided by N in the frequency divider 4 and input to the phase comparator 1. On the other hand, the reference input signal 100 is also frequency-divided by N in the frequency divider 5 to become the reference input signal 500, which is input to the phase comparator 1. As described above, in practice, the phases of the frequency-divided signals of the reference input signal 500 and the dependent frequency signal 400 are compared, and the oscillation frequency is controlled according to the phase comparison result.

In a PLL circuit, even if the phase relationship between a reference input signal and a dependent frequency signal is constant under a constant operating environment, a change in the operating environment due to a power supply fluctuation and a change in environmental temperature causes The dependent frequency signal changes. As a result, the phase difference between the reference input signal and the dependent frequency signal fluctuates. This means that if data is to be transferred in synchronization with the reference frequency signal in synchronization with the dependent frequency signal, the higher the speed of the data, the more rigorous the transfer becomes, which causes a data error. Further, when the alarm output is used for data processing, accuracy is required depending on the request, and there is a possibility that the alarm output may be affected by noise due to disturbance or the like.

[0005]

SUMMARY OF THE INVENTION The above-mentioned conventional PLL
In the circuit, when the dependent frequency signal changes due to changes in the operating environment due to power supply fluctuations and environmental temperature changes, resulting in a phase difference fluctuation between the reference input signal and the dependent frequency signal, data synchronized with the reference input signal is controlled. If data transfer is attempted in synchronization with a frequency signal, there is a disadvantage that the transfer becomes more severe as the data becomes faster, causing a data error.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art. The object of the present invention is to reduce the possibility of data errors and to be affected by noise due to disturbance or the like even with high-speed data. It is to provide a low PLL circuit.

[0007]

A PLL circuit according to the present invention detects a phase difference between an input signal and an output signal and detects a phase difference signal corresponding to the detected phase difference. Oscillating means for transmitting an output signal having a repetition frequency, and when the state of the phase advance or phase lag of the output signal with respect to the input signal is continuous, the voltage level of the phase difference signal is changed and controlled according to the number of continuations. and control means for and Nde including, said control means
Is a pulse having a pulse width corresponding to the number of consecutive times.
The pulse width modulator to generate and the generated pulse width
And an integrating circuit for integrating the tuning pulse.
The integration output level is added to the phase difference signal.
And features.

[0008] Further, the pulse width modulator includes
The output signal is phase-advanced and phase-lagged relative to the signal
Counts up when one of the states continues
One of the
Perform the other operation when the other state continues.
Includes an up-down counter and the count value of this counter
Generating a pulse having a pulse width corresponding to
Sign.

A temperature detecting means for detecting a temperature change; and an adding circuit for controlling the addition characteristic to be kept constant in accordance with the detected temperature change and adding the integrated output level to the phase difference signal. May be further included. The temperature detecting means is a thermistor whose resistance value changes according to a predetermined temperature characteristic, and the resistance value change of the thermistor cancels out the resistance value change of the resistor constituting the adding circuit.

Further, when the phase difference of the output signal with respect to the input signal becomes equal to or more than a predetermined value, the apparatus may further include an alarm unit for sending an alarm indicating the fact to the outside. The alarm means sends the alarm to the outside when the state where the phase difference is equal to or more than a predetermined value continues for a predetermined time or more.

Furthermore, an oscillator for generating an oscillation signal having a repetition frequency substantially the same as the repetition frequency of the input signal, wherein the oscillation signal is used instead of the input signal when the input disconnection state of the input signal continues for a predetermined time or more. A switching circuit for switching a signal to be input to the phase difference detection means and the control means may be further included. When the switching circuit switches from the input signal to the oscillation signal, the switching circuit may further include an alarm unit that sends an alarm indicating the fact to the outside.

In short, the present PLL circuit detects a phase difference between an input signal having a reference input signal and an output signal having a dependent frequency signal, and generates a pulse width modulation signal having a pulse width corresponding to the detected value. The level is added to the output result of the phase comparator. By doing so, the reaction of the fluctuation due to the phase difference is accelerated, and the phase fluctuation amount and the steady phase error fluctuation are reduced. Further, when a phase difference equal to or more than a certain value occurs or when the input signal is interrupted, an alarm is generated, and when the input signal is interrupted, the signal is switched to a dependent frequency signal that follows the built-in oscillator.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. In the figure, the PLL circuit of the present embodiment generates a pulse having a pulse width corresponding to the phase comparison result in the phase comparison circuit 10, integrates the generated pulse, and adds a level to the phase comparison result. A function is added to the conventional circuit (FIG. 15).
In addition, a function of switching the oscillation signal of the crystal oscillator (XO) 7 provided inside the circuit to be input to the phase comparison circuit 10 in response to the abnormality of the phase difference or the interruption of the clock input is added.

A more detailed configuration of the PLL circuit to which these two functions are added will be described with reference to FIG. As shown in the figure, the circuit includes a reference input signal 10.
A frequency divider 5 for dividing 0, a crystal oscillator 7, a frequency divider 6 for dividing the oscillation signal of the crystal oscillator 7, and switching between a signal from the frequency divider 5 and a signal from the frequency divider 6. Output switch 8
And a frequency divider 4 for dividing the dependent frequency signal 300 output from the circuit, and a phase comparator 1 for comparing the phases of the signal 400 from the frequency divider 4 and the signal 500 from the switch 8. It is comprised including.

Further, the circuit comprises a signal 400 and a signal 500.
A pulse width modulator 11 that outputs a pulse having a pulse width corresponding to the phase difference between the pulse width modulator 11 and an integration circuit 13 that integrates a pulse output from the pulse width modulator 11 by charging a capacitor C via a resistor R. And an adder 12 for level-adding the integrated signal output from the integration circuit 13 to the signal from the phase comparator 1, an LPF 2 for smoothing the added output signal of the adder 12, and an LPF 2 for smoothing the signal. And a VCO 3 that outputs a signal 300 having a frequency corresponding to the voltage level.

Further, the circuit includes a clock state detector 91 for monitoring the input state of the reference input signal 100, and an alarm determiner for outputting an alarm based on the state of the phase difference between the output signal of the phase comparator 1 and the signal 500. 92.

As shown by a dashed line in FIG.
Phase comparator 1, pulse width modulator 11, adder 12
And the integration circuit 13, the phase comparison circuit 1 in FIG.
0 has been realized. Also, the alarm decision unit 9
2 and the clock state detector 91 implement the alarm detection circuit 9 in FIG.

In FIG. 2, a reference input signal 100 is frequency-divided by a frequency divider 5 to a frequency to be compared by a phase comparator 1, and is input to a pulse width modulator 11 as a signal 500 through a switch 8. . On the other hand, the dependent frequency signal 300 output from the VCO 3 is frequency-divided by the frequency divider 4 to the frequency to be compared by the phase comparator 1, and is input to the pulse width modulator 11 as a signal 400.

In the pulse width modulator 11, pulse width modulation is performed, and the pulse width of the output signal changes according to the phase difference between the signal 500 and the signal 400. The output signal whose pulse width changes is integrated by an integrating circuit 13 and then added in level by an adder 12.

The addition output signal of the adder 12 is LPF2
The oscillation frequency of the VCO 3 is controlled by the output of the smoothed signal. The frequency of the input voltage to the VCO 3 decreases as the potential decreases, and the frequency increases as the input voltage increases. For this reason, when the phase of the dependent frequency signal is advanced with respect to the reference input signal, the duty ratio pulse is gradually reduced at regular intervals, and the potential is sequentially reduced by passing through the integrator, and the dependent frequency signal from the VCO is reduced. Approximate the phase of the reference input signal. On the other hand, when the phase of the dependent frequency signal is delayed with respect to the reference input signal, a pulse having a large duty ratio is generated at regular intervals, and the potential is sequentially increased by passing through the integrator. Approximate the signal.

Since the output of the pulse width modulator 11 is integrated by the integrating circuit 13 and the level is added to the output of the phase comparator 1, the response of the fluctuation due to the phase difference is enhanced, and the phase due to the power fluctuation and the ambient temperature fluctuation is increased. The fluctuation amount and the steady phase error fluctuation can be reduced, and the convergence time of the PLL can be shortened.

Here, a configuration example of the pulse width modulator 11 in FIG. 2 will be described with reference to FIG. In the figure, the pulse width modulator 11 converts the dependent frequency signal 300 to N
A D-type flip-flop (hereinafter, referred to as a DFF) 11a having the frequency-divided signal 400 as a D input and the output signal 500 from the switch 8 as a clock input, and an output Q of the DFF 11a as a D input and a signal 400 as a clock input. D
An exclusive-OR gate 11c for receiving the FF 11b, the output Q of the DFF 11a, and the output Q of the DFF 11b as inputs and detecting a match between the two, loading the count value by the output of the gate 11c, and responding to the output of the DFF 11a An up / down counter 11d that counts down or counts up, and an up counter 11e that counts up the count value of the counter 11d as an input.
And a NAND gate 11q that receives the count value of the counter 11e as an input, and an inverter 11r that inverts the output of the NAND gate 11q. Note that the output of the inverter 11r is input to the integration circuit 13.

The pulse width modulator 11 includes a DFF 11
an inverter 11h for inverting the output Q of a, and a counter 1
OR gate 1 which receives each bit of 1d count value as input
1j, the output of the OR gate 11j and the inverter 11
h, an OR gate 11i for outputting a logical sum with the output of
An inverter 11k for inverting the output of the FF 11a; a NAND gate 11f receiving the output of the inverter 11k and each bit of the count value of the counter 11d; and an AND gate 11m receiving the output of the NAND gate 11f and the output of the OR gate 11i. It is comprised including. The counter 11d is enabled by the output of the AND gate 11m.

Further, the pulse width modulator 11 outputs the signal 40
A DFF 11n clocked by a signal C400 obtained by frequency-dividing the signal 400 at a predetermined frequency division ratio with 0 as an input, an inverter 11p for inverting this output, and the logical product of the output Q of the DFF 11n and the output of the inverter 11p are output. And an AND gate 11q.

In such a configuration, the dependent frequency signal 30
The signal 400 obtained by dividing 0 by N is input to the DFF 11a and held, and the output Q is input to the DFF 11b and held. When the output Q of the DFF 11a matches the output Q of the DFF 11b, that is, when the phase advance state or the phase delay state continues, the signal S4 output from the exclusive OR gate 11c becomes "L". Therefore, the count value is not loaded to the counter 11d. On the other hand, when the state changes from the phase advance state to the phase delay state or vice versa, the signal S4 output from the exclusive OR gate 11c becomes "H", so that the counter 11d is loaded with the count value. You. In this example, since inputs D0 to D2 are fixed at "L" and input D3 is fixed at "H", "1"
000 "is loaded into the counter 11d.

When the output Q of the DFF 11a is "H", the counter 11d performs a countdown operation. On the other hand, DF
When the output Q of F11a is "L", the counter 11d performs a count-up operation. The count outputs Q0 to Q3 of the counter 11d become the inputs D0 to D3 of the counter 11e. The counter 11e enters a load state by the output of the AND gate 11q. The AND gate 11q receives not only the signal 400 but also the output signal of the inverter 11p that inverts the output Q of the DFF 11n that receives the signal 400. Therefore, the counter 11e is in the load state while the signal 400 is at "H".

The count outputs Q0 to Q3 of the counter 11e
Is output via the NAND gate g and the inverter 11r. Only when the count outputs Q0 to Q3 are all "H", the output of the inverter 11r is "H" and the count output Q0
ＱQ3 is “L”, the inverter 11
The output of r becomes "L". The output of the inverter 11r is input to the integration circuit 13 and integrated.

FIGS. 4 and 5 are waveform diagrams showing the operation of the pulse width modulator 11. FIG. In both figures, S1, S2, etc.
Each symbol shown in FIG. 3 is shown.

First, when the state where the phase of the dependent frequency signal is advanced with respect to the reference input signal continues, the signal S1 from the frequency divider 5 and the signal S2 from the frequency divider 4
Is as shown in FIG. Then, the signal S3 becomes an “H” level signal and the counter 1
The output of 1d is a signal S5 in a down-count state. In the figure, "14", "13", "12" ... "5",
"4" is counted down. This signal S5 becomes the load data of the counter 11e, and is counted from the load data by the signal S6, and outputs the signal S7 of the "H" level with the final count value.

Since the signal S7 loads the signal S5 at a constant period, if the phase relationship between the signal S1 and the signal S2 shown in FIG. S7 is sequentially Dut at regular intervals.
The pulse changes to a pulse having a small y ratio.

On the other hand, if the state in which the phase of the dependent frequency signal is delayed with respect to the reference input signal continues, the phase relationship between the signal S1 from the frequency divider 1 and the signal S2 'from the frequency divider 2 Is as shown in FIG. The signal S3 'becomes an "L" level signal, and the output of the counter 11d becomes the signal S5' in an up-count state. In the figure, "5", "6", "7" ... "13", "14" are counted up. This signal S5 'is a counter 11e
If the relationship between the signal S1 and the signal S2 'shown in the figure is continued, the signal S5' is counted up at regular intervals, and as a result, the signal S7 'is sequentially duty cycled at regular intervals. The pulse changes to a pulse having a large ratio.

The signal S7 (signal S7 ') passes through an integrating circuit 13 consisting of a resistor R and a capacitor C. For this reason,
If the pulse has a small duty ratio, the output voltage level of the integrating circuit 13 will decrease, and if the pulse has a large duty ratio, the output voltage level will increase.

Therefore, when a pulse having a small duty ratio is generated at regular intervals, the voltage level after passing through the integration circuit is gradually lowered, thereby acting to delay the phase of the dependent frequency signal. Therefore, if the relationship that the phase of the signal S2 is advanced from that of the signal S1 continues, the duty ratio of the signal S7 is minimized even if there is a difference in the amount of advance, and the phase of the dependent frequency signal under the best condition Can be delayed.

Further, when a pulse having a large duty ratio is generated at regular intervals, the voltage level after passing through the integrating circuit is sequentially increased, thereby acting to advance the phase of the dependent frequency signal. Therefore, if the relationship that the phase of the signal S2 lags behind that of the signal S1 continues, the duty ratio of the signal S7 becomes maximum even if there is a difference in the amount of delay, and the phase of the dependent frequency signal under the best condition Can be advanced.

In FIG. 3, the counters 11d and 1d
By changing the number of digits of 1e, it is possible to easily change the pulse width output from the pulse modulator in response to requests for various responses such as loop gain, step, phase, and frequency.

Next, an example of the configuration of the phase comparator 1 in FIG. 2 will be described with reference to FIG. In the figure, a phase comparator 1 receives a signal 500 from a switch 8 as a clock input, a DFF 1 a having an input D fixed to “H”, and a signal 4.
00 is a clock input, a DFF 1b having a signal C400 'obtained by dividing the signal 400 at a predetermined dividing ratio as an input D, an inverter 1c for inverting the signal C400', and an output of the inverter 1c and an output Q of the DFF 1b. And an AND gate 1d. The output of the DFF 1a is controlled to a clear state by the output of the AND gate 1d.

FIGS. 7 and 8 are waveform diagrams showing the operation of the phase comparator 1. FIG. First, as shown in FIG. 7, when the phase of the dependent frequency signal 300 is advanced with respect to the reference input signal 100, the phase of the signal S2 is advanced from the signal S1, and the signal S8 has a duty ratio. Is output from the DFF 1a as a pulse having a smaller value. On the other hand, as shown in FIG. 8, when the phase of the dependent frequency signal 300 is advanced with respect to the reference input signal 100, the phase of the signal S2 'is later than that of the signal S1', and the signal S8 ' Is Du
The pulse is output from the DFF 1a as a pulse having a large ty ratio.

The signal S shown in FIGS.
8 (signal S8 ') has a pulse width in accordance with the phase difference between the reference input signal and the dependent frequency signal.
LL circuit. On the other hand, in the present PLL circuit, the adder 12 adds a voltage level which is the result of integrating the output of the pulse width modulator 11 described above by the integration circuit 13, and then adds LP
Since the input to F2 controls the VCO 3, the convergence time until the PLL locks is shortened.
A configuration example of the clock state detector 91 in FIG. 2 will be described with reference to FIG. In the figure, a clock state detector 91 includes an inverter 9 for inverting a reference input signal S1.
1e, a counter 91a that counts when the output of the inverter 91e is "H" (when the reference input signal S1 is "L"), and a counter that counts when the reference input signal S1 is "H". 91b and an inverter 9 for clearing the count value of the counter 91a when the output Q3 of the counter 91a becomes "H", that is, when the count value becomes "1000"("8" in decimal notation).
1c, and an inverter 91d for clearing the count value of the counter 91b when the output Q3 of the counter 91b becomes "H", that is, when the count value becomes "1000"("8" in decimal). Counter 91a
And an OR gate 91f which outputs a signal S12 which is an alarm output of "H" level when one of the output Q3 of the counter 91b and the output Q3 of the counter 91b is "H".

In such a configuration, in a state where the reference input signal S1 is always input, that is, in a state where "H" and "L" are alternately repeated, the counters 91a and 91b output the signal Q3 of "H". The count value is cleared before "". Therefore, when the reference input signal S1 is always input, the signal S, which is an alarm output, is output.
12 is not output.

On the other hand, in a state where the input of the reference input signal S1 is stopped, that is, in an abnormal state where the reference input signal S1 is fixed at "H" or "L", the counter 91a or 91b counts up. Will be When the output Q3 of the counter 91a or 91b becomes "H", that is, when the count value becomes "100".
When it becomes "0", a signal S12, which is an alarm output, is output.

In short, the clock state detector 91
Can detect an abnormal state of the reference input signal. As described above, when the reference input signal is interrupted, the signal is switched by the switch 8 and the reference input signal 100
Instead, the oscillation signal of the crystal oscillator 7 built in the circuit is employed. As a result, a signal obtained by dividing the oscillation signal of the crystal oscillator 7 by the divider 6 is output from the switch 8,
The dependent frequency signal 300 synchronized with this signal is output. Note that an alarm is output to the outside and the switch 8
May be notified that the switching in has been performed.

An example of the configuration of the alarm decision unit 92 in FIG. 2 will be described with reference to FIG. In the figure, the alarm determiner 92 includes counters 92a and 92b that perform a counting operation when the input to the terminal CD is "H", NAND gates 92k and 92m for resetting the counters 92a and 92b, and a NAND gate 92k. , 9
Inverters 92n and 92 for respectively inverting the output of 2m
p and a DFF 9 that inputs and holds the inverted signal
2c and 92e, and signals S9 and S10 output from the DFFs 92c and 92d operate as clock inputs.
FFs 92d and 92f, a NOR gate 92t having the outputs of the DFFs 92d and 92f as inputs, and a D which sequentially outputs the signal S11 output from the NOR gate 92t to a subsequent stage.
FFs 92-1 to 92-4 and these DFFs 92-1 to 9-9
An AND gate 92g that receives the output of 2-4 as an input, and a DFF 9 that receives and holds the output of the AND gate 92g.
2h, an inverter 92s for inverting the output of the DFF 92h, a counter 92i for performing a counting operation when the inverted signal is "H", and an output Q5 of the counter 92i is inverted to clear the count value. And an inverter 92r for generating an alarm output. Since the inverter 92j is provided, one of the counters 92a and 92b operates. Further, since the inverter 92q is provided, mutually inverted values are input to the DFFs 92d and 92f.

In this configuration, the count value of the counter 92a is cleared via the NAND gate 92k by the outputs Q4 and Q5 of the counter 92a that performs the counting operation. Also, the count value of the counter 92b is cleared via the NAND gate 92m by the outputs Q2 and Q3 of the counter 92b. The output of the NAND gate 92k is input to the DFF 92c after being inverted by the inverter 92n.
The output of the NAND gate 92m is inverted by the inverter 92p and then input to the DFF 92e. Note that the signal S1 is directly input to the counter 92a,
Since the signal S1 is inverted and input to 2b by the inverter 92j, when the input of either signal S1 is interrupted, one of the counters 92a and 92b starts the counting operation.

As described above, since the clear timing of the counter 92a and the counter 92b is fixed, the signal S9 output from the DFF 92c and the DFF 92e are output.
Has a fixed phase relationship with the output signal S10. The signal S9 becomes a clock input of the DFF 92d, and the signal S10 becomes a clock input of the DFF 92f.
The signal 8 is directly input to the DFF 92d and the DFF 9
The signal 8 is inverted and input to 2f by the inverter 92q.

Since the output Q of the DFF 92d and the output Q of the DFF 92f are input to the NOR gate 92t, if at least one of these two outputs Q is "H", the output Q
“L” is always input to the FFs 92-1 to 92-4. On the other hand, if both outputs Q are "L", D
“H” is input to the FF 92-1 and the DFF 92-
2, 92-3, 92-4.

When the outputs Q of the DFFs 92-1 to 92-4 all become "H", the output of the AND gate 92g becomes "H", which is input to the DFF 92h. That is, 4
Only when the output Q of the DFF 92d and the output Q of the DFF 92f are "L" continuously for the number of clocks, the output Q of the DFF 92h
Becomes “H”. This output Q is inverted by the inverter 92s and becomes a signal for causing the counter 92i to perform a counting operation. When the count operation of the counter 92i advances and the output Q5 becomes "H", the count value is cleared by the inverter 92r and an alarm is output.

FIG. 11 and FIG.
FIG. 6 is a waveform chart showing the operation of FIG. First, as shown in FIG. 11, the dependent frequency signal S
Consider a case where the phase of 2-1 is advanced. In this case, the signal S8-1 at the rising timing of the signal S10 is "H", and the signal S8-1 at the rising timing of the signal S9.
8-1 is "L". That is, the logic level of the signal S8-1 changes within the window from the rising timing of the signal 10 to the rising timing of the signal S9. Therefore, S11-1 which is the output of the NOR gate 92t changes from "L" to "H" at the rising timing of the signal S9. Therefore, DFF 92-1
AND gate 92 which is the logical product of the outputs Q of .about.92-4.
Since the output of g is "H" and the output of DFF 92h is "H", the counter 92i does not perform the counting operation. Therefore, the alarm output is at "H", indicating that it is in a normal state.

Here, when the phase of the dependent frequency signal S2-2 is more advanced with respect to the reference input signal S1,
The signal S8-2 at the rising timing of the signal S10 is "L", and the signal S8 at the rising timing of the signal S9 is low.
8-2 is "L". That is, since the phase is excessively advanced, the logical level of the signal S8-2 does not change within the window from the rising timing of the signal 10 to the rising timing of the signal S9. Therefore, the signal S11-2 output from the NOR gate 92t remains "L". Therefore, when the "L" state of the signal S11-2 occurs, the output of the AND gate 92g, which is the logical product of the outputs Q of the DFFs 92-1 to 92-4, is "L",
Since the output of the DFF 92h is "L", the counter 92
i performs a counting operation. The counting operation of the counter 92i is based on each output Q of the four DFFs 92-1 to 92-4.
Until all of them become "H". Therefore, even if the normal state is restored for a moment, the counting operation of the counter 92i is continued until the normal state continues four times.

The counting operation of the counter 92i is continued, and when the count value becomes "00100000", the output Q becomes "H". For this reason, the alarm output is set to "L" by the inverter 92r, indicating an abnormal state.

Since no alarm is output until the count value of the counter 92i reaches a predetermined value, the counter 92i operates as a timer until the alarm is sent. Therefore, even if the state becomes abnormal for a moment, the timer is stopped when the state is restored to the normal state thereafter.

As described above, by the time the alarm signal is output, the continuity of the abnormal state and the invariance of the alarm state by the timer are confirmed. That is, the DFF 92−
Since the continuity of the alarm state is detected by a four-stage configuration of 1 to 92-4, and the timer circuit confirms that the alarm state does not change, malfunction of the alarm judgment due to noise generated by disturbance or the like is prevented. is there.

On the other hand, as shown in FIG. 12, consider the case where the phase of the dependent frequency signal S2-1 'is delayed with respect to the reference input signal S1. In this case, the signal S8-1 ′ at the rising timing of the signal S10 is “H”, and the signal S8-1 ′ at the rising timing of the signal S9 is “L”. That is, the logic level of the signal S8-1 'changes within the window from the rising timing of the signal 10 to the rising timing of the signal S9. Therefore, S11-1 ′, which is the output of the NOR gate 92t, changes from “L” to “H” at the rising timing of the signal S9. Therefore, DFF 92-1
AND gate 92 which is the logical product of the outputs Q of .about.92-4.
Since the output of g is "H" and the output of DFF 92h is "H", the counter 92i does not perform the counting operation. Therefore, the alarm output is at "H", indicating that it is in a normal state.

Here, when the phase of the dependent frequency signal S2-2 'lags behind the reference input signal S1, the signal S8- at the rising timing of the signal S10.
2 ′ is “L”, and the signal S8-2 ′ at the rising timing of the signal S9 is “L”. That is, since the phase is too late, the logical level of the signal S8-2 'is changed to the signal 1
There is no change in the window between the rising timing of 0 and the rising timing of the signal S9. Therefore, the signal S11-2, which is the output of the NOR gate 92t,
'Remains "L". Therefore, the counter 92i performs the counting operation as in the case of FIG. 11 described above. The counting operation of the counter 92i is performed by four DFFs 92
It continues until all the outputs Q of −1 to 92-4 become “H”, and when the count value becomes “00100000”, the output Q becomes “H”. For this reason, the alarm output is set to "L" by the inverter 92r, indicating an abnormal state.

By the way, in FIG.
The above-mentioned window is formed by inputting the outputs Q4 and Q5 of 2a to the NAND gate 92k and inputting the outputs Q2 and Q3 of the counter 92b to the NAND gate 92m. Therefore, the width of the window can be freely changed by changing the output input from the counters 92a and 92b to the NAND gates 92k and 92m. If the width of the window is reduced, even a slight abnormality can be detected. That is, since an alarm is output when a phase difference equal to or more than a predetermined value that is arbitrarily determined continuously occurs, the predetermined value can be easily changed.

Further, by changing the number of stages of the DFFs 92-1 to 92-4, the value of the number of continuous occurrences of a phase difference equal to or more than a predetermined value at which an alarm should be output can be changed, and a higher quality alarm can be output. It is.

The counters 92a and 92b, DFF9
For 2-1 to 92-4, etc., a well-known PLD (Progra
It is generally realized using a mmable Logic Device), and the inside can be easily changed, so that the window width and the number of consecutive times described above can be easily changed.

When the PLL circuit is configured as described above, the pull-in characteristic of the PLL changes depending on the temperature. Therefore, as shown in FIG. 13, a temperature compensation circuit for detecting and compensating for a temperature change may be added to the configuration of FIG. That is, in the figure, an adder 14 is added between the integrating circuit 13 and the adder 12, and this adder 14
In the above, the level of the output of the integration circuit 13 and the temperature compensation circuit 15 are added.

FIG. 14 shows a configuration example of the adder 14 and the temperature compensating circuit 15. As shown in the figure, the adder 14 includes an operational amplifier 14a and a negative feedback resistor 1.
4b and the like. Also, the temperature compensation circuit 1
Reference numeral 5 includes a thermistor 15a and a resistor 15b connected in parallel with the thermistor 15a, and has a configuration in which a change in the resistance value of the resistor 15b due to a temperature change is offset by a change in the resistance value of the thermistor 15a. Then, by applying the output of the temperature compensation circuit 15 to the positive input terminal of the operational amplifier 14a, the voltage level of the positive input terminal is kept constant regardless of the temperature change. The output of the pulse width modulator 11 is applied to the negative input terminal of the operational amplifier 14a. The output voltage level of the temperature compensating circuit 15 is added to the voltage level of the output voltage, and then input to the adder 12.

The adder 12 is composed of an operational amplifier 12a and the like. In the adder 12, the output of the pulse width modulator 11 temperature compensated by the temperature compensating circuit 15 and the adder 14 is added to the output of the phase comparator 1. Then, the output of the adder 12 is supplied to the LPF as described above.
2 is input. If the oscillation frequency of the VCO 3 is controlled by the output of the LPF 2, the PLL circuit shown in FIG. 1 can be realized.

Further, the clock state detector 91 described above is used.
In the case of detecting the disconnection state of the clock, the switching unit 8 is switched to continue the operation using the oscillation signal of the crystal oscillator 7 built in the circuit, so that a continuous oscillation signal can be output without interruption. You can.

[0062]

As described above, according to the present invention, a pulse width corresponding to the phase difference between the reference input signal and the dependent frequency signal is generated and added to the output of the phase comparator, so that the fluctuation response due to the phase difference is suppressed. In other words, the amount of phase fluctuation and steady phase error fluctuation due to power supply fluctuation and ambient temperature fluctuation can be reduced, and the convergence time of the PLL can be shortened. Also, by providing a circuit for detecting the state of the reference input signal,
By switching to the crystal oscillator when the reference input signal is interrupted, there is an effect that a continuous oscillation signal can be output without interruption. Further, the provision of the temperature compensation circuit has the effect of minimizing the influence of the ambient temperature fluctuation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a more detailed configuration of the PLL circuit of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of a pulse width modulator in FIG. 2;

FIG. 4 is a time chart illustrating an operation of the pulse width modulator of FIG. 3;

FIG. 5 is a time chart illustrating an operation of the pulse width modulator of FIG. 3;

FIG. 6 is a block diagram showing a configuration example of a phase comparator in FIG. 2;

FIG. 7 is a time chart illustrating an operation of the phase comparator of FIG. 6;

FIG. 8 is a time chart illustrating an operation of the phase comparator of FIG. 6;

FIG. 9 is a block diagram illustrating a configuration example of a clock state detector in FIG. 2;

FIG. 10 is a block diagram illustrating a configuration example of an alarm determiner in FIG. 2;

FIG. 11 is a waveform chart showing the operation of the alarm determiner of FIG.

FIG. 12 is a waveform chart showing an operation of the alarm determiner of FIG.

FIG. 13 is a block diagram illustrating a detailed configuration of a PLL circuit to which a temperature compensation circuit is added.

FIG. 14 is a diagram illustrating a configuration example of an adder 14 and a temperature compensation circuit 15;

FIG. 15 is a block diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 1-3 frequency divider

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/14

Claims (8)

(57) [Claims] 1. A phase difference detecting means for detecting a phase difference between an output signal and an input signal, and an oscillating means for transmitting an output signal having a repetition frequency corresponding to a voltage level of the phase difference signal corresponding to the detected phase difference. when, wherein the output signal of the phase with respect to the input signal lead or has a control means for changing control of the voltage level of the phase difference signal in accordance with the number of consecutive times Nde including when the state of phase lag are continuous, the control The means has a pulse width corresponding to the number of consecutive times.
A pulse width modulator that produces pulses
And an integrating circuit for integrating the pulse width modulation pulse.
The integration output level of the integration circuit of
A PLL circuit characterized in that: 2. The pulse width modulator according to claim 1, wherein when the output signal continues to be in one of a phase advance state and a phase delay state with respect to the input signal, one of a count-up operation and a count-down operation is performed. includes up-down counter for performing other operations when carried out operation and the other state continues, PLL circuit according to claim 1, wherein generating a pulse having a pulse width corresponding to the count value of the counter . 3. A temperature detecting means for detecting a temperature change, and an adding circuit for controlling the addition characteristic to be kept constant in accordance with the detected temperature change and adding the integrated output level to the phase difference signal. Claims further comprising:
3. The PLL circuit according to 1 or 2 . 4. The temperature detecting means is a thermistor whose resistance value changes according to a predetermined temperature characteristic, and the change in resistance value by the thermistor cancels the change in resistance value of a resistor constituting the adding circuit. The PLL circuit according to claim 3 , wherein: 5. A method according to claim 1-4, characterized in that the phase difference of the output signal relative to the input signal further comprises an alarm means for sending an alarm to that effect to the outside when it is at or above a predetermined value The PLL circuit according to any one of the above. 6. The PLL circuit according to claim 5 , wherein the alarm means sends the alarm to the outside when the state where the phase difference is equal to or more than a predetermined value continues for a predetermined time or more. 7. An oscillator for generating an oscillation signal having a repetition frequency substantially the same as the repetition frequency of the input signal, and the oscillation signal instead of the input signal when the input signal is disconnected for a predetermined time or more. The PLL circuit according to any one of claims 1 to 6 , further comprising a switching circuit for switching the input to the phase difference detecting means and the control means. 8. The PLL according to claim 7 , further comprising an alarm means for sending an alarm to the outside when said switching circuit switches from said input signal to said oscillation signal. circuit.