JP4654919B2 - Phase synchronization circuit - Google Patents

Description

  The present invention relates to a phase synchronization circuit such as a high-frequency wireless communication apparatus, and more particularly to a phase synchronization circuit having a monitoring (alarm) function of synchronous / asynchronous operation with respect to a synchronous clock or the like.

  Conventionally, in a synchronous high-frequency radio communication system, a configuration is adopted in which a synchronization clock as a reference signal (reference signal) is input and a clock signal generated by a clock synchronization circuit that is phase-synchronized with the synchronization clock is used for transmission / reception processing. It is known that when an abnormality occurs in the synchronous clock, a voltage-controlled oscillator in the phase-locked loop is free-running to continuously generate and output a clock signal (see Patent Document 1).

  FIG. 4 is a diagram illustrating a configuration example of a high-frequency wireless communication apparatus including a clock synchronization circuit. Each transmitter / receiver is composed of a modem 11, a transmitter / receiver circuit 12, a duplexer 13, and a feeder 14. The modem 11 inputs a modulation signal and a synchronous clock and outputs a transmission signal, inputs an intermediate frequency signal from the transmission / reception circuit 12 and outputs a demodulation signal. The transmission / reception circuit 12 frequency-converts the transmission signal from the modulator / demodulator 11 and outputs it as a radio frequency signal to the duplexer 13, and frequency-converts the radio frequency signal from the duplexer 13 and outputs it to the modulator / demodulator 11. The antenna feeder 14 wirelessly transmits the output of the duplexer 13 and outputs the wirelessly received signal to the duplexer 13.

  Here, the transmission / reception circuit 12 is provided with a clock synchronization circuit that receives a synchronization clock and has a voltage-controlled oscillator capable of self-running oscillation therein, and does not require a synchronization configuration when the synchronization clock is defective (only one system). The voltage-controlled oscillator is configured to be free-running (operating asynchronously) and continuously output a clock signal.

  In addition, when the operation due to the synchronization clock is abnormal, an alarm is transmitted from the transmission / reception circuit 12 side to the modem 11 side, and alarm monitoring and clock signal switching control are performed on the modem 11 side. The alarm signal and the control signal for the synchronous / asynchronous operation of the voltage controlled oscillator can be transmitted / received by multiplexing means using a signal line between the modem 11 and the transmission / reception circuit 12, for example.

  FIG. 5 is a diagram illustrating a configuration example of the clock synchronization circuit of the transmission / reception circuit. This clock synchronization circuit has a PLL (Phase Locked Loop) circuit composed of a frequency divider 1, a phase comparator 2, a loop filter 4 and a voltage controlled oscillator 6 as a basic configuration. A switch 5 is provided in the input unit, and is configured to switch and output either the voltage output of the loop filter 4 or the voltage output of the internal control voltage generation circuit 8 output via the amplifier 7 to the voltage controlled oscillator 6. The alarm circuit 3 is connected to the output of the phase comparator 2, and the state of the phase comparator 2 is monitored.

  In this clock synchronization circuit, the voltage controlled oscillator 6 can be switched between synchronous oscillation and free-running oscillation by the switch 5, but the switch 5 is in a phase locked loop or with the internal control voltage generation circuit 8 in each operation mode. The voltage control oscillator 6 is connected in series, and the voltage drop or the like may affect the oscillation phase (frequency).

Further, the phase synchronization operation can be monitored by connecting the alarm circuit 3 to the phase comparator 2, and when an abnormality occurs in the PLL circuit, an abnormality in the output of the phase comparator 2 is detected and the alarm signal 103 is output. Output. For example, when there is no synchronous clock 102, or when an abnormality such as a frequency defect or a signal level decrease occurs, the PLL circuit becomes abnormal, the phase comparator 2 generates a signal such as an abnormal level, and the alarm signal 103 of the alarm circuit 3 is It becomes a specific logic level and an alarm state (alarm) is entered, which is notified to the modem side. The modem 11 on the alarm monitoring side detects the occurrence of an alarm and outputs a switching signal 101 to the switching unit 5 of the transmission / reception circuit 12, so that the clock synchronization circuit generates the control voltage of the voltage controlled oscillator 6. Control can be performed so as to switch from the output of the loop filter 5 to the output of the internal control voltage generator 8. However, when the control voltage of the voltage controlled oscillator 6 is switched to the output of the internal control voltage generator 8, the PLL circuit is not in the locked state and the voltage controlled oscillator 6 is in the free-running oscillation state, but the output of the phase comparator 2 is Since the abnormality continues, the alarm circuit 3 continues to generate an alarm.
JP-A-5-30092

  As described above, a phase-locked loop that can switch between synchronous oscillation and free-running oscillation (asynchronous oscillation) using a switch may affect the oscillation phase (frequency) of the switch, and the phase comparator The connected alarm circuit has a problem that even if the voltage-controlled oscillator 6 is switched to a normal free-running operation when the synchronous clock is abnormal, the PLL circuit continues to generate an alarm as an abnormality.

Regarding the problem of the latter alarm circuit, it is conceivable that the alarm monitoring side modem 11 ignores this alarm or uses the switching signal 101 so as not to output the alarm signal to the modem 11.
FIG. 6 is a diagram showing a configuration example in which alarm signals are prohibited. The basic PLL circuit configuration is the same as that shown in FIG. 5 except that an alarm control circuit 9 is provided at the output of the alarm circuit 3 and the switch 5 uses the output of the internal control voltage circuit 8 by the switching signal 101. When switching to, the alarm control circuit 3 is controlled by the switching signal 101 to prohibit the alarm signal 103 from being output to the modem 11 side.

  As described above, the clock synchronization circuit described above has a configuration in which a switch is provided at the input portion of the voltage controlled oscillator and an alarm control circuit that prohibits an alarm signal is provided at the output portion of the alarm circuit. The generated voltage drop tends to cause an oscillation phase offset, and the circuit configuration is complicated in order to solve an alarm problem.

(the purpose)
A main object of the present invention is to solve the above-described problems, and to provide a phase synchronization circuit that enables switching control between synchronous oscillation and free-running oscillation with a highly accurate oscillation phase (frequency).
Another object of the present invention is to provide a phase locked loop circuit capable of switching control between synchronous oscillation and free-running oscillation with a simple configuration.
Another object of the present invention is to provide a phase locked loop circuit that enables control of synchronous oscillation and free-running oscillation of a voltage controlled oscillator by controlling only a phase comparator.
Another object of the present invention is to provide a phase synchronization circuit including an alarm circuit that does not generate an alarm in a normal synchronous oscillation state and a free-running oscillation state.

The phase-locked loop of the present invention is the phase-locked loop that controls the oscillation phase of the voltage-controlled oscillator based on the output of the voltage-controlled oscillator or the output of the phase comparator that compares the phase of the divided output with the reference signal. A voltage generation circuit for applying a voltage for free-running oscillation to the output side of the comparator and the reference signal are monitored, and when the reference signal is in a normal state, the supply power of the phase comparator is controlled to be in an on state. A supervisory control circuit (for example, 11 in FIG. 3) for controlling the power supply of the phase comparator to be in an off state, and an alarm circuit for detecting an abnormality in the phase synchronization operation by the output of the phase comparator and outputting an alarm And a monitoring device (for example, 11 in FIG. 4) for monitoring the phase synchronization operation of the phase synchronization circuit based on the output of the alarm circuit. And it switches to the OFF state of the transmission of the reference signal.

Further, the phase synchronization circuit of the present invention is a phase synchronization circuit that controls the oscillation phase of the voltage controlled oscillator by the output of the voltage controlled oscillator or the output of the frequency comparator and the output of the phase comparator that compares the phase of the reference signal. A voltage generation circuit for applying a voltage for free-running oscillation to the output side of the phase comparator and the reference signal are monitored, and when the reference signal is in a normal state, the supply power of the phase comparator is controlled to be in an on state. , a monitoring control circuit for controlling the power supply of the phase comparator when the abnormal state to the oFF state (e.g., 11 in FIG. 3), outputs an alarm by detecting the abnormality of the phase lock operation by the output of the phase comparator comprising an alarm circuit, from time to the alarm circuit to generate an alarm, the length of time until the monitoring control circuit to turn off the power supply of said phase comparator to monitor the reference signal Characterized in that the set.

  Further, the present invention provides the phase synchronization circuit provided in the transmission / reception circuit in a high-frequency radio communication apparatus comprising a modem having a function as the monitoring device and a transmission / reception circuit having a frequency conversion function connected to the modem. The reference signal is input as a synchronous clock from the modem side, and the output of the alarm circuit is transmitted to the modem.

  According to the present invention, since no switching means is connected to the control input section of the voltage controlled oscillator, a highly accurate phase (frequency) oscillation operation is possible, and synchronous oscillation and free-running are performed without performing circuit switching control. Oscillation operation can be switched.

  Since switching control between synchronous oscillation and free-running oscillation is controlled by controlling the power supply of the phase comparator connected to the alarm circuit, an alarm circuit that does not generate an alarm in either normal synchronous oscillation or free-running oscillation is realized.

  In addition, there is no need for switching means, and there is no need for processing to ignore alarms on the monitoring side or the addition of an alarm control circuit that prohibits alarms, so switching control and monitoring between synchronous oscillation and free-running oscillation is possible with a simple configuration. It becomes.

  According to the present invention, the alarm monitoring device side receives an alarm once when the reference signal (synchronization clock) is defective, and then outputs a switching signal to switch the operation by turning off the power supply of the phase comparator. Can be returned to. In addition, it is possible to determine whether the phase synchronization circuit is operated in synchronous oscillation or free-running oscillation based on the occurrence of the alarm.

  If there is no abnormality in the circuit that transmits the synchronous clock, and the alarm is generated again even if the power supply of the phase comparator is turned on by the switching signal and the mode is switched to the synchronous oscillation mode again, the PLL system is abnormal. Judgment is possible.

  Further, the alarm monitoring side can be switched to the free-running oscillation mode without generating an alarm by turning off the power supply of the phase comparator with a switching signal even when the synchronization clock is normal.

  Even when the initial state is no synchronous clock, it operates in the same manner as when an abnormality occurs in the synchronous clock, and switches to free-running oscillation without any problem.

As an embodiment of the phase synchronization circuit of the present invention, an example of a clock synchronization circuit such as a high-frequency transmitter / receiver as shown in FIG.
(Description of configuration)
FIG. 1 is a diagram showing an embodiment of a clock synchronization circuit of the present invention.
In the present embodiment, the switch 5 and the alarm control circuit 9 relating to the use / non-use switching of the synchronous clock 102 in the conventional circuit shown in FIG. A configuration for performing control is provided.

  As a basic configuration of the clock synchronization circuit, a phase comparator 2, a loop filter 4, a voltage control oscillator 6, and a frequency divider 1, if necessary, constituting a PLL circuit are provided, and an internal control voltage generator 8 and a buffer amplifier 7 are further provided. And the output of the internal control voltage generator 8 is configured to be supplied directly between the output of the loop filter 4 and the input of the voltage controlled oscillator 6 via the amplifier 7. Further, the phase comparator 2 is provided with a power supply control circuit 10 for performing on / off control of the power supply voltage, a switching signal 101 is supplied to the power supply control circuit 10, and the alarm circuit 3 is connected to the output of the phase comparator 2. , Monitor its output status.

  Here, the DC output of the internal control voltage generator 8 is applied to its voltage control terminal so that the voltage controlled oscillator 6 oscillates at a predetermined frequency set in advance in a synchronous oscillation state by the synchronous clock 102. That is, in the synchronous oscillation state by the synchronous clock 102, the output of the phase comparator 2 outputs a signal level corresponding to a slight phase error centered on the zero level as a negative feedback signal, and the internal control voltage generator 8 The voltage-controlled oscillator 6 enters a synchronous oscillation state with a combined value with the direct current output.

  The phase comparator 2 has a function of comparing the phase of the output of the voltage controlled oscillator 6 with the phase of the synchronous clock 102 input from the outside as a reference signal (reference signal). Specifically, it has a synchronous detection function of multiplying the synchronous clock 102 and the oscillation output of the voltage controlled oscillator 6 by a double balanced modulator or the like, and the phase difference between both signals is detected in the power supply state to the phase comparator 2. A corresponding pulse-like or analog-like signal is output, and its DC component becomes the phase error signal, which is, for example, zero output in a non-power supply state.

  The output of the phase comparator 2 is supplied to the loop filter 4 and the alarm circuit 3. The loop filter 4 smoothes the output of the phase comparator 2 and the signal level corresponding to the phase error is supplied to the voltage controlled oscillator 6 as a control voltage. The negative feedback control is performed so that the phase of the oscillation output of the voltage controlled oscillator 6 is synchronized with the synchronous clock 102. Here, the frequency of the oscillation output of the voltage controlled oscillator 6 is the same frequency as that of the synchronous clock 102 or a frequency that is a reciprocal of the frequency division ratio of the frequency divider 1. The alarm circuit also basically has a function of inputting the output of the phase comparator 2 and monitoring the DC voltage in the same manner.

  FIG. 2 is a diagram showing a more specific configuration example of an alarm circuit or the like. The alarm circuit 32 includes a full-wave rectifier circuit 31 in which an input unit is connected to the connection point between the output of the phase comparator 2 and the loop filter 4, and the output of the full-wave rectifier circuit 31 is connected to, for example, a source-grounded P as a switch element. The gate of the channel type MOS transistor Q is connected, the drain of the MOS type transistor Q is connected to the power source V via the load resistor RL, and the resistor R and the capacitor C are formed at the connection point of the load resistor RL and the drain. A time constant circuit is connected and the voltage of the capacitor C is output as an alarm signal 103 to the monitoring side or the like. By connecting the time constant circuit, it is possible to prevent the occurrence of an alarm in a momentary abnormal state of the phase comparator 2 and to adjust the time until the alarm occurs.

  The phase comparator 2 includes a power supply control circuit 10 that performs on / off control of the power supply, and outputs a high-frequency synchronous detection output when the power-supplyed PLL circuit is operated, and the full-wave rectifier circuit 31 inputs a synchronous detection output. Similar to the loop filter 32, the filter generates a low-frequency DC component having a signal level corresponding to the phase error, and the DC component is always output to the gate of the MOS transistor Q as a positive signal by the rectifier circuit.

  During normal operation of the PLL circuit, this DC output is a low level negative feedback signal. At this time, the MOS transistor Q is turned on because a channel is formed because the gate potential is below the threshold value, and the charge of the capacitor C passes through the resistor R. The alarm signal 103 is at a low level and does not output an alarm state (alarm). On the other hand, the full-wave rectifier circuit 31 outputs a positive DC component due to the large phase error output of the phase comparator 2 during abnormal operation of the PLL circuit. The capacitor C is charged through the load resistor RL and the resistor R, and the alarm signal 103 becomes high level and becomes an alarm output.

  As described above, when the phase error between the synchronous clock 102 and the output of the voltage controlled oscillator 6 is large, an alarm is output to the alarm signal 103 of the alarm circuit 32. When an alarm state occurs, the monitoring side detects this and outputs a switching signal 101 to the power supply control circuit 10, and the power supply control circuit 10 switches off the power supply of the phase comparator 2. As a result, the output signal of the phase comparator 2 becomes zero and the direct current output of the full-wave rectifier circuit 31 also becomes zero, and the charge of the capacitor C is discharged through the conducting MOS transistor Q, and the alarm signal 103 is in the normal state. Return.

  At this time, the output of the loop filter 32 also drops to zero, but the output of the internal control voltage generator 8 is applied to the voltage controlled oscillator 6, and the oscillation operation of the frequency determined by the output continues, and the voltage controlled oscillator 6 is in a free-running oscillation state. Even in this state, since the output of the phase comparator 2 is at the zero level, the alarm signal 103 from the alarm circuit 32 does not enter the alarm state.

  As described above, in the present embodiment, the output of the phase comparator 2 and the output of the internal control voltage generator 8 are connected to the voltage control input section of the voltage controlled oscillator 6, and the power supply of the phase comparator 2 When is turned off and there is no output of the phase comparator 2, the operation is performed only with the output of the internal control voltage generator 6.

  Further, by controlling the power supply control circuit 10 with the switching signal 101, the power supply of the phase comparator 2 can be turned on / off (OFF). When the synchronous clock 102 is not used, the power of the phase comparator 2 is turned off. It is configured.

(Description of operation)
The operation of this embodiment will be described in detail with reference to an example applied to the high-frequency wireless communication apparatus shown in FIG.
First, as an initial state, when the synchronous clock 102 is normally supplied to the clock synchronous circuit and the voltage controlled oscillator 6 is operating with the synchronous clock, the phase comparator 2 outputs the synchronous clock 102 and the oscillation output of the voltage controlled oscillator 6. A phase error signal corresponding to the phase difference is output, and negative feedback control is performed on the oscillation phase shift of the voltage controlled oscillator to operate in the locked state.

  In this state, when an abnormality occurs in the synchronization clock 102, such as the period of the synchronization clock 102, a significant fluctuation in the signal level, or the synchronization clock is disconnected, the output of the phase comparator 2 changes greatly, and a predetermined threshold value of the MOS transistor is set. When the transistor is turned off and the transistor is turned off, the voltage of the capacitor C rises, and the alarm signal 103 becomes a high level indicating out of synchronization, indicating an alarm state.

  The alarm signal 103 is transmitted to an alarm monitoring side such as a modem, and on the alarm monitoring side, the voltage controlled oscillator 6 switches from a control state using the synchronous clock 102 to a free-running oscillation by the output of the internal control voltage generator 8 and a phase. The switching signal 101 set to turn off the power of the comparator 2 is output to the transmission / reception circuit.

  In the clock synchronization circuit of the transmission / reception circuit, the voltage controlled oscillator 6 is switched to the free-running control and the power of the phase comparator 2 is turned off, so that the output becomes zero and the gate voltage of the MOS transistor is lowered, and the transistor becomes conductive. Then, since the drain is grounded and the capacitor C is discharged, the alarm signal 103 becomes low level and returns to the normal state even when the synchronization is lost.

  The advantages of the alarm monitoring side by the alarm operation from the locked state of the voltage controlled oscillator 6 by the synchronous clock of the clock synchronization circuit to the self-running operation of the unlocked state can be summarized as follows.

  (1) Since the alarm monitoring side switches the switching signal 101 after an alarm is once generated (received) when the synchronous clock 102 is defective, the alarm is then returned to the normal state, but the clock synchronization circuit oscillates (synchronizes with the synchronous clock 102). It is possible to determine whether the operation is performed by oscillation (oscillation) or oscillation by the output of the internal control voltage generator 8 (self-running oscillation).

  (2) There is no abnormality in the circuit that transmits the synchronous clock 102, and the alarm is generated again even when the mode is switched to the mode that uses the synchronous clock 102 again by switching the phase comparator 2 on by the switching signal 101. If this is the case, it can be determined as an abnormality in the PLL system.

  (3) On the alarm monitoring side, even when the synchronous clock 102 is normal, the output of the internal control voltage generator 8 is used without generating an alarm by turning on / off the power of the phase comparator 2 by the switching signal 101. You can be in a mode to do.

  (4) Even when the initial state is the absence of the synchronous clock 102, the operation is the same as when the abnormality occurs in the synchronous clock 102, and the state is switched to the state where the output of the internal control voltage generator 8 is used without any problem.

(Other embodiments)
FIG. 3 is a diagram showing the configuration of another embodiment of the present invention. In the present embodiment, instead of controlling the power supply of the phase comparator 2 by the switching signal 101 from the alarm monitoring side, the clock synchronization circuit side voluntarily switches to the output of the internal control voltage generator 8 when the synchronization clock is abnormal. It has a function.

  The PLL configuration of the present embodiment is the same as that of the embodiment shown in FIGS. 1 and 2, but monitors whether the synchronous clock 102 is in a normal state or an abnormal state for the synchronous operation of the PLL at the input portion of the synchronous clock. When the monitoring control circuit 11 for controlling the power supply of the phase comparator 2 is provided, and when the synchronization clock 102 is normal, the monitoring control circuit 11 turns on the power of the phase comparator 2 to perform a synchronous operation, and the synchronization clock 102 is abnormal In this case, the power supply of the phase comparator 2 is turned off and the self-running operation is performed by the output of the internal control voltage generator 8.

  When the synchronization clock abnormality occurs, the time until the monitoring control circuit 11 monitors the synchronization clock 102 and turns off the phase comparator 2 is longer than the time until the alarm circuit 3 generates an alarm. Set as follows. With this setting, even when the operation based on the synchronous clock 102 is switched to the operation based on the output of the internal control voltage generator 8, an alarm can be generated until the power of the phase comparator 2 is turned off.

  Even when the voltage controlled oscillator 6 is switched from the output of the internal control voltage generator 8 to the operation of the output of the loop filter 4, an alarm is generated until the phase is pulled in by the phase comparator 2. It is possible to determine whether the operation is a synchronous oscillation operation or a free-running oscillation operation.

  In the present embodiment, the alarm monitoring side turns on / off the transmission of the synchronous clock 102 instead of transmitting the use / non-use switching signal of the synchronous clock 102, so that the phase synchronous oscillation by the output of the loop filter and the internal It is possible to switch the mode of free-running synchronous (asynchronous) oscillation using the output of the control voltage generator 8.

It is a figure which shows one Embodiment of the clock synchronization circuit of this invention. It is a figure which shows the more specific structural example of the alarm circuit etc. of this invention. It is a figure which shows the structure of other embodiment of this invention. It is a figure which shows the structural example of a high frequency radio | wireless communication apparatus. It is a figure which shows the structural example of the clock synchronization circuit of a transmission / reception circuit. It is a figure which shows the structural example which prohibited the alarm signal.

Explanation of symbols

1 Divider 2 Phase comparator 3 Alarm circuit 4 Loop filter 5 Switch 6 Voltage controlled oscillator 7 Amplifier (buffer amplifier)
8 Internal control voltage generator 9 Alarm control circuit 10 Power supply control circuit 11 Monitoring control circuit

Claims (6)

In a phase-locked loop that controls the oscillation phase of the voltage-controlled oscillator by the output of the voltage-controlled oscillator or a phase comparator that compares the phase of the divided output and the reference signal, it is free-running on the output side of the phase comparator A voltage generation circuit that applies an oscillation voltage and the reference signal are monitored, and when the reference signal is in a normal state, the power supply of the phase comparator is controlled to be in an on state, and in an abnormal state, the phase comparator A supervisory control circuit for controlling the power supply to an off state;
An alarm circuit for detecting an abnormality of the phase synchronization operation by an output of the phase comparator and outputting an alarm;
A monitoring device that monitors a phase synchronization operation of the phase synchronization circuit based on an output of the alarm circuit, wherein the monitoring device switches the transmission of the reference signal to an off state when the phase synchronization operation of the phase synchronization circuit is abnormal ; Phase synchronization circuit. In a phase-locked loop that controls the oscillation phase of the voltage-controlled oscillator by the output of the voltage-controlled oscillator or a phase comparator that compares the phase of the divided output and the reference signal, it is free-running on the output side of the phase comparator A voltage generation circuit that applies an oscillation voltage and the reference signal are monitored, and when the reference signal is in a normal state, the power supply of the phase comparator is controlled to be in an on state, and in an abnormal state, the phase comparator A supervisory control circuit for controlling the power supply to an off state;
An alarm circuit that outputs an alarm by detecting an abnormality of the phase synchronization operation by the output of the phase comparator ,
The phase characterized in that the time until the monitoring control circuit monitors the reference signal and turns off the power supply of the phase comparator is set longer than the time until the alarm circuit generates an alarm. Synchronous circuit. Based on the time until the alarm circuit generates an alarm, the supervisory control circuit determines the reference signal.
The time until monitoring the signal and turning off the power supply of the phase comparator is set long.
The phase-locked loop according to claim 1 . 4. The phase locked loop circuit according to claim 1, wherein the alarm circuit detects an abnormality in a synchronous oscillation operation by comparing a signal level of a phase error of an output of the phase comparator with a predetermined threshold value . A phase synchronization circuit provided in the transmission / reception circuit in a high-frequency wireless communication apparatus comprising a modem having a function as the monitoring device and a transmission / reception circuit having a frequency conversion function connected to the modem, 2. The phase synchronization circuit according to claim 1, wherein a signal is input as a synchronization clock from the modem side, and an output of the alarm circuit is transmitted to the modem . A loop filter is provided between the output of the phase comparator and the voltage controlled oscillator, and the voltage generation circuit supplies a voltage for free-running oscillation to a connection point between the loop filter and the voltage controlled oscillator via a buffer amplifier. 6. The phase synchronization circuit according to claim 1, wherein the phase synchronization circuit is applied.

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