JP2008199355A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit that maintains frequency accuracy by suppressing frequency fluctuations of the output, even in an interrupted or a recovered state of the input signal. <P>SOLUTION: The PLL circuit is provided with a first frequency-dividing means 3 for frequency-dividing an input into a desired frequencies; a second frequency dividing means 8 for frequency-diving an output of a voltage controlled oscillator 7 into a desired frequencies; a first phase comparing means 4 between the output of the first frequency-dividing means 3 and an output of the second frequency-dividing means 8; a first selecting means 11 for one of an inverted output of the first frequency-dividing means 3 and an inverted output of the second frequency-dividing means 8; a second phase comparing means 12, between the output of the second frequency-dividing means 8 and the output of the first selecting means 11; a second selecting means 6 for one of an output of the first phase comparing means 4 and the output of the second phase comparing means 12; an input signal monitoring means 9; and a timing-generating means 10 for generating the timing for a fixed period, with respect to a monitoring result from the input signal monitoring means 9, wherein the first selecting means 11 and the second selecting means 6 perform selections according to the signal state from the timing-generating means 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit that generates an output signal synchronized with an input signal. In particular, the present invention relates to a PLL circuit that is used in an information communication device or the like and suppresses frequency fluctuations of an output signal even when the input signal is disconnected or recovered, and maintains frequency accuracy.

  In recent years, a PLL circuit has been widely used as a circuit that generates a signal synchronized with a reference signal.

  An example of a conventional PLL circuit as disclosed in Patent Document 1 will be described with reference to FIG.

  In FIG. 2, a PLL circuit divides an input signal from an input terminal 21 to which a reference input signal is applied, an output terminal 22 to which an output signal synchronized with the input signal is applied, and an input signal from the input terminal into a desired frequency. Frequency divider 23, phase comparator 24 that compares the phases of the two signals, filter 25 that removes unnecessary high-frequency components from the phase comparison result of the phase comparator and converts it to a DC signal, and a DC control signal from the filter A voltage-controlled oscillator 26 that outputs the output signal, and a frequency-dividing circuit 27 that divides the output signal from the voltage-controlled oscillator to a desired frequency.

  The operation of the PLL circuit is as follows. In the phase comparator 24, a signal obtained by dividing the input signal applied to the input terminal 21 to a desired frequency by the divider circuit 23 and an output signal of the voltage controlled oscillator 26 are divided by the divider circuit 27. By repeating the operation of comparing the phase of the signal divided to a desired frequency and applying the DC control signal corresponding to the phase comparison result to the voltage controlled oscillator 26 via the filter 25 to control the output frequency, the input signal The output signal synchronized with is generated.

  That is, an output signal synchronized with the input signal is constantly generated through an automatic control system using a feedback loop formed by the phase comparator 24, the filter 25, the voltage control oscillator 26, and the frequency divider circuit 27.

  If the frequency of the input signal applied to the input terminal 21 changes, for example, in the positive direction, the phase comparator 24 divides the input signal applied to the input terminal 21 to a desired frequency by the frequency divider 23. A phase difference is generated between the signal and the signal obtained by dividing the output signal of the voltage controlled oscillator 26 to a desired frequency by the frequency divider circuit 27. Therefore, the phase comparator 24 operates so as to output a phase comparison result corresponding to the phase difference and to provide a voltage control oscillator 26 with a DC control signal for changing the frequency of the output signal in the plus direction via the filter 25.

  Therefore, the output signal of the voltage controlled oscillator 26 changes in the plus direction, and is fed back to the phase comparator 24 via the frequency divider circuit 27 and is again phase-compared with the input signal. Therefore, the automatic control system synchronizes with the input signal. Output signal can be generated.

  The same applies when the frequency of the input signal applied to the input terminal 21 changes in the negative direction.

  FIG. 5 shows an operation example of the PLL circuit. When the input signal applied to the input terminal 1 is in a normal state, the control voltage of the voltage controlled oscillator 26 is in the vicinity of the center control voltage (≈VDD / 2), and the output frequency of the voltage controlled oscillator 26 is in the vicinity of the center frequency (≈ F0).

Further, Patent Document 2 discloses that the phase comparator output that stores the phase comparator output stored when the input signal is released is aligned and released.
JP 2001-85995 A (see FIG. 1) JP 2002-135115 A

  However, in the conventional PLL circuit, when the input signal applied to the input terminal 21 is in an abnormal state (disconnected state), the signal input to the phase comparator 24 via the frequency divider circuit 23 is lost. As a result, the DC control signal from the filter 25 (that is, the control voltage of the voltage controlled oscillator 26) is, for example, near the center control voltage (≈VDD / 2), for example, near the power supply voltage level (≈VDD), or near the ground level (≈0). Therefore, the output frequency of the voltage controlled oscillator 26 fluctuates in the plus direction or minus direction by the frequency variable range of itself.

  For example, if the frequency variable range of the voltage controlled oscillator 26 is ± 100 ppm, when the input signal applied to the input terminal 21 is in an abnormal state (disconnected state), the output terminal 22 is only +100 ppm or −100 ppm. There is a problem in that an output signal having a fluctuating frequency is applied, which has a great influence on the system. Furthermore, in some cases, the entire network may be seriously affected.

  Therefore, an object of the present invention is to provide a PLL circuit that is used in a communication device or the like and suppresses frequency fluctuation of an output signal even when the input signal is disconnected or recovered, and maintains frequency accuracy.

  In order to solve the above-mentioned problem, the invention according to claim 1 is a PLL circuit including a voltage controlled oscillator, wherein the first frequency dividing means for dividing the input signal to a desired frequency, and the output of the voltage controlled oscillator Second frequency dividing means for dividing the signal to a desired frequency, first phase comparing means for comparing the phases of the output signal of the first frequency dividing means and the output signal of the second frequency dividing means, First selection means for selecting one of an output signal from the first frequency dividing means and an inverted signal obtained by inverting the output signal from the second frequency dividing means, the output signal from the second frequency dividing means, and the first selection Second phase comparing means for comparing the phase with the output signal of the means; second selecting means for selecting one of the output signal of the first phase comparing means and the output signal of the second phase comparing means; Input signal monitoring means for monitoring the state of the input signal; and Timing generating means for generating a timing of a predetermined time with respect to the monitoring result from the monitoring means, wherein the first selection means and the second selection means are configured to output the one signal according to the signal state from the timing generation means. It is characterized by selecting.

  According to a second aspect of the present invention, in the PLL circuit according to the first aspect, the input signal monitoring means monitors whether the state of the input signal is a disconnected state or a recovered state.

  According to a third aspect of the present invention, in the PLL circuit according to the first or second aspect, an unnecessary high-frequency component is removed from the phase comparison result of the first phase comparison means and converted into a DC signal, so that the second selection is performed. A first filter that outputs to the means, and a second filter that removes an unnecessary high-frequency component from the phase comparison result in the second phase comparison means, converts it to a direct current signal, and outputs it to the second selection means, The filter time constant of the second filter is configured to have a sufficiently larger relationship than the filter time constant of the first filter.

  According to a fourth aspect of the present invention, in the PLL circuit according to any one of the first to third aspects, the timing generation means is substantially simultaneous when the state of the input signal changes from a normal state to a disconnected state. Timing is generated, and when the state of the input signal recovers from the disconnected state to the recovered state, timing having a time constant sufficiently larger than the filter time constant is generated.

  According to a fifth aspect of the present invention, in the PLL circuit according to any one of the first to fourth aspects, the first selection unit is configured to perform the first selection when a signal state from the timing generation unit is a normal state. The output signal from the 1-frequency divider is selected, and the inverted signal is selected when the signal state from the timing generator is an abnormal state (disconnected state).

  According to a sixth aspect of the present invention, in the PLL circuit according to any one of the first to fifth aspects, the second selection unit is configured to perform the first selection when the signal state from the timing generation unit is a normal state. The output signal of the first phase comparison means is selected, and the output signal of the second phase comparison means is selected when the signal state from the timing generation means is an abnormal state (disconnected state).

  As described above, according to the present invention, by switching the PLL circuit according to the state of the input signal, when the input signal is in an abnormal state (disconnected state), the two input to the second phase comparison means Since both signals are signals from the voltage controlled oscillator and there is no phase difference between the two signals, the DC control signal from the second filter can be fixed near the center control voltage of the voltage controlled oscillator. The output frequency does not fluctuate greatly, and it is possible to operate near the center frequency.

  The best mode of the present application will be described below with reference to the accompanying drawings. In addition, about this embodiment, it is only one form for implementing this application, and this application is not limited by this embodiment.

  The configuration of the PLL circuit according to the embodiment of the present invention is shown in FIG.

  As shown in FIG. 1, the PLL circuit of this embodiment includes an input terminal 1 to which a reference input signal is applied, an output terminal 2 to which an output signal synchronized with the input signal is applied, and an input signal from the input terminal 1. The frequency dividing circuit 3 as the first frequency dividing means for dividing the signal to the desired frequency, the phase comparator 4 as the first phase comparing means for comparing the phases of the two signals, and the phase comparison result in the phase comparator 4 Filter 5 serving as a first filter that removes unnecessary high-frequency components, converts it to a DC signal, and outputs the signal to selection circuit 6, and voltage control that outputs an output signal corresponding to the DC control signal from filter 5 via selection circuit 6 The state of the input signal applied to the input terminal 1 (disconnection state and recovery state) is determined by the frequency divider 8 as the second frequency dividing means for dividing the output signal from the oscillator 7 and the voltage controlled oscillator 7 to a desired frequency. Input signal monitor to monitor The input signal monitoring circuit 9 as a timing generator, a timing generation circuit 10 as a timing generation means for generating a fixed time timing for the result from the input signal monitoring circuit 9, and the two input signals according to the signal state from the timing generation circuit 10 Selection circuit 11 as first selection means for selecting one, phase comparator 12 as second phase comparison means for comparing the phases of two signals, and removal of unnecessary high-frequency components from the phase comparison result in phase comparator 12 A filter 13 as a second filter that converts the signal into a DC signal and outputs it to the selection circuit 6, and a selection circuit 6 as a second selection means for selecting one of the two input signals according to the signal state from the timing generation circuit 10. Prepare.

  The selection circuit 11 selects a signal from the frequency dividing circuit 3 if the signal state from the timing generation circuit 10 is normal, and divides if the signal state from the timing generation circuit 10 is abnormal (disconnected state). Operate to select the signal from circuit 8.

  The selection circuit 6 selects the signal from the filter 5 if the signal state from the timing generation circuit 10 is normal, and the filter 13 if the signal state from the timing generation circuit 10 is abnormal (disconnected state). Operates to select the signal from

  According to the present embodiment, the state of the input signal applied to the input terminal 1 by the input signal monitoring circuit 9 and the timing generation circuit 10, that is, the disconnection state and the recovery state are monitored, and the selection circuit 11, The PLL circuit that operates is controlled by controlling the selection circuit 6.

  That is, when the input signal applied to the input terminal 1 is in a normal state, the PLL circuit is an automatic control system using a feedback loop formed by the phase comparator 4, the filter 5, the voltage control oscillator 7, and the frequency divider circuit 8. When the input signal applied to the input terminal 1 is in an abnormal state (disconnected state), the PLL circuit is a feedback loop formed by the phase comparator 12, the filter 13, the voltage control oscillator 7, and the frequency divider circuit 8. It has a circuit configuration that operates in an automatic control system.

  As described above, when the input signal applied to the input terminal 1 is in an abnormal state (disconnected state) by switching the PLL circuit according to the state of the input signal, the two signals input to the phase comparator 12 are both voltages. Since it is a signal from the control oscillator 7 and there is no phase difference between the two signals, the DC control signal from the filter 13 can be fixed in the vicinity of the center control voltage (≈VDD / 2) of the voltage control oscillator 7.

  Therefore, the output frequency of the voltage controlled oscillator 7 does not vary greatly, and it is possible to operate near the center frequency (≈F0).

  Next, an example of the operation of the PLL circuit according to the present embodiment will be described with reference to FIGS.

  In the configuration of the PLL circuit according to the present embodiment of FIG. 1, the filter 5 and the filter 13 have time constants τ1 and τ2 that determine the response characteristics of the PLL circuit, respectively, so that the time constant becomes τ1 << τ2. It is configured.

  Further, the timing generation circuit 10 generates a timing of a certain time (= T) with respect to the result from the input signal monitoring circuit 9, and T≈0 when the state of the input signal changes from the normal state to the disconnected state. When the state of the input signal changes from the disconnected state to the recovered state, the timing of T> τ2 is generated.

  First, the operation of the PLL circuit when the input signal applied to the input terminal 1 is in a normal state and there is no frequency deviation of the input signal (ΔF / F0≈0) will be described with reference to FIG.

  In FIG. 3, when the input signal applied to the input terminal 1 is in a normal state, the PLL circuit is an automatic control system using a feedback loop formed by the phase comparator 4, the filter 5, the voltage control oscillator 7, and the frequency divider circuit 8. Is working with.

  When the input signal applied to the input terminal 1 is in a normal state, the selection circuit 11 operates so as to select the signal from the frequency dividing circuit 3, so that the same signal is supplied to the phase comparator 4 and the phase comparator 12. Is input, and the output signals of the filter 5 and the filter 13 have the same result.

  Here, since there is no frequency deviation of the input signal (ΔF / F0≈0), the output signals of the filter 5 and the filter 13 are both near the center control voltage (≈VDD / 2), and the output of the voltage controlled oscillator 7 The frequency is operating near the center frequency (≈F0).

  When the input signal is in a normal state, the phase comparator 4 and the filter are also used in an automatic control system using a feedback loop including the phase comparator 12, the filter 13, the voltage control oscillator 7, and the frequency divider circuit 8. 5, the same value as that of the feedback loop constituted by the voltage controlled oscillator 7 and the frequency dividing circuit 8 is taken.

  Next, when the input signal applied to the input terminal 1 is in an abnormal state (disconnected state), the selection circuit 6 is immediately switched (T≈0) by a signal from the timing generation circuit 10. That is, the PLL circuit is switched to operate in an automatic control system using a feedback loop formed by the phase comparator 12, the filter 13, the voltage control oscillator 7, and the frequency divider circuit 8. At the same time, the selection circuit 11 is switched immediately (T≈0) by the signal from the timing generation circuit 10.

  That is, the two signals input to the phase comparator 12 are both signals from the frequency dividing circuit 8, and there is no phase difference between the two signals, so that the output signal of the filter 13 is in the vicinity of the center control voltage of the voltage controlled oscillator 7. It can be fixed at (≈VDD / 2).

  Therefore, the control voltage input to the voltage controlled oscillator 7 by switching of the operating PLL circuit does not vary greatly from the vicinity of the center control voltage (≈VDD / 2), and the output frequency of the voltage controlled oscillator 7 is also close to the center frequency ( It becomes possible to operate at ≈F0).

  When the input signal is in an abnormal state, when the input signal is in a normal state, a value similar to that of a feedback loop including the phase comparator 4, the filter 5, the voltage controlled oscillator 7, and the frequency divider circuit 8 is taken. Therefore, the output to the voltage controlled oscillator 7 does not vary greatly.

  When the input signal applied to the input terminal 1 returns to a normal state (recovered state), the selection circuit 6 switches back to a certain time (T> τ2) by a signal from the timing generation circuit 10.

  That is, the PLL circuit switches back to operate in an automatic control system using a feedback loop formed by the phase comparator 4, the filter 5, the voltage control oscillator 7, and the frequency divider circuit 8.

  At this time, in the PLL circuit formed by the phase comparator 4, the filter 5, the voltage controlled oscillator 7, and the frequency divider circuit 8, the input signal changes from the disconnected state to the recovered state. It takes time until the PLL circuit is stabilized by the time constant (= τ1).

  Therefore, when switching back immediately (T≈0), the PLL circuit is not stable, so switching back after a certain time (T> τ2, τ2 >> τ1). Is operated in the vicinity of the center control voltage (≈VDD / 2) which is the output signal of the filter 13. At the same time, the selection circuit 11 is switched back after a certain time (T> τ2) by the signal from the timing generation circuit 10.

  Therefore, the control voltage of the voltage controlled oscillator 7 does not fluctuate from the vicinity of the center control voltage (≈VDD / 2) even when the operating PLL circuit is switched back, and the output frequency of the voltage controlled oscillator 7 is also near the center frequency (≈F0). ) Can be operated.

  Next, the operation of the PLL circuit when the input signal applied to the input terminal 1 is in a normal state and there is a frequency deviation of the input signal (ΔF / F0 ≠ 0) will be described with reference to FIG.

  In FIG. 4, when the input signal applied to the input terminal 1 is in a normal state, the PLL circuit is automatically controlled by a feedback loop formed by the phase comparator 4, the filter 5, the voltage control oscillator 7, and the frequency divider circuit 8. The system is operating.

  When the input signal applied to the input terminal 1 is in a normal state, the selection circuit 11 operates so as to select the signal from the frequency dividing circuit 3, so that the same signal is supplied to the phase comparator 4 and the phase comparator 12. And the output signals of the filter 5 and the filter 13 have the same result.

  Here, when the frequency deviation of the input signal is deviated from F0 + ΔF by ΔF in the plus direction, the output signals of the filter 5 and the filter 13 are both control voltages deviated in the plus direction with respect to the center control voltage (≈ (VDD / 2 ) + Α), and the output frequency of the voltage controlled oscillator 7 is operating at a frequency (≈F0 + ΔF) shifted in the positive direction with respect to the center frequency.

  When the input signal is in a normal state, the phase comparator 4 and the filter are also used in an automatic control system using a feedback loop including the phase comparator 12, the filter 13, the voltage control oscillator 7, and the frequency divider circuit 8. 5, the same value as that of the feedback loop constituted by the voltage controlled oscillator 7 and the frequency dividing circuit 8 is taken.

  On the other hand, when the input signal applied to the input terminal 1 is in an abnormal state (disconnected state), the selection circuit 6 is switched immediately (T≈0) by a signal from the timing generation circuit 10. That is, the PLL circuit is switched to operate in an automatic control system using a feedback loop formed by the phase comparator 12, the filter 13, the voltage control oscillator 7, and the frequency divider circuit 8. At the same time, the selection circuit 11 is switched immediately (T≈0) by the signal from the timing generation circuit 10.

  That is, the two signals input to the phase comparator 12 are both signals from the frequency divider circuit 8 and there is no phase difference between the two signals, so that the output signal of the filter 13 is in the vicinity of the center control voltage of the voltage controlled oscillator 7. It can be fixed at (≈VDD / 2).

  At this time, the control voltage of the voltage controlled oscillator 7 changes from (VDD / 2) + α to VDD / 2. However, if the control voltage is suddenly changed, the output frequency of the voltage controlled oscillator 7 changes from F0 + ΔF to F0. May fluctuate instantaneously, and the circuit connected to the subsequent stage of the output terminal 2 may not be able to follow this sudden frequency fluctuation and affect the system.

  Therefore, the output frequency of the voltage controlled oscillator 7 is also increased by giving the response characteristic of the filter 13 a large time constant τ2 and slowly changing the control voltage of the voltage controlled oscillator 7 from (VDD / 2) + α to VDD / 2. Fluctuating slowly from F0 + ΔF to F0 so that the circuit connected to the subsequent stage of the output terminal 2 can follow this frequency variation, and the output frequency of the voltage controlled oscillator 7 can be operated near the center frequency (F0). It becomes possible.

  Therefore, it is possible to provide a PLL circuit that does not affect the system by switching the operating PLL circuit.

  When the input signal is in an abnormal state, when the input signal is in a normal state, a value similar to that of a feedback loop including the phase comparator 4, the filter 5, the voltage controlled oscillator 7, and the frequency divider circuit 8 is taken. Therefore, the output to the voltage controlled oscillator 7 does not vary greatly.

  When the input signal applied to the input terminal 1 returns to a normal state (recovered state), the selection circuit 6 switches back to a certain time (T> τ2) by a signal from the timing generation circuit 10.

  That is, the PLL circuit switches back to operate in an automatic control system using a feedback loop formed by the phase comparator 4, the filter 5, the voltage control oscillator 7, and the frequency divider circuit 8.

  At this time, in the PLL circuit formed of the phase comparator 4, the filter 5, the voltage controlled oscillator 7, and the frequency divider circuit 8, the input signal is recovered from the disconnected state. It takes time to stabilize the PLL circuit by the time constant (= τ1).

  Therefore, when switching back immediately (T≈0), the PLL circuit is not stable, so switching back after a certain time (T> τ2, τ2 >> τ1). The interval is operated by the output signal of the filter 13.

  In addition, since the frequency of the recovered input signal is shifted in the positive direction from F0 + ΔF, the control voltage of the voltage controlled oscillator 7 changes from VDD / 2 to (VDD / 2) + α. Changes the output frequency of the voltage controlled oscillator 7 instantaneously from F0 to F0 + ΔF, and the circuit connected to the subsequent stage of the output terminal 2 cannot follow this sudden frequency fluctuation, affecting the system. May be given.

  Therefore, the output frequency of the voltage controlled oscillator 7 is also increased by giving the response characteristic of the filter 13 a large time constant τ2 and slowly changing the control voltage of the voltage controlled oscillator 7 from (VDD / 2) + α to VDD / 2. The circuit fluctuates slowly from F0 to F0 + ΔF, and the circuit connected to the subsequent stage of the output terminal 2 can follow this frequency fluctuation.

  Accordingly, it is possible to provide a PLL circuit that does not affect the system even when the operating PLL circuit is switched back.

1 is a block diagram of a PLL circuit according to the present invention. It is a block diagram of a conventional PLL circuit. It is the operation example 1 of the PLL circuit by this invention. It is the operation example 2 of the PLL circuit by this invention. It is an operation example of a conventional PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Input terminal 2 ... Output terminal 3 ... Frequency divider 4 ... Phase comparator 5 ... Filter 6 ... Selection circuit 7 ... Voltage control oscillator 8 ... Frequency division Circuit 9 ... Input signal monitoring circuit 10 ... Timing generation circuit 11 ... Selection circuit 12 ... Phase comparator 13 ... Filter

Claims (6)

In a PLL circuit having a voltage controlled oscillator,
First frequency dividing means for dividing the input signal to a desired frequency;
Second frequency dividing means for dividing the output signal of the voltage controlled oscillator to a desired frequency;
First phase comparison means for comparing the phases of the output signal of the first frequency divider and the output signal of the second frequency divider;
First selection means for selecting one of an output signal of the first frequency dividing means and an inverted signal obtained by inverting the output signal of the second frequency dividing means;
Second phase comparison means for comparing phases of the output signal of the second frequency dividing means and the output signal of the first selection means;
Second selection means for selecting one of the output signal of the first phase comparison means and the output signal of the second phase comparison means;
Input signal monitoring means for monitoring the state of the input signal;
Timing generation means for generating a fixed time timing with respect to the monitoring result from the input signal monitoring means,
The PLL circuit according to claim 1, wherein the first selection unit and the second selection unit select the one signal in accordance with a signal state from the timing generation unit. The PLL circuit according to claim 1,
The PLL circuit characterized in that the input signal monitoring means monitors whether the state of the input signal is a disconnected state or a recovered state. The PLL circuit according to claim 1 or 2,
A first filter that removes an unnecessary high-frequency component from the phase comparison result in the first phase comparison means, converts it to a direct current signal, and outputs it to the second selection means;
A second filter that removes an unnecessary high-frequency component from the phase comparison result in the second phase comparison means, converts it to a direct current signal, and outputs it to the second selection means,
A PLL circuit configured so that a filter time constant of the second filter is sufficiently larger than a filter time constant of the first filter. The PLL circuit according to any one of claims 1 to 3,
The timing generation means generates substantially simultaneous timing when the state of the input signal changes from a normal state to a disconnected state, and when the state of the input signal recovers from a disconnected state to a recovered state, A PLL circuit that generates timing having a sufficiently large time constant. The PLL circuit according to any one of claims 1 to 4,
The first selecting unit selects an output signal from the first frequency dividing unit when the signal state from the timing generating unit is a normal state, and the signal state from the timing generating unit is in an abnormal state (disconnected state). ), The inverted signal is selected. The PLL circuit according to any one of claims 1 to 5,
The second selection unit selects the output signal of the first phase comparison unit when the signal state from the timing generation unit is normal, and the signal state from the timing generation unit is in an abnormal state (disconnected state). If so, the output signal of the second phase comparison means is selected.

Images