JP3349416B2 - Power semiconductor device - Google Patents
Power semiconductor deviceInfo
- Publication number
- JP3349416B2 JP3349416B2 JP32696497A JP32696497A JP3349416B2 JP 3349416 B2 JP3349416 B2 JP 3349416B2 JP 32696497 A JP32696497 A JP 32696497A JP 32696497 A JP32696497 A JP 32696497A JP 3349416 B2 JP3349416 B2 JP 3349416B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- metal
- output terminal
- power semiconductor
- metal base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
- H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/222—Completing of printed circuits by adding non-printed jumper connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は電力半導体装置内の
複数の電力半導体チップ間の接続の改善に関する。The present invention relates to an improvement in connection between a plurality of power semiconductor chips in a power semiconductor device.
【0002】[0002]
【従来の技術】この種の従来技術を図5と図6を参照し
て説明する。この電力半導体装置は,金属ベース1と,
金属ベース1に半田付けされた絶縁層2と,この絶縁層
2に半田付けされた入出力端子3,44と,入出力端子
3及び44に半田付けされた第1の電力半導体チップ7
及び第2の電力半導体チップ8と,電力半導体チップ7
と8を接続する金属ブリッジ46とを具備している。2. Description of the Related Art A prior art of this type will be described with reference to FIGS. This power semiconductor device comprises a metal base 1 and
An insulating layer 2 soldered to the metal base 1, input / output terminals 3 and 44 soldered to the insulating layer 2, and a first power semiconductor chip 7 soldered to the input / output terminals 3 and 44
And the second power semiconductor chip 8 and the power semiconductor chip 7
And a metal bridge 46 connecting the first and the second metal bridge 8.
【0003】入出力端子44は,コの字形をして金属ベ
ースに対して水平に位置する部分が絶縁層2上に半田付
けされ,その先端が金属ベース1に対して垂直に立ち上
がる部分を有している。入出力端子44の水平に位置す
る他方の面には第2の電力半導体チップ8が半田付けさ
れ,入出力端子44の金属べース1に垂直に立ち上がる
部分の先端は端子幅が細くなっている。また,第2の電
力半導体チップ8の上には入出力端子45が半田付けさ
れ,さらに,第1の電力半導体チップ7は入出力端子3
に半田付けされている。The input / output terminal 44 has a U-shaped portion that is positioned horizontally with respect to the metal base and soldered on the insulating layer 2, and has a portion whose tip rises vertically with respect to the metal base 1. are doing. The second power semiconductor chip 8 is soldered to the other surface of the input / output terminal 44 which is located horizontally, and the end of the portion of the input / output terminal 44 which rises vertically to the metal base 1 has a narrow terminal width. I have. An input / output terminal 45 is soldered on the second power semiconductor chip 8, and the first power semiconductor chip 7 is connected to the input / output terminal 3.
Soldered.
【0004】第1の電力半導体チップ7と第2の電力半
導体チップ8の間には金属ブリッジ46が接続されてい
る。この金属ブリッジ46の第2の電力半導体チップ8
側には穴51が設けられ,出力端子44の垂直に立ち上
がり端子幅が細くなっている先端52が金属ブリッジ4
6の穴51にはめ込まれて,半田付けで固定される。な
お,金属ブリッジ46の穴51が設けられている側の反
対側は電力半導体チップ7に半田付けされ固定されてい
る。[0004] A metal bridge 46 is connected between the first power semiconductor chip 7 and the second power semiconductor chip 8. The second power semiconductor chip 8 of the metal bridge 46
A hole 51 is provided on the side of the metal bridge 4 and the output terminal 44 has a vertically rising terminal 52 having a narrow terminal width.
6 and is fixed by soldering. The side of the metal bridge 46 opposite to the side where the holes 51 are provided is soldered and fixed to the power semiconductor chip 7.
【0005】[0005]
【発明が解決しようとする課題】ところが,入出力端子
44と金属ブリッジ46を接続するための半田付けは,
金属ブリッジ46及び入出力端子44の厚みの接触面積
しか得ることができず,電力半導体チップ7と前記電力
半導体チップ8の間の電気抵抗が大きくなる。さらに,
入出力端子44と金属ブリッジ46との半田付けは,接
続点が空中に浮いているために手作業で半田付けする必
要があるので組立工数が多くなるという問題がある。However, soldering for connecting the input / output terminal 44 and the metal bridge 46 requires
Only the contact area of the thickness of the metal bridge 46 and the input / output terminal 44 can be obtained, and the electric resistance between the power semiconductor chip 7 and the power semiconductor chip 8 increases. further,
The soldering between the input / output terminal 44 and the metal bridge 46 has a problem that the number of assembling steps is increased because the connection point is floating in the air and must be manually soldered.
【0006】[0006]
【課題を解決するための手段】第1の発明の電力半導体
装置は,金属ベースと,前記金属ベース上に半田付けさ
れる絶縁層と,前記絶縁層上に設けられる第1の入出力
端子と,コの字形をし金属ベースに対して水平に位置す
る部分が前記絶縁層上に半田付けされる第2の入出力端
子と,両入出力端子上にそれぞれ搭載され半田付けされ
る第1及び第2の電力半導体チップと,両電力半導体チ
ップ間を電気的に接続する金属ブリッジとを具備する電
力半導体装置において,前記第2の入出力端子が,前記
金属ベースに対して垂直に立ち上がり,その先端が前記
金属ブリッジに勘合する第1の突起を有する端子であ
り,前記金属ブリッジが,前記第2の入出力端子側が前
記突起に勘合する第1の勘合穴を有するとともに前記勘
合穴から垂直に下がる金属ブリッジであり,前記金属ベ
ースに対して垂直に立ち上がる前記第2の端子と前記金
属ベースに対して垂直に下がる金属ブリッジとがわずか
な間隔でもって並行に配置されているものである。すな
わち,片方の端子を曲げて端子同士が平行になる部分を
作ることによって端子間の電気抵抗を下げる。According to a first aspect of the present invention, there is provided a power semiconductor device, comprising: a metal base; an insulating layer soldered on the metal base; a first input / output terminal provided on the insulating layer; A second input / output terminal having a U-shape and positioned horizontally with respect to the metal base is soldered on the insulating layer; and a first and a second input / output terminal mounted and soldered on the two input / output terminals, respectively. In a power semiconductor device comprising a second power semiconductor chip and a metal bridge for electrically connecting the two power semiconductor chips, the second input / output terminal rises perpendicularly to the metal base, The tip is a terminal having a first projection that fits into the metal bridge, and the metal bridge has a first fitting hole on the second input / output terminal side that fits into the projection, and is perpendicular to the fitting hole. Below A metal bridge, in which a metal bridge down perpendicular to the second terminal and said metal base which rises perpendicularly to the metal base is disposed in parallel with a slight spacing. That is, the electric resistance between the terminals is reduced by bending one of the terminals to form a portion where the terminals are parallel to each other.
【0007】[0007]
【発明を解決するための手段】第2の発明の電力半導体
装置は,金属ベースと,前記金属ベース上に半田付けさ
れる絶縁層と,前記絶縁層上に設けられる第1の入出力
端子と,コの字形をし金属ベースに対して水平に位置す
る部分が前記絶縁層上に半田付けされる第2の入出力端
子と,両入出力端子上にそれぞれ搭載され半田付けされ
る第1及び第2の電力半導体チップと,両電力半導体チ
ップ間を電気的に接続する金属ブリッジとを具備する電
力半導体装置において,前記第2の入出力端子が,前記
金属ベースに対して垂直に立ち上がり,その立ち上がり
前に前記金属ブリッジに勘合する第2の勘合穴を有し,
かつその先端が前記金属ブリッジに勘合する第1の突起
を有する端子であり,前記金属ブリッジが,第2の入出
力端子側が前記第1の突起に勘合する第1の勘合穴を有
し,かつ前記第1の勘合穴から垂直に下がり,その先端
が第2の勘合穴に勘合する第2の突起を有する金属ブリ
ッジであり,前記金属ベースに対して垂直に立ち上がる
前記第2の端子と前記金属ベースに対して垂直に下がる
金属ブリッジとがわずかな間隔でもって並行に配置され
ているものである。すなわち前記第1の端子と前記第2
の端子の間の接続部分の接触面積を広くする。According to a second aspect of the present invention, there is provided a power semiconductor device comprising: a metal base; an insulating layer soldered on the metal base; a first input / output terminal provided on the insulating layer; A second input / output terminal having a U-shape and positioned horizontally with respect to the metal base is soldered on the insulating layer; and a first and a second input / output terminal mounted and soldered on the two input / output terminals, respectively. In a power semiconductor device comprising a second power semiconductor chip and a metal bridge for electrically connecting the two power semiconductor chips, the second input / output terminal rises perpendicularly to the metal base, Having a second fitting hole for fitting to the metal bridge before rising;
And the tip is a terminal having a first projection that fits into the metal bridge, and the metal bridge has a first fitting hole on a second input / output terminal side that fits into the first projection, and A metal bridge having a second protrusion which is vertically lowered from the first fitting hole and whose tip is fitted to the second fitting hole, and which rises perpendicularly to the metal base and the second terminal; Metal bridges that run perpendicular to the base are arranged in parallel with a slight spacing. That is, the first terminal and the second terminal
The contact area of the connection portion between the terminals is increased.
【0008】[0008]
【発明の実施の形態】第1の発明の実施の形態を図1と
図2を参照して説明する。図1の電力半導体装置は,金
属ベース1と,金属ベース上に半田付けされる絶縁層
2,2aと,絶縁層2,2a上に設けられるL字形をし
た入出力端子3と,コの字形をし,金属ベース1に対し
て水平に位置する部分が絶縁層2の上に半田付けされる
入出力端子4と,入出力端子3,4上にそれぞれ搭載さ
れ半田付けされる電力半導体チップ7,8と,電力半導
体チップ7と8間を電気的に接続する金属ブリッジ6
と,電力半導体チップ8の上に設けられた入出力端子5
を具備している。図1において,点線で囲んだ入出力端
子4と金属ブリッジ6との半田付け箇所の拡大図を図2
に示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to FIGS. The power semiconductor device shown in FIG. 1 includes a metal base 1, insulating layers 2 and 2a soldered on the metal base, L-shaped input / output terminals 3 provided on the insulating layers 2 and 2a, and a U-shape. An input / output terminal 4 having a portion positioned horizontally with respect to the metal base 1 is soldered on the insulating layer 2 and a power semiconductor chip 7 mounted and soldered on the input / output terminals 3 and 4, respectively. , 8 and a metal bridge 6 for electrically connecting between the power semiconductor chips 7 and 8
And an input / output terminal 5 provided on the power semiconductor chip 8.
Is provided. FIG. 2 is an enlarged view of a soldering portion between the input / output terminal 4 and the metal bridge 6 surrounded by a dotted line in FIG.
Shown in
【0009】図2に示すように半田付け箇所では入出力
端子4は金属ベース1に対し垂直に立ち上がり,その入
出力端子4の先端は金属ブリッジ6と勘合するための突
起22を有している。一方の金属ブリッジ6には突起2
2と係り合う勘合穴21を有している。この金属ブリッ
ジ6の先端は勘合穴から折り曲がって垂直に下がってい
る。従って,入出力端子4の立ち上がり部分と金属ブリ
ッジ6から垂直に下がる部分が1mm以下のわずかな間
隔をもって並行に配置され,入出力端子4の突起22は
金属ブリッジ6の勘合穴21に勘合される。勘合した入
出力端子4の突起22と金属ブリッジの間の勘合穴21
に半田を付けて固定する。この半田付けの時に入出力端
子4と金属ブリッジ6が並行に重なっている部分に毛細
管効果により半田が流れ込んで,入出力端子4と金属ブ
リッジ6の間の接続がなされる。As shown in FIG. 2, the input / output terminal 4 rises perpendicularly to the metal base 1 at the soldering point, and the tip of the input / output terminal 4 has a projection 22 for fitting with the metal bridge 6. . One metal bridge 6 has a protrusion 2
It has a fitting hole 21 that engages with the second. The tip of this metal bridge 6 is bent from the fitting hole and vertically lowered. Therefore, the rising portion of the input / output terminal 4 and the portion vertically descending from the metal bridge 6 are arranged in parallel with a small interval of 1 mm or less, and the projection 22 of the input / output terminal 4 is fitted into the fitting hole 21 of the metal bridge 6. . The fitting hole 21 between the projection 22 of the fitted input / output terminal 4 and the metal bridge
And fix it with solder. At the time of this soldering, the solder flows into the portion where the input / output terminal 4 and the metal bridge 6 overlap in parallel by the capillary effect, and the connection between the input / output terminal 4 and the metal bridge 6 is made.
【0010】第2の発明の実施の形態を図3と,図3に
おいて破線で囲んだ箇所の拡大図を示す図4を参照して
説明する。図3の電力半導体装置は,金属ベース1と,
金属ベース上に設けられた絶縁層2,2aと,この絶縁
層2,2a上に設けられた入出力端子3,34と,電力
半導体チップ7,8と,金属ブリッジ36とで構成す
る。図1の電力半導体装置と異なる点は,図1の金属ブ
リッジ6から垂直に下がる部分が,図3及び図4に示す
ように長く伸ばされ,先端が突起35を形成させてい
る。さらに,図1の金属ベース1に対して水平に位置す
る入出力端子4の部分が,図4に示すように突起35に
係り合う勘合穴33が設けられた点にある。従って,突
起32と勘合穴31との勘合と,突起35と勘合穴33
との勘合と2点で行われている。そして,入出力端子3
4の垂直に立ち上がる部分と,金属ブリッジ36の立ち
下がる部分との間は1mm以下のわずかな間隔をもって
並行に配置されている。An embodiment of the second invention will be described with reference to FIG. 3 and FIG. 4 showing an enlarged view of a portion surrounded by a broken line in FIG. The power semiconductor device of FIG.
It comprises insulating layers 2, 2a provided on a metal base, input / output terminals 3, 34 provided on the insulating layers 2, 2a, power semiconductor chips 7, 8, and a metal bridge 36. The difference from the power semiconductor device of FIG. 1 is that the portion vertically descending from the metal bridge 6 of FIG. 1 is elongated as shown in FIGS. 3 and 4, and the tip forms a projection 35. Further, the portion of the input / output terminal 4 located horizontally with respect to the metal base 1 in FIG. 1 is that a fitting hole 33 that engages with the projection 35 is provided as shown in FIG. Therefore, the fitting between the projection 32 and the fitting hole 31 and the fitting between the projection 35 and the fitting hole 33 are performed.
And two points. And the input / output terminal 3
4 and the falling portion of the metal bridge 36 are arranged in parallel with a slight gap of 1 mm or less.
【0011】電力半導体チップ7,8を金属ベースに半
田付けする際には,勘合穴33から半田が毛細管効果に
より伝わり,入出力端子34と金属ブリッジ36の間に
も半田が伝わり半田付けすることができる。When the power semiconductor chips 7 and 8 are soldered to the metal base, the solder is transmitted from the fitting hole 33 by a capillary effect, and the solder is also transmitted between the input / output terminal 34 and the metal bridge 36 for soldering. Can be.
【0012】[0012]
【発明の効果】入出力端子4を金属ブリッジ6又は入出
力端子34を金属ブリッジ36に勘合させて半田により
接続箇所の接触面積を広くすることによって接触抵抗を
低減させることができ,電力半導体素子7と8の間の電
気抵抗を下げることができる。さらに,電力半導体素子
を半田付けする際に入出力端子34と金属ブリッジ36
とが半田付けされて,手作業の半田の工程が必要でなく
なる。According to the present invention, the contact resistance can be reduced by fitting the input / output terminal 4 to the metal bridge 6 or the metal input / output terminal 34 to the metal bridge 36 and increasing the contact area of the connection portion by soldering. The electrical resistance between 7 and 8 can be reduced. Further, when soldering the power semiconductor element, the input / output terminal 34 and the metal bridge 36
Are soldered, eliminating the need for a manual soldering process.
【図1】第1の発明の実施の形態を示す電力半導体装置
の断面図である。FIG. 1 is a sectional view of a power semiconductor device according to an embodiment of the first invention.
【図2】図1の部分拡大図である。FIG. 2 is a partially enlarged view of FIG.
【図3】第2の発明の実施の形態を示す電力半導体装置
の断面図である。FIG. 3 is a sectional view of a power semiconductor device according to an embodiment of the second invention.
【図4】図3の部分拡大図である。FIG. 4 is a partially enlarged view of FIG. 3;
【図5】従来の電力半導体装置の断面図である。FIG. 5 is a sectional view of a conventional power semiconductor device.
【図6】図5の部分拡大図である。FIG. 6 is a partially enlarged view of FIG. 5;
1 金属ベース 2 絶縁層 3,4,5,34,44,45 入出力端子 6,36,46 金属ブリッジ 7,8 電力半導体チップ 21,31,33 勘合穴 22,32,35 突起 DESCRIPTION OF SYMBOLS 1 Metal base 2 Insulating layer 3,4,5,34,44,45 Input / output terminal 6,36,46 Metal bridge 7,8 Power semiconductor chip 21,31,33 Fitting hole 22,32,35 Projection
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 25/00 - 25/18 ────────────────────────────────────────────────── ─── Continued on front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 25/00-25/18
Claims (2)
付けされる絶縁層と,前記絶縁層上に設けられる第1の
入出力端子と,コの字形をし金属ベースに対して水平に
位置する部分が前記絶縁層上に半田付けされる第2の入
出力端子と,両入出力端子上にそれぞれ搭載されて半田
付けされる第1及び第2の電力半導体チップと,両電力
半導体チップ間を電気的に接続する金属ブリッジとを具
備する電力半導体装置において,前記第2の入出力端子
が,前記金属ベースに対して垂直に立ち上がり,その先
端が前記金属ブリッジに勘合する第1の突起を有する端
子であり,前記金属ブリッジが,前記第2の入出力端子
側が前記突起に勘合する第1の勘合穴を有するとともに
前記勘合穴から垂直に下がる金属ブリッジであり,前記
金属ベースに対して垂直に立ち上がる前記第2の端子と
前記金属ベースに対して垂直に下がる金属ブリッジとが
わずかな間隔でもって並行に配置されていることを特徴
とする電力半導体装置。1. A metal base, an insulating layer to be soldered on the metal base, a first input / output terminal provided on the insulating layer, and a U-shaped and horizontally positioned with respect to the metal base. A second input / output terminal whose part to be soldered is soldered on the insulating layer; first and second power semiconductor chips mounted and soldered on the two input / output terminals, respectively; And a metal bridge for electrically connecting the metal base, the second input / output terminal rises vertically with respect to the metal base, and a tip of the first projection fits into the metal bridge. The metal bridge is a metal bridge having a first fitting hole in which the second input / output terminal side fits with the projection and vertically descending from the fitting hole. The power semiconductor device, wherein the second terminal that rises vertically and a metal bridge that falls vertically with respect to the metal base are arranged in parallel at a slight interval.
付けされる絶縁層と,前記絶縁層上に設けられる第1の
入出力端子と,コの字形をし金属ベースに対して水平に
位置する部分が前記絶縁層上に半田付けされる第2の入
出力端子と,両入出力端子上にそれぞれ搭載され半田付
けされる第1及び第2の電力半導体チップと,両電力半
導体チップ間を電気的に接続する金属ブリッジとを具備
する電力半導体装置において,前記第2の入出力端子
が,前記金属ベースに対して垂直に立ち上がり,その立
ち上がり前に前記金属ブリッジに勘合する第2の勘合穴
を有し,かつその先端が前記金属ブリッジに勘合する第
1の突起を有する端子であり,前記金属ブリッジが,第
2の入出力端子側が前記第1の突起に勘合する第1の勘
合穴を有し,かつ前記第1の勘合穴から垂直に下がり,
その先端が第2の勘合穴に勘合する第2の突起を有する
金属ブリッジであり,前記金属ベースに対して垂直に立
ち上がる前記第2の端子と前記金属ベースに対して垂直
に下がる金属ブリッジとがわずかな間隔でもって並行に
配置されていることを特徴とする電力半導体装置。2. A metal base, an insulating layer to be soldered on the metal base, a first input / output terminal provided on the insulating layer, and a U-shape which is positioned horizontally with respect to the metal base. A second input / output terminal whose part to be soldered is soldered on the insulating layer; first and second power semiconductor chips mounted and soldered on the two input / output terminals, respectively; In a power semiconductor device comprising a metal bridge electrically connected to the metal base, the second input / output terminal rises perpendicularly to the metal base, and a second fitting hole fits into the metal bridge before the rise. And a terminal having a first projection fitted at the tip thereof to the metal bridge, wherein the metal bridge has a first fitting hole at a second input / output terminal side fitted to the first projection. Have and said Down from 1 of the fitting hole in the vertical,
The tip is a metal bridge having a second projection that fits into a second fitting hole, and the second terminal that rises vertically with respect to the metal base and the metal bridge that falls vertically with respect to the metal base. A power semiconductor device, wherein the power semiconductor devices are arranged in parallel at a slight interval.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32696497A JP3349416B2 (en) | 1997-11-11 | 1997-11-11 | Power semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32696497A JP3349416B2 (en) | 1997-11-11 | 1997-11-11 | Power semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11145377A JPH11145377A (en) | 1999-05-28 |
JP3349416B2 true JP3349416B2 (en) | 2002-11-25 |
Family
ID=18193767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32696497A Expired - Fee Related JP3349416B2 (en) | 1997-11-11 | 1997-11-11 | Power semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3349416B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10352671A1 (en) | 2003-11-11 | 2005-06-23 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | power module |
JP5218009B2 (en) * | 2008-12-16 | 2013-06-26 | 富士電機株式会社 | Semiconductor device |
-
1997
- 1997-11-11 JP JP32696497A patent/JP3349416B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH11145377A (en) | 1999-05-28 |
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