JP3343618B2 - Terminal uninterrupted online system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal uninterrupted online system, and more particularly to a terminal uninterrupted online system which does not interrupt a session with a terminal even when a host failure or a front-end processor failure occurs.

[0002]

2. Description of the Related Art An on-line system includes a host for performing general business processing and a front-end processor (hereinafter referred to as FEP) for executing host communication processing, for high performance and high reliability. , And a terminal is connected to the FEP.

As a conventional online system, for example, “Transactions of Information Processing Society of Japan, Vol. 30, No. 2, (198
9), page 214 to page 225 ". In this online system, the host has a configuration in which one spare host is provided for every two execution hosts, and the FEP has a configuration in which one spare FEP is provided for a plurality of active FEPs. The terminal transmits the message to the execution host via the FEP, and the execution host processes the message. When a failure occurs in the execution host, the spare host starts takeover processing of the execution host. FEP
Holds the message to be transferred to the host until the takeover process ends. When the takeover processing on the host ends, the FE
P collectively transfers the held messages to the spare host. Then, the spare host executes the processing of the received message.

[0004]

In the above-mentioned conventional online system, the host does not manage the state of all messages, so that even if a failure occurs, it is impossible to determine at which point the failure has occurred. Interrupt some sessions. Further, FEP does not make itself redundant, so FEP
When an EP failure occurs, the message received from the terminal is lost,
Requests the terminal to resend the message. As a result, when a host failure or an FEP failure occurs, there is a problem that a session between the host, the FEP, and the terminal is interrupted.

An object of the present invention is to provide a terminal uninterrupted online system capable of preventing interruption of a session even when a host failure or an FEP failure occurs.

[0006]

In order to achieve the above object, the present invention provides a hot standby system in which an execution host and a spare host share a disk device by connecting a terminal to a front-end processor and a high-speed LAN. In an online system connected via
It manages the state of all messages, and the front-end processor has a dual configuration of an active system and a standby system. The active system and the standby system have a line adapter connected to a line to a terminal and a LAN adapter connected to a high-speed LAN. The line adapter is provided with a storage device for holding a received message from the terminal, and when receiving a message from the terminal, the terminal is connected to both the working and standby line adapters and these storage devices are connected. The LAN adapter is provided with a storage device for holding a transmission message to the execution host. When the host is stopped, the message to be transferred to the host is stored in both the active and standby LAN adapters. held in the apparatus, furthermore, full
The redundant shared memory is set in the front-end processor.
And the shared memory is processed by the front-end processor.
The time stamp of the message being processed and the time of the message that has finished processing
Store the stamp and the time stamp of the message to be transferred to the host
That provides a terminal uninterrupted online system, characterized in that.

[0007]

The host has a hot standby configuration in which the execution host and the spare host share a disk device, and manages the status of all messages. Therefore, even if a failure occurs in the execution host, the spare host can restart all the messages being executed.

[0008] The FEP has a dual configuration of an active system and a standby system, each of which is provided with a line adapter and a LAN adapter.
The message received from the terminal is stored in the storage device of the line adapter, and the message to be transferred to the host is stored in the storage device of the LAN adapter. Therefore, even if a failure occurs in the FEP, it is possible to prevent loss of the message from the terminal and the message to be transferred to the host. Also, the shared memory is added to the front-end processor.
And a shared memory with a front-end processor
The time stamp of the message being processed and the message for which processing has been completed
And the time stamp of the message to be transferred to the host.
To pay. As a result, the duplicated FEP can be coordinated appropriately.
Can be made. In addition, the shared memory is also duplicated,
Be prepared for harm.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a terminal uninterrupted online system (1000) according to an embodiment of the present invention will be described. Note that the present invention is not limited by this.

As shown in FIG. 1, a terminal uninterrupted online system (1000) according to the present invention comprises a host computer (1), a high-speed LAN (3), an FEP (4), a line (5) and a large number of terminals (6). ). The host computer (1) includes an execution host (1-0) and a spare host (1-1). Disk device (2) shared by the execution host (1-0) and the spare host (1-1)
Has a duplex configuration for high reliability.

FIG. 2 is a configuration diagram of the host computer (1). The execution host (1-0) and the spare host (1-
1) is a processor IP (10-0, 10-
1), memory MS (11-0, 11-1), system controller SC (12-0, 12-1), host I / O processor HIOP (13-0, 13-1), channel CH
(14-0, 14-1), a host LAN controller HLANC (15-0, 15-1) and a host disk controller HDKC (16-0, 16-1).

The execution host (1-0) and the spare host (1-
1) is connected by an inter-channel coupling device CTCA (17). Timers (18-0, 18-1) are provided in host I / O processors HIOP (13-0, 13-1), respectively. In order for the spare host (1-1) to take over the processing of the execution host (1-0), the host checkpoint data and the journal of the host indicating the I / O history are stored in the disk device (2-0, 2-1). ).

FIG. 3 is a configuration diagram of the FEP (4). F
The EP (4) has a working system (30-0) and a standby system (30-).
1), shared memory (50-0, 50-1), time stamp timer (51), line switching device (52), system bus (5
3) and disk devices (54-0, 54-1). The active system (30-0) and the standby system (30-1) are connected by a bus, and are configured by a hot standby system.

The working system (30-0) has a processor (31).
-0), memory (32-0), IOP (33-0), bus extender (34-0), line adapter (35-
0), a LAN adapter (36-0) and a disk controller (37-0). The standby system (30-1)
Processor (31-1), memory (32-1), IOP
(33-1), a bus extender (34-1), a line adapter (35-1), a LAN adapter (36-1), and a disk controller (37-1).

The line adapters (35-0, 35-1)
It has a reception queue (40-0, 40-1) and holds a message received from the terminal (6). Also, it has a transmission queue (41-0, 41-1) and holds a message to be transmitted to the terminal (6). LAN adapter (36-0, 36)
-1) has a reception queue (42-0, 42-1) and holds a message received from the host (1). Also,
It has a transmission queue (43-0, 43-1) and holds messages to be transmitted to the host.

Disk controller (37-0, 37-1)
Holds write data or read data for the disk device (54-0, 54-1), and stores the data in the disk device (54-0, 54-1).
0, 54-1).

When receiving a message from the terminal (6), the line switching device (52) operates the terminal (6) so that the working system (30-0) and the standby system (30-1) can simultaneously receive the message. Is connected to the working system (30-0) and the standby system (30-1). When transmitting a message to the terminal (6), the current system (3
The terminal (6) is connected to the active system (30-0) so that a message can be transmitted from 0-0).

The shared memories (50-0, 50-1) store the same contents as a duplicated configuration, while preventing a system failure even if a failure occurs. Similarly, the disk devices (54-0, 54-1) store the same contents in a duplex configuration so that the system does not go down even if a failure occurs.

The time stamp timer (51) is used to add a time stamp to a message received from the terminal (6). In the shared memory (50-0, 50-1), in order to manage the message being processed, the message area (60-
0, 60-1) and a message area (61-
0, 61-1). Further, in order to manage the processed message, the processed message area (62-0, 6
2-1) is provided. Further, a takeover information area (63-0, 63-1) is provided to manage checkpoint data for takeover.

In the FEP (4), the active line adapter (35-0) and the standby line adapter (35-1)
Holds the received message (70) from the terminal (6), and the active LAN adapter (36-0) and the standby LAN adapter (36-1) transmit the transmitted message (73) to the host (1). Hold. Thus, even if a failure occurs in either the FEP active system (30-0) or the FEP standby system (30-1), the message is not lost. Further, during execution of the message processing, the time of the write processing to the disk device (54-0, 54-1) is taken as the point of the takeover of the processing, and the processor (31-0, 31) is taken.
-1) registers, I / O wait factors and their registers,
The information of the register of the message in the ready state is written to the shared memory (50-0, 50-1) as checkpoint data. As a result, even if a failure occurs in the FEP active system (30-0), the standby system (30-1) allows the shared memory (5-5) to operate.
By referring to the checkpoint data stored in (0-0, 50-1), it is possible to restart the execution of processing of all messages from the latest checkpoint.

FIG. 4 is a diagram showing an outline of the processing of the system (1000). During execution of the message processing, the execution host (1-0) stores the host checkpoint data indicating the message management information, the task information and the I / O information, and the host journal indicating the I / O history in the disk device. It is stored in (2) (process 100).

When a failure occurs in the execution host (1-0), the spare host (1-1) refers to the disk device (2) to read the host checkpoint data and the host journal (process 102). The communication state of the file contents and the message is returned at the time of the checkpoint, and is inherited from the message processing at the time of the checkpoint. FEP (4)
If messages from the terminal (6) to the host (1) are received during the switching from the execution host (1-0) to the spare host (1-1), the messages are transferred to the LAN adapters (36-0, 36).
-1) (process 103).

From the execution host (1-0) to the spare host (1
When the switching to -1) is completed, the FEP (4) collectively transfers the held messages to the host (1) (Process 1).
04). The spare host (1-1) receives the message and executes the processing.

FIG. 5 is a diagram showing an outline of the processing of the FEP (4). The line adapter (35-0, 35-1) receives the message body from the terminal (6) (process 120), attaches the time stamp, and stores it in the reception queue (40-0, 40-1). (Step 121). FIG. 6 shows a message (7) obtained by adding a time stamp (72) to the message body (71) received from the terminal (6).
0).

The active processor (31-0) extracts the message (70) from the reception queue (40-0) of the line adapter (35-0) (process 122), and the host (1)
It is determined whether the message is to be transferred to the FEP or to be processed by the FEP (4).

If the FEP (4) determines that the message is to be processed, the active processor (31-0) sends the message body (7
1) is written into the memory (32-0) (process 123),
A process corresponding to the message body (71) is executed. Further, the time stamp (72) is stored in the F of the shared memory (50-0, 50-1).
It is written into the message area (60-0, 60-1) during the execution of the EP process (process 124). When the processing corresponding to the message body (71) is completed, the transmission message to the terminal (6) is sent to the transmission queue (41-0) of the active line adapter (35-0).
(Process 125). Further, the time stamp (72) of the completed message is stored in the shared memory (50-0, 50-1).
Is written in the processed message area (62-0, 62-1).

If the active processor (31-0) determines that the message is to be transferred to the host (1), the active processor (31-0) places the message (70) in the transmission queue (43-0) of the LAN adapter (36-0). It is stored (process 129). In addition, the time stamp (7
2) is written into the message area (61-0, 61-1) of the shared memory (50-0, 50-1) during the execution of the host process (process 128).

The LAN adapter (36-0) receives the message body sent from the host (1) which has completed the message processing (step 130), attaches a time stamp, and attaches a time stamp to the message. 0). FIG. 7 shows a format of a message (73) in which a time stamp (72) is added to a message body (74) received from the host (1). Active processor (3
1-0) retrieves the message (73) from the reception queue (42-0) of the LAN adapter (36-0) and transfers the message body (74) to the transmission queue of the line adapter (35-0). (41-0) (process 131).

The line adapter (35-0) transmits the message stored in the transmission queue (41-0) to the terminal (6) (process 126). As shown in FIG. 8, the transmission message (75) to the terminal (6) is composed of only the message body (76).

On the other hand, the standby processor (31-1)
At regular intervals, the time stamp (72) is read from the message area (61-0, 61-1) during the host processing of the shared memory (50-0, 50-1) (processing 135), and the corresponding message (70) is read. ) Is stored in the transmission queue (43-1) of the LAN adapter (36-1) (process 136). Further, the process-executed message area (62-0, 62-1) of the shared memory (50-0, 50-1) is read out at regular intervals (process 133), and the time stamp (72) at which the process is completed. ), And sends the corresponding message (70) to the line adapter (3).
5-1) is removed from the reception queue (40-1) and the transmission queue (43-1) of the LAN adapter (36-1) (process 134).

Next, the registers used in the host (1) will be described with reference to FIGS. FIG.
This is a spare host alive register (20-0) of the execution host (1-0). The execution host (1-0)
An alive message is received from the spare host (1-1), and whether it is normal or not is monitored. Alive for spare host
The e register (20-0) uses only bit 0, and if bit 0 is "1", an alive message has been transmitted,
If it is “0”, it means that the alive message has not been transmitted.
FIG. 10 shows an example of the execution host “a” of the spare host (1-1).
live register (20-1). Spare host (1
-1) receives an alive message from the execution host (1-0) and monitors whether it is normal. The execution host alive register (20-1) uses only the bit 0. If the bit 0 is "1", the alive message has been transmitted, and if the bit 0 is "0", the alive message has not been transmitted.

FIG. 11 shows the F of the execution host (1-0).
The alive register for EP (21-0) is shown. The execution host (1-0) receives the alive message from the FEP (4) and monitors whether it is normal. The FEP register (21-0) uses only bit 0 and bit 0
Is "1", an alive message has been sent, "0"
Then, it means that the alive message has not been transmitted. FIG.
Indicates an FEP alive register (21-1) of the spare host (1-1). The spare host (1-1)
An alive message is received from the FEP (4), and whether the message is normal is monitored. Register for FEP (21-1)
Uses only bit 0, and if bit 0 is "1", al
When the live message has been transmitted, “0” means that the live message has not been transmitted.

FIG. 13 shows the received message counter (22-) of the execution host (1-0) and the spare host (1-1).
0, 22-1). The reception message counter (22-0) of the execution host (1) indicates that the execution host (1-0) has FEP.
Indicates the number of messages received from (4) and stored in the queue. The reception message counter (22-1) of the spare host (1-1) is not normally used, and the execution host (1-0)
Is used when a failure occurs in the server and switching to the spare host (1-1) is performed. Received message counter (22-0, 22-
1) has an 8-bit configuration.

FIG. 14 shows the congestion reference value registers (23-) of the execution host (1-0) and the spare host (1-1).
0,23-1). A congestion reference value is set in the congestion reference value register (23-0) of the execution host (1-0) when the system is started. If the number of received messages exceeds the congestion reference value, it is determined that the state is congested. Spare host (1-
The congestion reference value register (23-1) of 1) is not normally used, and is used when a failure occurs in the execution host (1-0) and the system is switched to the spare host (1-1).

FIG. 15 shows a congestion release reference value register (2) of the execution host (1-0) and the spare host (1-1).
4-0, 24-1). The congestion release reference value is set in the congestion release reference value register (24-0) of the execution host (1-0) when the system is started. During the congestion state, if the number of received messages falls below the congestion release reference value, it is determined that the congestion is released. The congestion release reference value register (24-1) of the spare host (1-1) is not normally used, and when a failure occurs in the execution host (1-0) and switching to the spare host (1-1) is performed. use.

The above alive register (20-0,2)
0-1, 21-0, 21-1), received message counter (2
2-0, 22-1), a congestion reference value register (23-0,
23-1), a congestion release reference value register (24-0, 24)
-1) is a LAN controller HLANC (15-0,
15-1).

FIG. 16 is a state transition diagram of FEP (4). The working state (150) is a state in which processing is being executed normally including all line-specific parts. Semi-active state (15
1) is a state in which a part of the line-specific part has a failure, but the failure part is closed and the processing is being executed. Standby state (152)
Indicates that the message is being received in synchronization with the active system,
When a failure occurs in the active system, the process can be taken over immediately. The offline state (153) is a state where the system is disconnected from the system due to occurrence of a failure or maintenance. The restoration state (154) is a state of being recovered from a failure or a state of starting up.

In the active state (150), if a line failure occurs, the active state (150) is changed to the quasi-active state (15).
1) (state transition 155), and when a system failure occurs, transition to the offline state (153) (state transition 15).
7). In the quasi-active state (151), when recovery from the line failure occurs, the state transits to the active state (150) (state transition 15).
6) If a new line part failure occurs, if possible, the line failure part is closed and stays in the semi-active state (151),
If impossible, the state transits to the offline state (153) (state transition 160). When a system failure occurs, the state transits to the offline state (153) (state transition 160). In the standby state (152), when the active system (30-0) transits to the offline state (153), it transits to the active state (150) (state transition 158), and when a system failure or a line part failure occurs, the offline state (150). 153) (state transition 159). When the restoration is completed in the offline state (153), the state transits to the restoration state (154) (state transition 16).
4). In the restoration state (154), when the message (72) is received, the state transits to the standby state (152) (state transition 162), and when a system failure or a line part failure occurs, the state transits to the offline state (153) ( State transition 16
3).

FIG. 17 shows the shared memory (5) of the FEP (4).
It is a mode transition diagram of (0-0, 50-1). The double mode (170) uses two shared memories (50-0, 50-
1) is a normal state. Writing is performed on the shared memory (50-
0, 50-1), and reading is performed from one of the shared memories (50-0). Single mode (171)
Is a state where a failure has occurred in one of the shared memories (50-0, 50-1). Writing and reading are performed to the normal shared memory. The quasi-double mode (172) is a state where one of the faulty shared memories has recovered from the fault and the contents of the normal shared memory are being copied. Writing is performed to both of the shared memories (50-0, 50-1), and reading is performed from the normal shared memory. Repair mode (173)
Is a state in which both of the shared memories (50-0, 50-1) are recovering from a failure or are starting up. The down mode (174) is a state where both shared memories (50-0, 50-1) cannot be used due to a failure or maintenance.

In the double mode (170), if a failure occurs in one of the shared memories, the single mode (17)
The state transits to 1) (mode transition 175). In the single mode (171), if a failure occurs in the normal shared memory, the state transits to the down mode (170) (mode transition 1).
80). When the failed shared memory is restored, the mode is changed to the quasi-double mode (172) (mode transition 176). In the quasi-double mode (172), when the contents of the normal shared memory have been copied to the restored shared memory, the mode is changed to the double mode (170) (mode transition 177). Further, when a failure occurs in the normal shared memory, the state transits to the down mode (174) (mode transition 1).
81). When a failure occurs again in the repaired shared memory, the state transits to the single mode (171) (mode transition 179). When both of the shared memories (50-0, 50-1) are restored in the down mode (174), the state transits to the restoration mode (173) (mode transition 178). In the repair mode (173), both shared memories (50-
0,50-1), the double mode (1
70) (mode transition 182).

FIG. 18 shows the shared memory (5) of the FEP (4).
FIG. 2 is an explanatory diagram of an exclusive control method of (0-0, 50-1). The shared memory (50-0, 50-1) includes an active system monitoring area (200-0, 200-1), a standby system monitoring area (201-0, 201-1) and a takeover information area (202-0). , 202-1). The FEP working system (30-0) has a working system monitoring area (200-0, 2).
00-1) is read / write enabled (210). The standby monitoring area (201-0, 201-1) can be read (211). Also, the takeover information area (202-0, 202-1) can be read / written (212). The FEP standby system (30-1) can read the active system monitoring area (200-0, 200-1) (21
3). In addition, the monitoring area for the standby system (201-0,
201-1) can be read / written (214). Further, the takeover management area (202-0, 202-1) can be read (215). With such a configuration, the active system (30-0) and the standby system (30-1) can exclusively control the shared memories (50-0, 50-1). The message area during execution of the FEP process (60-
0, 60-1), message area during host processing (61-
0, 61-1), the processed message area (62-0, 6)
2-1) and takeover information area (63-0, 63-)
1) is a takeover management area (202-0, 202-
Provided in 1).

FIG. 19 is a detailed circuit diagram of the FEP (4). Since the active system (30-0) and the standby system (30-1) have the same configuration, the standby system (30-1) is simplified in FIG. In addition, (5 **) in the active system (30-0)
-0,6 **-0) is (5 **-
1,6 **-1).

The processors (31-0, 31-1) are, for example, 68000 microprocessors. The internal registers of the processors (31-0, 31-1) are data registers DR0 to DR7 (500-0 to 507-0,500).
-1 to 507-1), address registers AR0 to AR6
(510-0 to 516-0, 510-1 to 516-
1), stack pointer AR7 (520-0, 520-
1), status register SR (521-0, 521-
1), the program counter PC (522-0, 522-
1).

The signal lines of the processors (31-0, 31-1) are connected to the data lines D0 to D7 (540-0, 540-
1), address lines A1 to A23 (541-0, 541-
1), interrupt line (processor L0-2) (543-0)
545-0, 543-1 to 545-1) and W / R lines (546-0, 546-1). W / R line (5
46-0, 546-1), when "H" is a read cycle, and when "L" is a write cycle.

The IOP (33-0, 33-1) includes an IO processor (570-0, 570-1) and a buffer (57
1-0, 571-1), ROM (572-0, 572-
1) and RAM (573-0, 573-1). The buffer (571-0, 571-1) stores a message to be transmitted to the terminal (6) and a disk device (54-0, 5
4-1) Write data is stored.

Further, a timer (530-0, 530-
1), an address decoder (531-0, 531-1) and an interrupt encoder (532-0, 532-1) are provided.

FIG. 20 shows the working system (30-) of the FEP (4).
FIG. 2 is a diagram showing a memory map of a standby system (30-1). The active system memory map (581-0) and the standby system memory map (581-1) are the same.

The shared memory (50-0, 50-1) stores the address (000000/16 to 0FFFFF / 16) in the range of 0 to α1...
0,200-1) α1 ~ α2 ........... Monitoring area for standby system (201-
0, 201-1) α2 to 0FFFFFF / 16 ... takeover management area (202-0,
202-1).

Working system (30-0) memory (32-0)
The memory (32-1) of the standby system (30-1) stores the address (100,000 / 16 to FFFFFF / 16) in the range of 100000/16 to β... OS area (583-0, 58).
3-1) β-γ: Program area (585-0, 58)
5-1) γ to FFFFFF / 16 ... reserved area (586-0,58)
6-1) Divided into three areas.

FIG. 21 is a detailed circuit diagram of the bus extenders (34-0, 34-1) of the FEP (4). Address lines A20-A23 of active processor (31-0)
If (541-0) are all "L", the shared memory (50-
0, 50-1), otherwise access the working memory (32-0). The same applies to the standby processor (31-1).

The control signal (55) of the active bidirectional driver
5-0), the address lines A20 to A23 (541-0) of the active processor (31-0) are all "L" and the W
When the / R line (546-0) is at "H", the shared memory (50
−0, 50-1), and when “L”, writing to the shared memory (50-0, 50-1) is performed. Control signal (555-1) for standby bidirectional driver
The same is true for

Next, the FEP will be described with reference to FIGS.
The register used in (4) will be described. These registers are provided in the active system monitoring area (200-0, 200-1) of the shared memory (50-0, 50-1). FIG. 22 shows the system status registers (256-0, 256-1), which are the FEP working system (30-0) and the FEP standby system (30-0).
-1) indicates the current state. Bit 4 indicates whether it is in the working state. Bit 3 indicates whether or not it is in the semi-active state. Bit 2 indicates whether or not the apparatus is in a standby state. Bit 1
Indicates whether the device is in the repaired state. Bit 0 indicates whether the device is offline. Bits 7 to 5 are not used. FIG. 23 shows an alive register (257-0, 25).
7-1), the active system (30-0) and the standby system (30-
In 1), the alive messages are exchanged with each other and used to monitor whether each other is normal. Only bit 0 is used, and if "1", an alive message has been transmitted,
If it is “0”, it means that the alive message has not been transmitted.

FIG. 24 shows an interrupt register (258-0,
258-1), and indicates whether or not an interrupt has occurred. The bit 6 (level 6) interrupt represents an emergency fault interrupt. An interrupt of bit 4 (level 4) indicates a fault interrupt. The bit 2 (level 2) interrupt represents a timer interrupt. The priority is higher as the number of levels is larger. Bits 7, 5, 3, 1, 0 are not used.
Note that the failure here is a system failure.

FIG. 25 shows host alive registers (259-0, 259-1) used to monitor whether the host (1) is normal. Only bit 0 is used, and if "1", an alive message has been transmitted,
If it is “0”, it means that the alive message has not been transmitted.

FIG. 26 shows the working system (30-) of the FEP (4).
FIG. 3 is a diagram showing a control circuit for timer interrupt of 0). The timer (530-0) is connected to the clock (550-0) and alive.
e message counter (551). The clock (550-0) increments the counter value of the alive message counter (551) by "1" every 10 ms. For example, if an interrupt occurs after a lapse of one second, the counter value is “10”.
When 0 "is increased, an interrupt is generated in the processor (31-0). The same applies to the control circuit for the timer interrupt of the standby system (30-1).

FIG. 27 is a detailed circuit diagram of the line adapter (35-0, 35-1) of the FEP (4). The line adapter (35-0, 35-1) is connected to the processor (590-
0,590-1), memory (591-0,591-
1), a buffer (592-0, 592-1) and a line controller (593-0, 593-1).

In the buffer (592-0, 592-1), a message receiving queue (40-0, 40-1),
A transmission queue (41-0, 41-1) is provided. The message received from the terminal (6) is stored in the message receiving queue (40-0, 40-1). The transmission queue (41-0, 41-1) stores a message to be transmitted to the terminal (6). Line control unit (593-0, 593-1)
Include line-specific sections (594-0, 594-0,
594-1) is provided.

FIG. 28 is a detailed circuit diagram of the LAN adapter (36-0, 36-1) of the FEP (4). The LAN adapter (36-0, 36-1) is connected to the processor (600).
−0, 600-1), memory (601-0, 601-
1), buffer (602-0, 602-1) and LA
It is composed of N control units (602-0, 602-1). The buffer (602-0, 602-1) has a message receiving queue (42-0, 42-1) and a transmission queue (4
3-0, 43-1). The message received from the host (1) is stored in the message receiving queue (42-0, 42-1). Transmission queue (43-0, 43-
1) stores a message to be transmitted to the host (1).

FIG. 29 is a diagram showing the transfer mode registers (44-0, 44-1) of the FEP (4). The transfer mode registers (44-0, 44-1) are registers indicating whether or not the FEP (4) collectively transfers messages to the host (1). Only bit 0 is used, "1" means batch transfer mode, and "0" means normal transfer mode. Normally, only the transfer mode register (44-0) of the active system (30-0) is used, and the transfer mode register (44-1) of the standby system (30-1) is not used.

FIG. 30 is a detailed circuit diagram of the line switching device (52) of the FEP (4). Contention prevention circuit (55)
Is allowed to transmit and receive with the active system (30-0), and the standby system (30-1) can only receive.

Next, the FEP will be described with reference to FIGS.
The software configurations of (4) and the host (1) will be described. FIG. 31 is a diagram showing a software configuration of the active system (30-0) of the FEP (4). Working system (30-0)
Receives the interrupt (700) and analyzes the interrupt type (701). The emergency failure interrupt (702) is at level 6,
The failure interrupt (703) is level 4 and the timer interrupt (7
04) is executed at level 2.

In the emergency failure interrupt (702), a shared memory recovery process (715) is executed in order to cope with a double failure of the shared memory (50-0, 50-1).
The recovery process (715) of the shared memory stores the contents of the shared memory (50-0, 50-1) in the disk device (54-
0, 54-1) to the working memory (32-0).

In the failure interrupt (703), a standby system disconnection process (711), a standby system connection process (712), and an execution host failure notification process (713) are executed. In the standby system disconnection process (711), when a failure occurs in the standby system (30-1), the standby system (30-1) is set to the offline state (153). Thereafter, the processing is continued only in the active system (30-0). In the standby system connection process (712), the standby system (30-1) recovered from the failure is set to the standby state, and the operation returns to the duplex operation. The host failure notification processing (713) is executed by the execution host (1-0) even after a certain time has elapsed.
When the message is not received, the failure of the execution host (1-1) is notified to the spare host (1-1).

In the timer interrupt (704), the standby system (3
0-1) Transmission processing of an alive message for failure detection (721), reception processing of an alive message in response thereto (722), and execution host (1-0)
, An alive message transmission process (723) for detecting a failure, an alive message reception confirmation process (724) for the alive message, and a shared memory backup process (725). The transmission process (721) of the standby alive message periodically transmits the alive message to the standby system (30-1). Standby alib
The e-message reception confirmation process (722) is performed in the active system (3
0-0) is the last alive from the standby system (30-1).
It is checked whether an alive message is received within a predetermined time after receiving the message. Host alive
The transmission process (723) of the e-message is periodically
ve message is sent to the execution host (1-0). Host alive message reception confirmation processing (724)
Checks whether the next alive message has been received within a predetermined time after receiving the last alive message from the execution host (1-0). The shared memory backup process (725) is performed by the shared memory (50-0,
In order to prepare for the double failure of 50-1), the contents of the shared memory (50-0, 50-1) are periodically stored in the disk devices (54-0, 54-1).

When the interrupt processing is completed, the active system (30-
0) executes a message processing (730). Message processing (7
30) uses the write processing to the disk device (50-0, 50-1) as a checkpoint, and stores checkpoint data (81) for each checkpoint in the shared memory (50).
−0, 50-1) takeover information area (63-0, 6)
3-1). When the processing of the message (730) is completed, the time stamp (72) of the message is displayed in the processed message area (6).
2-0, 62-1).

FIG. 32 shows the standby system (30-) of the FEP (4).
FIG. 2 is a diagram illustrating a configuration of software of 1). Standby system (3
0-1) is an interrupt (75) like the active system (30-0).
0) is received. The interrupt type analysis processing (751) analyzes whether a failure interrupt (752) or a timer interrupt (753). In the failure interrupt (752), the checkpoint data (81) in the takeover information area (63-0)
, The takeover processing of the active system (30-0) (76
Execute 1).

In the timer interrupt (753), the active system al
eve message transmission processing (771), active system ali
A ve message reception confirmation process (772), a host transfer message check process (773), and an end message check process (774) are executed. The transmission process of the active system alive message (771) periodically transmits the alive message to the active system (30-0). Active ari
The ve message reception confirmation process (772) checks whether the next alive message is received within a predetermined time after receiving the last alive message from the active system (30-0). The host transfer message check process (773) is performed by the active system (30-0) by the shared memory (5-0).
0-0, 50-1) Message area (6
1-0, 61-1), the time stamp (72) written is read, and the corresponding message (73) is stored in the L of the standby system (30-1).
The transmission queue (43-) of the AN adapter (36-1)
1). Check processing of end message (774)
Means that the active system (30-0) is shared memory (50-0,50)
-1) Processed message area (62-0, 62-1)
The time stamp (72) written in the standby system (30-1) is read, and the corresponding message is read.
Remove from the transmission queue (43-1) of 1).

FIG. 33 is a diagram showing a software configuration of the execution host (1-0). Execution host (1-0)
Receives the interrupt (800) and analyzes the interrupt type (801). The interrupt includes a fault interrupt (802) and a timer interrupt (803).

In the failure interrupt (802), the spare host (1-1) is disconnected (811) and the spare host (1
-1) The connection process (812), the congestion process (813), and the congestion release process (814) are executed. When a failure occurs in the spare host (1-1), the spare host disconnection process (811) disconnects the spare host (1-1) and continues processing only with the execution host (1-0). When the spare host (1-1) recovers from the failure, the spare host connection process (812) returns to the redundant operation with the execution host (1-0). The congestion process (813) causes the FEP (4) to temporarily suspend transmission of a message. The congestion release processing (814) is performed by the FE
The transmission of the message is restarted by P (4).

In the timer interrupt (802), the reception confirmation processing of the standby host alive message (821), the transmission processing of the standby host alive message (822), and F
EPalive message reception confirmation processing (823),
Transmission processing of spare host alive message (824)
And match control processing between the host and the FEP timer (82
Execute 5). The standby host alive message reception confirmation process (821) checks whether or not the last alive message from the standby host (1-1) is received and the next alive message is received within a predetermined time. Transmission processing of spare host alive message (8
22) periodically sends an alive message to the spare host (1-1). The reception confirmation processing of the FEP alive message (823) is performed within a predetermined time after receiving the last alive message from the FEP (4).
Check if a live message is received.
The transmission process of the FEPalive message (824) is as follows.
An alive message is periodically transmitted to the FEP (4). Host and FEP timer match control processing (825)
Makes the time stamp timers (51) of all the FEPs (4) coincide. The timer (18-) of the execution host (1-0)
0) and the timer (18-1) of the spare host (1-1) are matched. When these processes are completed, the message processing (83
Restart 0).

FIG. 34 is a diagram showing a software configuration of the spare host (1-1). Spare host (1-1)
Receives the interrupt (850) and analyzes the interrupt type (851). The interrupt includes a fault interrupt (852) and a timer interrupt (853).

In the failure interrupt (852), the takeover process (861) of the execution host is executed with reference to the takeover information of the disk device (2-0, 2-1).

In the timer interrupt (853), the reception confirmation processing of the execution host alive message (871) and the transmission processing of the execution host alive message (872)
Execute The execution host alive message reception confirmation process (871) checks whether or not the last alive message from the execution host (1-0) is received and the next alive message is received within a predetermined time. Execution host alive message transmission processing (87
2) periodically transfers the alive message to the execution host (1-1).

FIG. 35 is a diagram showing an outline of the message processing (830) in the execution host (1-0). Message processing (83
In (0), a message is received from FEP (4). This state is called a reception state (261). Next, the disk device (2
-Read necessary data from 0, 2-1). This state is called a read state (262). Then, the message processing is executed. Thereafter, the processing result is stored in the disk device (2-0, 2).
Write to -1). This state is called a write state (263). Finally, the terminal (6) returns a response. At this time, a state in which ACK is not received from the terminal (6) is called a transmitting state (264), and a state in which ACK is received is called a transmitted state (265).

FIG. 36 is a diagram showing a message management table (260). The message management table (260)
The state of one message is managed by bits 4, 3, 2, 1, and 0. Bits 7-5 are not used.

Next, five operation examples will be described. <Operation Example 1: Processing when Failure of Execution Host (1-0)> FIG. 37 shows the host (1), FEP (4), terminal (6) when a failure occurs in the execution host (1-0). It is a figure which shows the outline | summary of a processing procedure. The terminal (6) sends the electronic message (71) to the FEP (4) (process 900). The FEP (4) transfers the message (73) to the execution host (1-0) (process 90).
1). The execution host (1-0) periodically sends an alive message to the spare host (1-1) (Process 9).
03) cannot be sent if a failure occurs (process 90).
2). Therefore, the spare host (1-1) detects the failure of the execution host (1-0) (process 904), and all the Fs
The failure occurrence is notified to the EP (4) (process 905).

When the FEP (4) receives the notification of the occurrence of the failure, the execution host (1-0) starts holding the message including the message that could not be received (process 906). The spare host (1-1) refers to the journal and checkpoint data of the execution host (1-0) to execute the takeover processing (processing 907). When the takeover process is completed, F
The completion of the takeover process is notified to the EP (4) (process 908).

When the FEP (4) receives the notification of the completion of the takeover process, the FEP (4) collectively transfers the held messages to the spare host (1-1) (process 909). When the spare host (1-1) receives the messages from all the FEPs (4), the spare host (1-1) executes the processes in chronological order with reference to the time stamp (72) of the messages (process 910).

Next, the detailed procedure of the execution host (1-0) and the spare host (1-1) will be described.

FIG. 38 is a diagram showing in detail the processing procedure of the execution host (1-0). A message is received and message processing is executed (process 1000). At regular intervals, a message management table (260), checkpoint data indicating I / O management information and task information are recorded in the disk device (2). At the time of I / O issuance, a journal indicating the history of I / O is recorded in the disk device (2) (Process 100).
1). When a failure occurs, the processing stops (processing 100
2).

FIG. 39 is a diagram showing in detail the processing procedure of the spare host (1-1). A failure of the execution host (1-0) is detected by exchanging alive messages (Process 1).
010). The exchange of the alive message with the execution host (1-0) is interrupted (process 1011). All the FEPs (4) report that a failure has occurred in the execution host (1-0).
(Step 1012). The FEP (4) sets the transfer mode to the batch transfer mode and suspends the message transfer to the host (1) (Process 1013). A file recovery process is performed (process 1014). That is, the execution host (1-
The file is recovered by the journal or the like of 0). The communication state is recovered (processing 1015). That is,
Restore communication status. Notify all FEPs (4) that the takeover process of the execution host has been completed (process 10).
16). The FEP (4) transfers the message to the spare host (1-1) in a batch, and transitions from the batch transfer mode to the normal transfer mode (process 1018). A message is collectively received from all FEPs (4) (process 1018). Processing is performed on the messages received collectively in the order of the time stamp (Process 1
019).

FIG. 40 is a diagram showing the concept of the failure detection method of the execution host (1-0) using the alive message. The execution host (1-0), for example, alive every one second
e message to spare host (1-1) and FEP
Send to (4). Spare host (1-1) and FEP
(4) determines that a failure has occurred in the execution host (1-0) if the next alive message is not received within, for example, two seconds after receiving the last alive message.

FIG. 41 is a flowchart of a spare host alive message transmission process performed by the execution host (1-0). When the spare host alive message transmission process (822) is activated by a timer interrupt every second, the alive register (2) of the spare host (1-1) is activated.
0-1) from “00/16” to “01/16” (Process 10
30).

FIG. 42 is a flowchart of the execution host alive message reception confirmation process performed by the spare host (1-1). Execution host (1-0) to final a
When the reception confirmation process (871) of the execution host alive message is started by a timer interrupt two seconds after the reception of the live message, the alive register (2
0-1) is “01/16” (process 103)
1). If the alive register (20-1) is "01/16", the execution host (1-0) judges that it is normal, and alive
The e-register (20-1) is returned from "01/16" to "00/16" (process 1032). On the other hand, the alive register (2
0-1) is not "01/16", the execution host (1-
It is determined that a failure has occurred in 0) (process 1033). Similarly, the failure of the execution host (1-0) is detected in the FEP (4).

FIG. 43 is a diagram showing the concept of the file recovery process and the communication status recovery process performed by the spare host (1-1). The execution host (1-0) is connected to the memory MS
The task (11-0), the I / O management information, and the message management table are written to the disk device (2-0, 2-1) at regular intervals as checkpoint data (25) (process 1020). . The spare host (1-1)
With reference to the history (87) of the message management table, the state of the message in the message management table is matched with the time of occurrence of the failure (Process 1
021). Then, the checkpoint data (25) is read from the disk device (2-0, 2-1) and written to the memory MS (11-1) (process 1022). Lastly, referring to the journal (26), if there is a file that has not been updated, the file is updated to match the time when the failure occurred (Process 1).
023). As a result, the state of the file and the state of communication are restored to the point of occurrence of the failure.

FIG. 44 is a diagram showing a batch message of FEP (4). The batch message is the L of the FEP working system (30-0).
The transmission queue (43-) of the AN adapter (36-0)
0). The FEP (4) transfers a batch message by designating a start address (85) and a length (86).

FIG. 45 is a diagram showing a batch message of the spare host (1-1). The batch message is the spare host (1-1)
And a reception queue is provided for each FEP (4).
The spare host (1-1) is the time stamp (72-**) of the message.
It is executed in order from the smallest message.

FIG. 46 is a diagram showing a time stamp (72). The time stamp (72) is in units of 10 ms. The message is executed in the order of the time stamp, but since it is only necessary to follow the order in about 1 second,
Mask the lower 7 bits of the time stamp (72) and refer to only the upper 9 bits. Therefore, 1.28 seconds (= 10 ms ×
The messages are executed in an order having an error of (7 bits).

Next, the working system (30-0) of the FEP (4)
And the processing procedure of the standby system (30-1) will be described. FIG. 47 is a diagram showing a detailed processing procedure of the active system (30-0). The message is taken out from the reception queue (40-0) of the line adapter (35-0) (process 1050).
Judge whether the message is a message to be transferred to the host (1) (Process 1
051). For messages to be transferred to the host (1), LAN
It is stored in the transmission queue (43-0) of the adapter (36-0) (process 1052). LAN adapter (36-
0) refers to the mode register to judge whether the mode is the batch transfer mode (process 1060), and if the mode is the batch transfer mode, stores it in the transmission queue (43-0) (process 1061); (1) Transfer the message to (1)
062).

In the case of a message processed in FEP (4), it is determined whether the standby system (30-1) is in the standby state (process 105).
3). If the standby system (30-1) is in the standby state, the redundant operation is being performed. Therefore, the time of writing to the disk device (54-0, 54-1) is set as a check point, and the check point data is stored for each check point in the shared memory ( 50-
0, 50-1) takeover information area (63-0, 63)
-1) (step 1055). When the processing of the message is completed, the time stamp of the message is stored in the shared memory (50-0,5).
0-1) Processed message area (62-0, 62-)
1) (process 1056). Standby system (30-1)
If is not in the standby state, the operation is not a duplex operation, and thus the above processes 1055 and 1056 are skipped (process 105
4).

FIG. 48 shows the handover information writing process 1
It is a detailed flowchart figure of 055. Processor (3
1-0) saves the values of the address register AR0 (510-0) and the data register DR0 (500-0) in the memory (32-0) (process 1070). AR0
The start address of the checkpoint data is set in (510-0), and the data length of the checkpoint data is set in the data register DR0 (500-0) (Process 10).
71).

The checkpoint data is stored in the shared memory (5
0-0, 50-1) takeover information area (63-0, 50-1)
63-1), one byte is written to the data register DR0.
The content of (500-0) is decremented by "-1" (process 107).
2). It is determined whether the content of the data register DR0 (500-0) is "0" (whether all checkpoint data has been written to the takeover information area) (step 1073).
If the content of the data register DR0 (500-0) is not "0", the process returns to the above-mentioned process 1074, and if "0", the content of the address register AR0 (510-
0) and the values of the data register DR0 (500-0) are recovered (process 1075).

Data registers DR0 to DR7 (500-
0, 507-0), address registers AR0 to AR6
(510-0 to 516-0), stack pointer AR7
(520-0), status register SR (521-
0), the contents of the program counter PC (522-0) are stored in the takeover information area (63-0, 63-1) (process 1076).

FIG. 49 shows the standby system (30-) of the FEP (4).
It is a flowchart figure which shows the detailed processing procedure of 1).
The handover information area (62-0, 62-1) of the shared memory (50-0, 50-1) is periodically scanned, and the time stamp of the message is read (process 1080). The LAN adapter (36-1) notifies the read time stamp to the LAN adapter (36-1), and the LAN adapter (36-1) sends the corresponding message to the transmission queue (4-4).
3-1) (Step 1081). The line adapter (35-1) notifies the read time stamp to the line adapter (35-1), and the line adapter (35-1) sends the corresponding message to the reception queue (40-35).
1) (Step 1082).

As described above, the failure occurs in the execution host (1-0) and during the takeover to the spare host (1-1), the FEP
(4) holds the message to be transferred to the host (1), and since the execution host (1-0) manages the state of the message being processed, the message is not duplicated or missing. In addition, disconnection of the session between the host (1) and the FEP (4) can be prevented.

<Operation Example 2: Processing when a failure occurs in the FEP working system (30-0)> FIG. 50 shows the host (1) and the FEP (4) when a failure occurs in the FEP working system (30-0). It is a figure which shows the outline | summary of the processing procedure of a terminal (6). Terminal (6)
Sends the message (71) to the FEP (4) (processing 90
0). The FEP working system (30-0) transfers the message to the host (1) (process 901). FEP working system (30-
When a failure occurs in (0) (process 910), the FEP standby system (30-1) detects the failure and notifies the host (1) (process 912).

FIG. 51 is a flow chart of the takeover process of the FEP standby system (30-1) when a failure occurs in the FEP active system (30-0). When the failure of the active system (30-0) is detected by the alive message (processing 1
200), and notifies the host (1) of the occurrence of the failure (Process 1)
201).

By setting the system status register of the working system (30-0), the working system (30-0) is set to the offline state (process 1202). The standby system (30-1) is set by setting the system status register of the standby system (30-1).
Is set to the active state (process 1203). The transmission processing and the reception confirmation processing of the alive message are interrupted (processing 120
4).

The shared memory (50-0, 50-1) is read out, a message being processed is searched (process 1205), and it is determined whether or not the process has been executed up to the check point (process 1206). If the process has been executed up to the check point, the process is restarted from the check point (process 1207).
If the process has not been executed up to the check point, the process is performed from the beginning (process 1208).

The time stamp of the processed message is notified to the line adapter (35-1) and the LAN adapter (36-1), and the line adapter (35-1) and the LAN adapter (36-1) are notified.
-1) receives the corresponding message in the reception queue (40-
1), it is removed from the transmission queue (43-1) (process 1209).

FIG. 52 is a detailed flowchart of the process of restarting the process from the check point (process 1207). Data registers DR0 to DR7 (500-0 to 507-) stored in the takeover information area (63-0, 63-1) of the shared memory (50-0, 50-1)
0), address registers AR0 to AR6 (510-0 to
516-0), the stack pointer AR7 (520-
0), the contents of the status register SR (521-0) and the contents of the program counter PC (522-0) are stored in the standby system (30
-1) The processor (31-1) is set to each register (process 1520). The processor (31-1) of the standby system (30-1) issues an RTE instruction to the disk device (5-1).
4-0, 54-1), the process is restarted from the writing process (checkpoint) (process 1221). As a result, FE
P Even if a failure occurs in the active system (30-0), the standby system (3
0-1) takes over, so host (1) and FEP (4)
Disconnection of the session can be prevented.

FIG. 53 is a flowchart showing the details of the transmission processing of the alive message. The send processing of the alive message is started by a timer interrupt every second, and the other alive register is changed from “0/16” to “1/1 /
16 "(processing 1230).

FIGS. 54 and 55 are flowcharts showing the details of the process for confirming the reception of the alive message.
The reception confirmation processing of the alive message in FIG.
activated by the reception of the live message
The ve register is returned from “1/16” to “0/16” (Process 1
231), the alive message counter is returned to “0” (process 1232). The alive message reception confirmation process of FIG. 55 is started by a 10 ms timer interrupt, and increments the alive message counter by "+1" (process 1233). alive message counter is "20"
If it becomes 0 ”or more (process 1234), the active system (30-
At 0), it is determined that a failure has occurred (process 1235). a
If the live message counter is less than “200”, the process 1235 is skipped.

FIG. 56 shows the old working system (30
FIG. 10A is a flowchart diagram showing a process until −0a) recovers from the failure and performs the duplex operation with the FEP new active system (30-1a), which is the old standby system that has taken over the processing. Old working system (30-0
a), after recovering from the failure, the completion of the repair is notified to the new active system (3
0-1a) (process 1240).

The new active system (30-1a) is replaced with the old active system (3-1
0-0a) is received (Step 124)
6). Then, the checkpoint data is transferred to the takeover information area (63-) of the shared memory (50-0, 50-1).
0, 63-1) (process 1247).

The old working system (30-0a) changes the system status register from the off-line status to the repair status (process 124).
1). The reception of a message from the terminal (6) is started (Process 1).
242). The old working system (30-0a) reads the shared memory (50-0, 50-1) every second, and if the time stamps do not match, the old working system (30-0a) is still synchronized with the new working system (30-1a). It is determined that there is no message, and when the time stamps match, it is determined that the message has been received synchronously (process 1243). When it is determined that the message is received in synchronization, the old working system (30-0)
In a), the system status register is changed from the recovery status to the standby status (process 1245), and the duplex operation is started.

<Operation Example 3: Processing at Congestion of Execution Host>
When the message from the terminal (6) is congested, the queues of the FEP (4) and the host (1) run out of space and cannot be processed. An operation example at this time will be described. FIG.
It is a figure which shows the outline | summary of the communication processing procedure of the congestion state between an execution host (1-0), FEP (4), and a terminal (6). The terminal (6) sends a message to the FEP (4) (process 900).
The FEP (4) transfers the message to the host (1) (process 901).

When the host (1) detects a congestion state (process 930), the execution host (1-0) sends all FEPs
A congestion state is notified to (4) (process 931). FEP
In (4), upon receiving the congestion state, FEP (4) stops transmitting the message and starts holding the message (process 932).

The execution host (1-0) processes the message stored in the queue without receiving the message. Therefore, the number of messages stored in the queue decreases, and the congestion state disappears. When the execution host (1-0) detects the congestion release (process 935), it notifies all the FEPs (4) of the congestion release (process 936).

When all the FEPs (4) receive the congestion release notification, the FEP (4) collectively stores the held messages in the host (1).
(Step 937). The execution host (1-0)
When the message is received from all the FEPs (4), the process is executed in the order of the time with reference to the time stamp of the message (process 9).
38).

FIG. 58 shows the execution host (1-0) and the FEP.
(4) is a flowchart showing a processing procedure for detecting a congestion state. The execution host (1-0) is the FEP (4)
When a message is received from, the received message counter is incremented by "+1" (process 1400). When the count value of the received message counter becomes equal to or greater than the congestion reference value (processing 1401), the mobile station determines that the state is congested (processing 1402), and notifies all the FEPs (4) that the congestion state has been reached (processing 1403). If the count of the received message counter is less than the congestion reference value (processing 14
01), the processes 1402 and 1403 are skipped.

FEP (4), upon receiving the congestion notification,
The transfer mode register is set to the batch transfer mode (process 1404). After that, the FEP (4) suspends the transfer to the execution host (1-0) until the congestion state is released, and transfers the input message from the terminal (6) to the LAN adapter (36-0).
In the transmission queue (43-0).

FIG. 59 shows the execution host (1-0) and the FEP.
(4) is a flowchart showing a processing procedure for detecting a congestion release state. When the execution host (1-0) processes the message of the LAN controller HLANC, the execution host (1-0) sets the received message counter to "-1" (step 1410). If the count value of the received message counter is equal to or less than the congestion release reference value (process 1411), it is determined that the congestion state has been released (process 1412).
All FEPs (4) are notified that they have been released from the congestion state (process 1413). While the count value of the received message counter is larger than the congestion release reference value, the above-described processing 141 is performed.
2, 1413 are skipped (process 1411).

Upon receiving the congestion release notification, FEP (4) sets the transfer mode register to the normal transfer mode (processing 1414). Then, the held message is transferred to the execution host (1-0).

<Operation Example 4: Host (1) and FEP (4)>
Timer Matching Control Process> In order to manage a message using the time stamp (72), it is necessary to match the time of the time stamp timer (51) in all FEPs (4). The timer coincidence control processing will be described with reference to FIGS.

FIG. 60 is a flowchart showing the time transmission process of the execution host (1-0). Execution host (1
(-0) reads the time from the timer (18-0) at regular intervals and transmits the time to all the FEPs (4) (process 960). In addition, the time is also transmitted to the spare host (1-1) so that the time of the execution host (1-0) and the time of the spare host (1-1) are synchronized (step 961).

FIG. 61 shows that the FEP (4) and the spare host (1
It is a flowchart figure which shows the collation processing of the timer in -1). The FEP (4) and the spare host (1-1) determine whether or not the time difference Δ between the execution host (1-0) and t21 is equal to or greater than t21 (process 1600). If the difference Δ is equal to or greater than t21, FEP
(4) The timer failure of the spare host (1-1) is determined (step 1601), the timer failure is notified to the execution host (1-0) (step 1602), and the time stamp is not added to the message. (Step 1603).

If the difference Δ is smaller than t21, it is determined whether the difference Δ is equal to or larger than t22 (step 1604). If the difference Δ is less than t21 and greater than or equal to t22, the timers of the FEP (4) and the spare host (1-1) are set to the time of the execution host (1-0) (Process 16).
05). If the difference Δ is less than t22, it is determined that the timers of the FEP (4) and the spare host (1-1) are correct (step 16).
06).

<Operation Example 5: Processing at the time of double failure of FEP shared memory> FEP (4) shared memory (50-0,5)
If a double failure occurs in 0-1), the FEP (4) leads to a system down. Accordingly, the FEP (4) periodically backs up the contents of the shared memory (50-0, 50-1) to the disk devices (54-0, 54-1), and journals the I / O when it is issued. Is stored in the disk device (54-0, 54-1) so that even if a double failure occurs in the shared memory (50-0, 50-1), the system does not go down. 62 to 63
The processing procedure will be described with reference to FIG.

FIG. 62 shows the shared memory (50-0, 50-
It is a flowchart figure of 1) backup processing. This process is started periodically. Shared memory (50-0,
The start address and length of 50-1) are set, and the storage area of the disk device (54-0, 54-1) is set (process 1700). Shared memory (50-0, 50-1)
From the disk device (54-0, 54-1),
The length is set to "-1" (process 1701). With reference to the length, it is determined whether the copy of the shared memory (50-0, 50-1) has been completed (process 1702). The above process 1701 is repeated until the copying of the shared memory (50-0, 50-1) is completed (until the length becomes "0"). By the above processing, the shared memory (50-0, 50-
The contents of 1) can be backed up to the disk devices (54-0, 54-1). When the I / O is issued, the journal is collected in the disk device (54-0, 54-1). Even when the area is full, the shared memory (50-0, 50-) is used.
The backup processing of 1) is performed.

FIG. 63 shows the shared memory (50-0, 50-
It is a flowchart figure of 1) double failure detection processing. F
The EP working system (30-0) has a shared memory (50-0,5).
0-1) is accessed (processing 1710), and it is determined whether or not there is an ACK from the shared memory (50-0, 50-1) (processing 1711). Shared memory (50-0, 50-1)
From the shared memory (50-0, 50-
1) is determined to be normal (processing 1712). If there is no ACK from the shared memory (50-0, 50-1), it is determined that a double failure has occurred in the shared memory (50-0, 50-1), and an interrupt (interrupt level 6) is generated. (Process 17
13).

FIG. 64 shows the working system (30-) of the FEP (4).
FIG. 10 is a flowchart of a recovery process performed by the shared memory (50-0, 50-1) at the time of a double failure performed by the shared memory (0). Working system (3
0-0) is stored in the shared memory (50) in the execution host (1-0).
−0, 50-1) is notified (processing 172).
0), the exchange of the alive message with the standby system (30-1) is interrupted (process 1721).

When the double failure is resolved, the contents backed up are read from the disk devices (54-0, 54-1) and stored in the reserved area (586-0) of the active memory (32-0). Write shared memory (50-0,5)
0-1) recovery processing is performed (processing 1722). At this time, the contents written in the active memory (32-0) are updated with reference to the FEP journal indicating the I / O history, and returned to the contents at the time of the occurrence of the double failure in the shared memory (processing). 1723). Then, the FEP (4) refers to the working memory (32-0) and restarts the message processing (processing 1724).

FIG. 65 shows the shared memory (50-0, 50-
It is a detailed flowchart figure of 1) recovery processing (the above-mentioned processing 1722). Shared memory (50-0, 50-
The start address of 1) is set, and the disk device (54-
(0, 54-1) is set (processing 173).
0). The contents are copied from the disk device (54-0, 54-1) to the shared memory (50-0, 50-1), and the length is set to "-1" (process 1731). With reference to the length, it is determined whether the copying of the disk device (54-0, 54-1) has been completed. The above process 1731 is repeated until the copy is completed (process 1732). By the above processing, the contents of the disk device (54-0, 54-1) can be recovered to the shared memory (50-0, 50-1).

As a result, even if a double failure occurs in the shared memory, the contents of the shared memory (50-0, 50-1) can be referred to from the active memory (32-0). Continuation is possible.

The FEP (4) is executed by the execution host (1-
0), a failure of the execution host (1-0) is detected by not receiving an alive message within a predetermined time,
The spare host (1-1) notifies the failure of the execution host (1-0), and the spare host (1-1) notifies the other FEP (4) of the failure of the execution host (1-0). It may be.

[0127]

According to the terminal uninterrupted online system of the present invention, even if a failure occurs in the execution host, the spare host can take over the processing without interrupting the session with the terminal. Further, even if a failure occurs in the FEP, it is possible to prevent loss of a message from the terminal and a message to be transferred to the host.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a terminal uninterrupted online system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a host computer.

FIG. 3 is a configuration diagram of an FEP.

FIG. 4 is a schematic diagram of a process according to the present invention.

FIG. 5 is a flowchart of a process according to the present invention.

FIG. 6 is a format diagram of a message received from a terminal.

FIG. 7 is a format diagram of a message between the host and the FEP.

FIG. 8 is a format diagram of a transmission message to a terminal.

FIG. 9 is a schematic diagram illustrating an alive register for a spare host of an execution host;

FIG. 10 is a schematic diagram showing an active host alive register of a spare host.

FIG. 11 is a schematic diagram illustrating an FEP alive register of an execution host.

FIG. 12 is a schematic diagram showing an FEP alive register of a spare host.

FIG. 13 is a schematic diagram showing a received message counter.

FIG. 14 is a schematic diagram showing a congestion reference value register.

FIG. 15 is a schematic diagram showing a congestion release reference value register.

FIG. 16 is a state transition diagram of FEP.

FIG. 17 is a mode transition diagram of the FEP shared memory.

FIG. 18 is an explanatory diagram showing an exclusive control method of the FEP shared memory.

FIG. 19 is a detailed circuit diagram of a processor, a memory, an IOP, and a bus extender of the FEP.

FIG. 20 is a memory map diagram of an active system and a standby system of the FEP.

FIG. 21 is a detailed circuit diagram of a bus extender of the FEP.

FIG. 22 is a schematic diagram showing an FEP system status register.

FIG. 23 is a schematic diagram showing an alive register of the FEP.

FIG. 24 is a schematic diagram showing an interrupt register of the FEP.

FIG. 25 is a schematic diagram showing an alive register for an execution host of FEP.

FIG. 26 is a circuit diagram showing a control circuit for timer interruption of FEP.

FIG. 27 is a detailed circuit diagram of a line adapter of the FEP.

FIG. 28 is a detailed circuit diagram of a LAN adapter of the FEP.

FIG. 29 is a schematic diagram showing a mode register of the FEP.

FIG. 30 is a detailed circuit diagram of a line switching device of the FEP.

FIG. 31 is a configuration diagram of active software of the FEP.

FIG. 32 is a configuration diagram of FEP standby system software;

FIG. 33 is a configuration diagram of software of an execution host.

FIG. 34 is a configuration diagram of software of a spare host.

FIG. 35 is a schematic diagram of message processing in a host.

FIG. 36 is a schematic diagram showing a message management table.

FIG. 37 is an explanatory diagram of a communication processing procedure of the host, the FEP, and the terminal when the execution host fails.

FIG. 38 is a flowchart showing the processing procedure of the execution host.

FIG. 39 is a flowchart illustrating a processing procedure of a spare host.

FIG. 40 is an explanatory diagram of a failure detection method using an alive message of an execution host.

FIG. 41 is a flowchart of a process of transmitting a spare host alive message by the execution host;

FIG. 42 is a flowchart of a reception confirmation process of the execution host alive message of the spare host.

FIG. 43 is an explanatory diagram showing a host file recovery process and a communication status recovery process.

FIG. 44 is a schematic view showing a batch message of FEP.

FIG. 45 is a schematic diagram showing a batch message of a spare host.

FIG. 46 is a schematic view showing a time stamp.

FIG. 47 is a flowchart showing a detailed processing procedure of the FEP active system;

FIG. 48 is a detailed flowchart of a process 1055 in FIG. 47.

FIG. 49 is a flowchart showing a detailed processing procedure of the FEP standby system.

FIG. 50 shows the execution host and FE at the time of failure of the active system of FEP
It is explanatory drawing which shows the communication processing procedure of P and a terminal.

FIG. 51 is a flowchart of a takeover process of the FEP standby system.

FIG. 52 is a detailed flowchart of a process 1207 in FIG. 52.

FIG. 53 is a detailed flowchart of an alive message transmission process.

FIG. 54 is a detailed flowchart of an alive message reception confirmation process.

FIG. 55 is another detailed flowchart of the reception confirmation processing of the alive message;

FIG. 56 is a flowchart of the failure recovery process of the old active system.

FIG. 57 is an explanatory diagram showing a communication processing procedure of the execution host, the FEP, and the terminal in the congestion state;

FIG. 58 is a flowchart showing a processing procedure for detecting a congestion state between the execution host and the FEP.

FIG. 59 is a flowchart illustrating a processing procedure for detecting a congestion release state between the execution host and the FEP.

FIG. 60 is an explanatory diagram showing a time transfer procedure.

FIG. 61 is a flowchart showing the timer coincidence processing procedure of the FEP and the spare host.

FIG. 62 is a flowchart of a backup process of a shared memory.

FIG. 63 is a flowchart of double failure detection processing of the shared memory.

FIG. 64 is a flowchart of a recovery process when a double failure occurs in the shared memory.

FIG. 65 is a flowchart of a recovery process of the shared memory.

[Explanation of symbols]

1. Host computer, 1-0 Execution host, 1-1
... spare host, 2 ... disk device shared by host, 3 ... high-speed LAN, 4 ... FEP, 5 ... line, 6 ... terminal, 18-0 ... timer of execution host, 18-1 ... timer of spare host, 20-0 ... an alive register of the execution host, 20-1 ... an alive register of the spare host, 21-0 ... an alive register for FEP of the execution host, 21-1 ... an alive register of FEP of the spare host, 22-0 ... received message of the execution host 22-1 ... Received message counter of spare host 23-0 ... Congestion reference value register of execution host 23-1 ... Congestion reference value register of spare host 24-0 ... Congestion release reference value register of execution host 24-1: Congestion release reference value register of spare host 30-0: FEP working system, 30-1: FEP spare system, 31-0: current Processor for use, 31-1 ... Processor for standby, 35-0 ... Line adapter for work, 35
-1: standby line adapter, 36-0: active LA
N adapter, 36-1 ... standby LAN adapter, 40
−0: reception queue of the active line adapter 40-1: reception queue of the standby line adapter 41-0: transmission queue of the active line adapter 41-1: standby 42-0: Queue for reception of the active LAN adapter; 42-1: Queue for reception of the LAN adapter of the standby system; 43-0: Transmission of the LAN adapter for the active system Credit queue, 43-1: transmission queue of standby LAN adapter, 50-0, 50-1: shared memory of FEP, 51: time stamp timer, 52: line switching device, 54-0, 54-1 ... FEP disk device, 60-0, 60-1... FEP processing executing message area 61-0, 61-1... Host processing executing message area 62-0, 62-1... , 63- ... received message from the takeover information area 70 ... terminal, 71 ... message body, 72 ... time stamp, 73 ... execution host and message between the active FEP, 74 ...
Message body, 75: Transmission message, 76: Message body, 87: History of message management table.

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Masaya Yasu 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside Hitachi, Ltd.System Development Laboratory Co., Ltd. (72) Inventor Toshiyuki Kinoshita 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Hitachi Systems Development Laboratory (72) Inventor Hiroshi Oguro 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Hitachi Ltd.Kanagawa Plant (72) Inventor Atsushi Ugajin 1st Horiyamashita, Hadano-shi, Kanagawa Hitachi Ltd.Kanagawa Plant, Ltd. (72) Inventor, Isao Yoshino, 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture, Ltd.Kanagawa Plant, Hitachi, Ltd. (72) Inventor Takeshi Oga 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture, Kanagawa Plant, Hitachi, Ltd. (72) Inventor Satoshi Takemura 1 Horiyamashita, Hadano-shi, Kanagawa Inside Computer Computer Electronics (72) Inventor Yoshinori Tanaga 504-2 Shinanomachi, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Electronics Service Co., Ltd. (72) Inventor Hiroyuki Tsuneda 504-2 Shinanocho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Services (72) Inventor Norio Morioka 504-2 Shinanomachi, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within Hitachi Electronics Service Co., Ltd. (56) References JP-A-2-232738 (JP, A) JP-A-64-67635 ( JP, A) JP-A-4-33036 (JP, A) JP-A-3-196236 (JP, A) JP-A-2-77943 (JP, A) JP-A-63-307550 (JP, A) 63-216008 (JP, A) JP-A-2-148227 (JP, A) JP-A-59-49651 (JP, A) JP-A-61-98423 (JP, A) Hiroto Kawahara Uninterrupted Terminal Method for Fast Restart ”, Transactions of the Information Processing Society of Japan, Japan, February 15, 1989, Vol. 30, No. 2, p. 214-225 Tsuruho Seiji and two others, "High reliability method for large-scale functional distributed system", IEICE Transactions on Electronics, D-1, Japan, February 1990, Vol. J73-DI, No. 2, p. 235-244 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 15/00 G06F 11/20 G06F 15/177

Claims (8)

(57) [Claims] A host configured by a hot standby system in which an execution host and a spare host share a disk device is provided with a terminal, a front-end processor, and a high-speed LA.
In the online system connected via N, the host manages the state of all messages, the front-end processor has a dual configuration of the active system and the standby system, and the active system and the standby system have a line to the terminal. And a LAN adapter for connecting to a high-speed LAN. The line adapter is provided with a storage device for holding a received message from the terminal. When receiving a message from the terminal, the terminal is used as the active and standby terminals. Connected to both line adapters of the system and store the received messages in their storage devices,
The N adapter is provided with a storage device for holding a transmission message to the execution host, and when the host is stopped, the message to be transferred to the host is held in the storage devices of both the active and standby LAN adapters . Redundant sharing for front-end processors
Memory is provided, and the front-end
The time stamp of the message being processed by Sessa and the
Time stamp of the message to be sent and the time stamp of the message to be transferred to the host
And a terminal uninterrupted online system. 2. The terminal uninterrupted online system according to claim 1, wherein a standby system of the front-end processor is provided.
Is executed by the front-end processor every predetermined time.
Read the time stamp of the completed message from shared memory
Waiting for the corresponding message to be received by the standby line adapter.
A terminal uninterrupted online system characterized by removing from a queue . 3. An apparatus according to claim 1 or terminal uninterrupted online system according to claim 2, the front end pro
The standby system of the processor should be transferred to the host every predetermined time.
Reads the time stamp of the telegram from the shared memory and responds
The telegram is transferred from the storage device of the standby line adapter to the LAN adapter.
A terminal uninterrupted online system, wherein the terminal is transferred to a storage device of a terminal. 4. A terminal uninterrupted online system according to any one of claims 1 to 3, front-
Command processor includes a disk device, the shared memory
The contents are stored in the disk device at predetermined time intervals, and
A terminal uninterrupted online system wherein an O history is stored in a disk device when an I / O is issued . 5. The terminal uninterrupted online system according to claim 1, wherein the execution host
Has a counter that counts the number of stored messages,
Congestion when the count of
A terminal uninterrupted online system for notifying a state to a front-end processor . 6. A terminal uninterrupted online system according to one of claims 1 to 5, the front-end processor, or congestion detecting a failure or perform a host notified of the failure of the execution host A terminal uninterrupted online system characterized by stopping transmission of a message to a host upon receiving a notification of a state, and retaining the message body and its time stamp in a LAN adapter. 7. A terminal uninterrupted online system according to claim 6, front-end processor is notified of the cancellation of the takeover notification receiving Ru or congestion status of the execution host by the preliminary host, the LAN adapter A terminal uninterrupted online system characterized by transferring a message body and its time stamp stored in a storage device to a host in a batch. 8. The method according to claim 1, wherein :
Execution host in the terminal uninterrupted online system
Indicates the status of the message in the receiving status, reading status, and writing status.
State, sent state, sent state
And a terminal uninterrupted online system characterized in that the states of these messages are used as checkpoint data .