JP3338914B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents
Semiconductor device and method of manufacturing semiconductor deviceInfo
- Publication number
- JP3338914B2 JP3338914B2 JP20331194A JP20331194A JP3338914B2 JP 3338914 B2 JP3338914 B2 JP 3338914B2 JP 20331194 A JP20331194 A JP 20331194A JP 20331194 A JP20331194 A JP 20331194A JP 3338914 B2 JP3338914 B2 JP 3338914B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive layer
- semiconductor layer
- resistance semiconductor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 238000005275 alloying Methods 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 39
- 238000010586 diagram Methods 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000008186 active pharmaceutical agent Substances 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/806—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with Schottky drain or source contact
Description
【０００１】[0001]
【産業上の利用分野】本発明は、オーミック電極の構造
に特徴を有する電界効果型半導体装置（ＦＥＴ）、ヘテ
ロバイポーラトランジスタ（ＨＢＴ）等半導体装置及び
これら半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a field effect semiconductor device (FET), a hetero bipolar transistor (HBT), etc., characterized by the structure of an ohmic electrode, and a method of manufacturing these semiconductor devices.
【０００２】[0002]
【従来の技術】従来から、半導体装置のオーミック電極
は、コンタクト抵抗を下げるために高濃度不純物添加半
導体薄膜上に形成されていた。2. Description of the Related Art Hitherto, an ohmic electrode of a semiconductor device has been formed on a highly doped semiconductor thin film in order to reduce contact resistance.
【０００３】図４は、従来のＨＥＭＴの説明図であり、
（Ａ）は構成を示し、（Ｂ）は電流経路を示している。
この図において、１１はＧａＡｓ基板、１２はバッファ
層、１３は電気伝導層、１４はキャリア供給層、１５は
ｎ+ −ＧａＡｓ層、１６はゲート電極、１７は絶縁膜、
１８1 はソース電極、１８2 はドレイン電極、１９は電
極金属拡散領域である。FIG. 4 is an explanatory view of a conventional HEMT.
(A) shows the configuration, and (B) shows the current path.
In this figure, 11 is a GaAs substrate, 12 is a buffer layer, 13 is an electric conductive layer, 14 is a carrier supply layer, 15 is an n + -GaAs layer, 16 is a gate electrode, 17 is an insulating film,
18 1 is a source electrode, 18 2 is a drain electrode, and 19 is an electrode metal diffusion region.
【０００４】従来のＨＥＭＴは図４（Ａ）に示すよう
に、ＧａＡｓ基板１１の上に、バッファ層１２、電気伝
導層１３、キャリア供給層１４が形成され、その上にし
きい値を制御するため及びコンタクト抵抗を含むソース
抵抗を低減するための不純物を高濃度に添加したｎ+ −
ＧａＡｓ層１５が形成され、しきい値を所望の値に設定
するためにリセスされたｎ+ −ＧａＡｓ層１５にゲート
電極１６が形成され、ゲート電極１６の周囲のｎ+ −Ｇ
ａＡｓ層１５の上に絶縁膜１７が形成され、ｎ+−Ｇａ
Ａｓ層１５のゲート電極１６を挟んだ位置にＡｕＧｅ／
Ａｕが合金化処理されて、ソース電極１８1 とドレイン
電極１８2 が形成されている。In the conventional HEMT, a buffer layer 12, an electric conduction layer 13, and a carrier supply layer 14 are formed on a GaAs substrate 11, as shown in FIG. And n + − doped with impurities for reducing source resistance including contact resistance at a high concentration.
A GaAs layer 15 is formed, and a gate electrode 16 is formed on the n + -GaAs layer 15 recessed to set a threshold value to a desired value. The n + -G around the gate electrode 16 is formed.
An insulating film 17 is formed on the aAs layer 15, and n + -Ga
AuGe / is sandwiched between the gate electrodes 16 of the As layer 15.
Au is alloying, the source electrode 18 1 and the drain electrode 18 2 is formed.
【０００５】この合金化処理を行う際に、図４（Ｂ）に
示すように、Ａｕ及びＧｅがｎ+ −ＧａＡｓ層１５中に
拡散し、ｎ+ −ＧａＡｓ層１５とキャリア供給層１４の
厚さに依存する濃度で電気伝導層１３にまで拡散して低
抵抗の電極金属拡散領域１９を形成する。そのため、ｎ
+ −ＧａＡｓ層１５とキャリア供給層１４を通して破線
で示されているような電流が流れ、また、電気伝導層１
３を通して実線で示されているような電流が流れる。[0005] In making alloying process, as shown in FIG. 4 (B), Au and Ge diffuses into the n + -GaAs layer 15, the thickness of the n + -GaAs layer 15 and the carrier supply layer 14 The electrode metal diffusion region 19 having a low resistance is formed by diffusing into the electric conduction layer 13 at a concentration depending on the thickness. Therefore, n
A current as shown by a broken line flows through the + -GaAs layer 15 and the carrier supply layer 14, and the electric conduction layer 1
A current flows as indicated by a solid line through the line 3.
【０００６】図５は、従来のＤＭＴの構成説明図であ。
この図において２１はＧａＡｓ基板、２２はＧａＡｓバ
ッファ層、２３はｎ−ＧａＡｓ層、２４はｉ−ＡｌＧａ
Ａｓ層、２５はｎ+ −ＧａＡｓ層、２６はゲート電極、
２７は絶縁膜、２８1 はソース電極、２８2 はドレイン
電極である。FIG. 5 is a diagram for explaining the configuration of a conventional DMT.
In this figure, 21 is a GaAs substrate, 22 is a GaAs buffer layer, 23 is an n-GaAs layer, and 24 is i-AlGa
As layer, 25 is an n + -GaAs layer, 26 is a gate electrode,
27 insulating film, 28 1 source electrode, 28 2 is a drain electrode.
【０００７】従来の、キャリア走行層にドーピングする
ＤＭＴ（Ｄｏｐｅｄ Ｃｈａｎｎｅｌ ＭＩＳ Ｌｉｋ
ｅ ＦＥＴ）は図５に示すように、ＧａＡｓ基板２１の
上に、ＧａＡｓバッファ層２２、電気伝導層となるｎ−
ＧａＡｓ層２３、ｉ−ＡｌＧａＡｓ層２４が形成され、
その上にしきい値を制御するため及びコンタクト抵抗を
含むソース抵抗を低減するための不純物を高濃度に添加
したｎ+ −ＧａＡｓ層２５が形成され、しきい値を所望
の値に設定するためにリセスされたｎ+ −ＧａＡｓ層２
５にゲート電極２６が形成され、ゲート電極２６の周囲
のｎ+ −ＧａＡｓ層２５の上に絶縁膜２７が形成され、
ｎ+ −ＧａＡｓ層２５のゲート電極２６を挟んだ位置に
ＡｕＧｅ／Ａｕからなるソース電極２８1 とドレイン電
極２８2が合金化処理によって形成されている。A conventional DMT (Doped Channel MIS Lik) for doping a carrier transit layer
e FET), as shown in FIG. 5, a GaAs buffer layer 22 and an n-
A GaAs layer 23 and an i-AlGaAs layer 24 are formed,
An n + -GaAs layer 25 doped with impurities at a high concentration for controlling a threshold value and for reducing a source resistance including a contact resistance is formed thereon, and for setting the threshold value to a desired value. Recessed n + -GaAs layer 2
5, an insulating film 27 is formed on the n + -GaAs layer 25 around the gate electrode 26,
n + source electrode 28 1 and the drain electrode 28 2 made of AuGe / Au in a position sandwiching the gate electrode 26 of the -GaAs layer 25 is formed by alloying.
【０００８】このＤＭＴにおいても、ＨＥＭＴについて
前述したように、ＡｕＧｅ／Ａｕの合金化処理によっ
て、Ａｕ及びＧｅがｎ+ ＧａＡｓ層２５、ｉ−ＡｌＧａ
Ａｓ層２４の厚さに依存する濃度で電気伝導層となるｎ
−ＧａＡｓ層２３にまで拡散して電極金属拡散領域が形
成されるため、電気伝導層となるｎ−ＧａＡｓ層２３と
ソース電極２８1 あるいはドレイン電極２８2 の間に電
流経路が形成される。[0008] In this DMT, as described above for the HEMT, Au and Ge are converted into the n + GaAs layer 25 and the i-AlGa by alloying AuGe / Au.
N serving as an electrically conductive layer at a concentration depending on the thickness of the As layer 24
Since the electrode metal diffusion region is diffused into the -GaAs layer 23 is formed, a current path between the n-GaAs layer 23 becomes electrically conductive layer source electrode 28 1 and the drain electrode 28 2 is formed.
【０００９】[0009]
【発明が解決しようとする課題】しかし、ＨＥＭＴ（図
４参照）においては、ｎ+ −ＧａＡｓ層１５又はキャリ
ア供給層１４が厚い場合、電気伝導層１３まで拡散する
ＡｕおよびＧｅの濃度が低下して、ｎ+ −ＧａＡｓ層１
５とキャリア供給層１４を通して流れる電流は減少す
る。また、電気伝導層１３まで拡散するＡｕおよびＧｅ
の濃度が低下し、ソース電極１８1 とドレイン電極１８
2 から直接電気伝導層１３に流れる電流が少なくなる。
すなわち、オーミック電極であるソース電極１８1 とド
レイン電極１８2 と、電気伝導層１３の間の電気的距離
（抵抗率×距離）が大きくなり、その結果、コンタクト
抵抗が増大する。However, in the HEMT (see FIG. 4), when the n + -GaAs layer 15 or the carrier supply layer 14 is thick, the concentration of Au and Ge which diffuse to the electric conduction layer 13 decreases. And the n + -GaAs layer 1
5 and the current flowing through the carrier supply layer 14 decrease. Au and Ge that diffuse to the electrically conductive layer 13
Of the source electrode 18 1 and the drain electrode 18
The current flowing directly from 2 into the electric conduction layer 13 is reduced.
That is, the source electrode 18 1 and the drain electrode 18 2 is an ohmic electrode, the electrical distance between the electrically conductive layer 13 (resistivity × length) is increased, as a result, the contact resistance increases.
【００１０】また、ヘテロバイポーラトランジスタ（Ｈ
ＢＴ）等の半導体装置のオーミック電極においても、上
記と同様の問題を有している。In addition, a hetero bipolar transistor (H
Ohmic electrodes of semiconductor devices such as BT) also have the same problem as described above.
【００１１】また、ＤＭＴ（図５参照）においては、ｎ
+ −ＧａＡｓ層２５又はｉ−ＡｌＧａＡｓ層２４が厚い
場合、電気伝導層となるｎ−ＧａＡｓ層２３まで拡散す
るＡｕおよびＧｅの濃度が低下して、ソース電極２８1
とドレイン電極２８2 と、電気伝導層となるｎ−ＧａＡ
ｓ層２３の間のコンタクト抵抗が増大する。また、ＤＭ
Ｔはｉ−ＡｌＧａＡｓ層２４を有しているため、図４
（Ｂ）に破線で示す電流径路は存在しない。本発明は、
オーミック電極と電気伝導層の間に高抵抗の半導体層が
存在する場合でも、高濃度不純物添加半導体薄膜を必須
としないでコンタクト抵抗が低い半導体装置を提供する
ことを目的とする。In the DMT (see FIG. 5), n
When the + -GaAs layer 25 or the i-AlGaAs layer 24 is thick, the concentration of Au and Ge diffused to the n-GaAs layer 23 serving as an electric conduction layer decreases, and the source electrode 28 1
N-GaA which and the drain electrode 28 2, the electrically conductive layer
The contact resistance between the s layers 23 increases. Also, DM
Since T has the i-AlGaAs layer 24, FIG.
There is no current path shown by the broken line in (B). The present invention
It is an object to provide a semiconductor device having a low contact resistance without requiring a high-concentration impurity-doped semiconductor thin film even when a high-resistance semiconductor layer exists between an ohmic electrode and an electric conductive layer.
【００１２】[0012]
【課題を解決するための手段】本発明に依る半導体装置
及び半導体装置の製造方法に於いて、物の発明では、 （１） 電気伝導層と、前記電気伝導層上に形成され電極の合金
化処理に依って電極金属が該電気伝導層に充分拡散し得
る膜厚の薄膜を残してリセスされた高抵抗半導体層と、
前記高抵抗半導体層上に形成されソース抵抗を低減させ
る半導体層と、前記高抵抗半導体層を介して前記電気伝
導層に形成されるオーミック電極とを備えてなることを
特徴とするか、或いは、 （２） 電気伝導層上に高抵抗半導体層が積層された構造を有
し、該高抵抗半導体層は該電気伝導層が完全に空乏化し
ない膜厚を有する薄膜を残してリセスされ、 該高抵抗半
導体層を通して該電気伝導層にオーミック電極が形成さ
れてなることを特徴とするか、或いは、 （３） 電気伝導層と、前記電気伝導層上に形成され両端が電極
の合金化処理に依って電極金属が該電気伝導層に充分拡
散し得る膜厚の薄膜を残してリセスされた高抵抗半導体
層と、前記高抵抗半導体層を介して前記電気伝導層に形
成されるオーミック電極とを備えてなることを特徴とす
るか、或いは、 （４）前記（１）乃至（３）の何れか１記載の半導体装置がオ
ーミック電極を備えたＨＥＭＴ、又は、ＤＭＴ、又は、
ＭＥＳＦＥＴてあることを特徴とするか、或いは、方法
の発明では、 （５） 電気伝導層上に高抵抗半導体層が積層された構造に対し
ドライエッチングに依って該高抵抗半導体層の一部をリ
セスし電極を合金化処理する工程に於いて、該電気伝導
層まで電極金属が充分に拡散し、或いは、該電気伝導層
が完全に空乏化しない膜厚の薄膜を残し、該高抵抗半導
体層のリセスした領域にオーミック電極を合金化処理に
依って形成することを特徴とするか、或いは、 （６） 電気伝導層上に高抵抗半導体層が積層された構造に対し
ウエットエッチングに依って該高抵抗半導体層の一部を
リセスし電極を合金化処理する工程に於いて、該電気伝
導層まで電極金属が充分に拡散し、或いは、該電気伝導
層が完全に空乏化しない膜厚の薄膜を残し、該高抵抗半
導体層のリセスした領域にオーミック電極を合金化処理
に依って形成することを特徴とする。 A semiconductor device according to the present invention.
In the method of manufacturing a semiconductor device, the invention of the product includes: (1) an electrically conductive layer and an alloy of an electrode formed on the electrically conductive layer.
The electrode metal can sufficiently diffuse into the electrically conductive layer due to the oxidation treatment.
A high-resistance semiconductor layer recessed leaving a thin film having a thickness of
The source resistance formed on the high resistance semiconductor layer is reduced.
And the electrical conduction through the high-resistance semiconductor layer.
And an ohmic electrode formed on the conductive layer.
Or (2) having a structure in which a high resistance semiconductor layer is laminated on an electric conductive layer.
However, the high-resistance semiconductor layer completely depletes the electric conduction layer.
Leaving a thin film having a no film thickness is recessed, the high resistance and a half
An ohmic electrode is formed on the electrically conductive layer through the conductive layer.
Or (3) an electric conductive layer, and electrodes formed on the electric conductive layer and having both ends formed of electrodes.
The electrode metal is sufficiently spread on the electrically conductive layer by the alloying process of
High-resistivity semiconductor recessed leaving a thin film of dispersible thickness
Layer and the electrically conductive layer via the high resistance semiconductor layer.
And an ohmic electrode formed.
Luke, or (4) the (1) to (3) semiconductor device of any one described is o
HEMT, or DMT, or
MESFET or method
In the invention of (5), a structure in which a high-resistance semiconductor layer is laminated on an electric conductive layer
Part of the high-resistance semiconductor layer is removed by dry etching.
In the process of alloying the
The electrode metal diffuses sufficiently to the layer or the electrically conductive layer
Leaves a thin film with a thickness that does not completely deplete,
Ohmic electrode is alloyed in the recessed region of the body layer
Or (6) a structure in which a high-resistance semiconductor layer is laminated on an electric conductive layer.
A part of the high-resistance semiconductor layer is formed by wet etching.
In the step of recessing and alloying the electrode,
The electrode metal diffuses sufficiently to the conductive layer, or
Leaving a thin film having a thickness that does not completely deplete the layer,
Alloying ohmic electrode in recessed area of conductor layer
Characterized by the following.
【００１３】[0013]
【００１４】[0014]
【００１５】[0015]
【００１６】[0016]
【００１７】[0017]
【作用】オーミック電極の低抵抗化が優先される場合
は、電気伝導層の上に高抵抗半導体層が積層された構造
の高抵抗半導体層を、電極の合金化処理によって電極金
属が電気伝導層に充分に拡散しうる膜厚の薄膜を残して
リセスし、高抵抗半導体層のリセスされた領域にオーミ
ック電極を合金化処理によって形成して、多量の電極金
属を薄い高抵抗半導体層を通して電気伝導層に拡散して
低抵抗の電流経路を形成することができる。When priority is given to lowering the resistance of an ohmic electrode, a high-resistance semiconductor layer having a structure in which a high-resistance semiconductor layer is laminated on an electrical conductive layer is used to form an electrode conductive layer by alloying the electrode. Recessing, leaving a thin film of sufficient thickness to allow diffusion, forming an ohmic electrode in the recessed region of the high-resistance semiconductor layer by alloying, and conducting a large amount of electrode metal through the thin high-resistance semiconductor layer Diffusion into the layer can form a low-resistance current path.
【００１８】これとは逆に、電気伝導層が空乏化される
のを防ぐことが優先される場合は、電気伝導層の上に高
抵抗半導体層が積層された構造の高抵抗半導体層を電気
伝導層が完全に空乏化しない膜厚の薄膜を残してリセス
し、高抵抗半導体層のリセスされた領域を通して電気伝
導層にオーミック電極を形成することができる。On the contrary, when it is a priority to prevent the electric conduction layer from being depleted, the high resistance semiconductor layer having a structure in which the high resistance semiconductor layer is laminated on the electric conduction layer is electrically connected. An ohmic electrode can be formed in the electric conduction layer through the recessed region of the high-resistance semiconductor layer, leaving a thin film whose thickness does not completely deplete the conduction layer.
【００１９】本発明は、電界効果型半導体装置のゲート
電極の下に高抵抗層を介在してゲートリークを低減しよ
うとする場合に特に大きな効果を発揮する。The present invention exerts a particularly great effect when a high resistance layer is interposed under a gate electrode of a field effect type semiconductor device to reduce gate leakage.
【００２０】[0020]
【実施例】以下、本発明の実施例を説明する。図１は、
本発明の一実施例のＤＭＴの構成説明図である。この図
において、１はＧａＡｓ基板、２はＧａＡｓバッファ
層、３はｎ−ＩｎＧａＡｓ層、４はｉ−ＡｌＧａＡｓ
層、５はｎ+ −ＧａＡｓ層、６はゲート電極、７は絶縁
膜、８1 はソース電極、８2 はドレイン電極、９1 ，９
2 は電極金属拡散領域である。Embodiments of the present invention will be described below. FIG.
FIG. 2 is a diagram illustrating the configuration of a DMT according to an embodiment of the present invention. In this figure, 1 is a GaAs substrate, 2 is a GaAs buffer layer, 3 is an n-InGaAs layer, 4 is i-AlGaAs.
Layer, the n + -GaAs layer 5, the gate electrode 6, 7 denotes an insulating film, 8 1 source electrode, 82 drain electrode, 9 1, 9
2 is an electrode metal diffusion region.
【００２１】この実施例のＤＭＴ（Ｄｏｐｅｄ Ｃｈａ
ｎｎｅｌ ＭＩＳ Ｌｉｋｅ ＦＥＴ）は、ＧａＡｓ基
板１の上に、ＧａＡｓバッファ層２、電気伝導層となる
Ｓｉ不純物を添加（ＮD ＝５×１０18ｃｍ-3）した膜厚
１４ｎｍのｎ−ＩｎＧａＡｓ層３、膜厚５０ｎｍのｉ−
ＡｌＧａＡｓ層４が形成され、その上にしきい値を制御
するため及びコンタクト抵抗を含むソース抵抗を低減す
るためのＳｉを添加した（ＮD ＝２×１０18ｃｍ-3）膜
厚５０ｎｍのｎ+ −ＧａＡｓ層５が形成され、しきい値
を所望の値に設定するためにｎ+ −ＧａＡｓ層５をリセ
スした後、ゲート電極６が形成され、ゲート電極６の周
囲のｎ+ −ＧａＡｓ層５の上に絶縁膜７が形成され、ゲ
ート電極６を挟んだ位置のｎ+ −ＧａＡｓ層５とｉ−Ａ
ｌＧａＡｓ層４の一部がリセスされ、このリセスされた
領域のｉ−ＡｌＧａＡｓ層４の上にＡｕＧｅ／Ａｕが蒸
着され、４００℃で１８０秒間加熱して合金化処理を行
ってソース電極８1 とドレイン電極８2 が形成されてい
る。The DMT (Doped Cha) of this embodiment
nnel MIS Like FET) has, on the GaAs substrate 1, GaAs buffer layer 2, addition of Si impurity serving as electrically conductive layer (N D = 5 × 10 18 cm -3) and film thickness 14nm of n-InGaAs layer 3 , 50-nm i-
AlGaAs layer 4 is formed, the upper Si was added to reduce the source resistance including for and contact resistance for controlling the threshold (N D = 2 × 10 18 cm -3) having a thickness of 50 nm n + -GaAs layer 5 is formed, and after n + -GaAs layer 5 is recessed to set the threshold value to a desired value, gate electrode 6 is formed and n + -GaAs layer 5 around gate electrode 6 is formed. An insulating film 7 is formed on the n + -GaAs layer 5 and the i-A
Some of lGaAs layer 4 is recessed, the AuGe / Au on top of recessed regions i-AlGaAs layer 4 is deposited, 400 ° C. in heated for 180 seconds and the source electrode 81 by performing an alloying treatment drain electrode 8 2 is formed.
【００２２】この場合、ｉ−ＡｌＧａＡｓ層４をリセス
する際の残厚は、電気伝導層となるｎ−ＩｎＧａＡｓ層
３が空乏化されず、かつ、このｎ−ＩｎＧａＡｓ層３に
拡散する金属原子の量を低下させない厚さにするため、
要求される特性との兼ね合いによってコンタクト抵抗が
決定される。In this case, the remaining thickness when the i-AlGaAs layer 4 is recessed is such that the n-InGaAs layer 3 serving as an electric conduction layer is not depleted and the metal atoms diffused into the n-InGaAs layer 3 are not depleted. In order not to reduce the amount,
The contact resistance is determined depending on the required characteristics.
【００２３】この実施例のＤＭＴにおいては、ソース電
極８1 とドレイン電極８2 を形成するための、ＡｕＧｅ
／Ａｕの合金化処理によって、Ａｕ及びＧｅがｉ−Ａｌ
ＧａＡｓ層４と電気伝導層となるｎ−ＩｎＧａＡｓ層３
に拡散して電極金属拡散領域９1 ，９2 が形成されるた
め、電気伝導層となるｎ−ＩｎＧａＡｓ層３とソース電
極８1 あるいはドレイン電極８2 の間に低抵抗の電流経
路が形成される。[0023] In the DMT in this embodiment, for forming the source electrode 81 and the drain electrode 8 2, AuGe
Au and Ge become i-Al
GaAs layer 4 and n-InGaAs layer 3 serving as an electrically conductive layer
Since the electrode metal diffusion region 9 1, 9 2 is formed by diffusing, low resistance current path between the n-InGaAs layer 3 and the source electrode 81 or drain electrode 82 serving as the electrically conductive layer is formed You.
【００２４】また、本発明における高抵抗半導体層の一
部および高抵抗半導体層よりも表面側にある半導体層の
リセス工程として、エッチングの選択性や制御性が優れ
たドライエッチングと、制御性にやや欠けるが半導体層
に損傷を与えないウェットエッチングを、目的とする半
導体装置に望まれる特性に応じて選択して適用すること
ができる。In the present invention, a part of the high-resistance semiconductor layer and a recess step of the semiconductor layer on the surface side of the high-resistance semiconductor layer are formed by dry etching having excellent selectivity and controllability. Wet etching, which is slightly chipped but does not damage the semiconductor layer, can be selected and applied depending on characteristics desired for a target semiconductor device.
【００２５】図２は、従来のオーミック電極を用いたＤ
ＭＴの静特性図である。この図の横軸はドレイン電圧Ｖ
DSを示し、１目盛りが２００ｍＶに相当し、縦軸はドレ
イン電流ＩDSを示し、１目盛りが１００μＡに相当す
る。この図に示された従来のオーミック電極を有するＤ
ＭＴの特性は、正常なＦＥＴ特性を示さないことがわか
る。FIG. 2 shows a structure of a conventional ohmic electrode.
It is a static characteristic diagram of MT. The horizontal axis in this figure is the drain voltage V
DS indicates one scale corresponds to 200 mV, and the vertical axis indicates the drain current I DS , and one scale corresponds to 100 μA. D having a conventional ohmic electrode shown in FIG.
It can be seen that the MT characteristics do not show normal FET characteristics.
【００２６】図３は、第１実施例のオーミック電極を用
いたＤＭＴの静特性図である。この図の横軸はドレイン
電圧ＶDSを示し、１目盛りが２００ｍＶに相当し、縦軸
はドレイン電流ＩDSを示し、１目盛りが１ｍＡに相当す
る。この図に示された第１実施例のオーミック電極を有
するＤＭＴの特性は、正常なＦＥＴ特性を示しているこ
とがわかる。FIG. 3 is a static characteristic diagram of the DMT using the ohmic electrode of the first embodiment. The horizontal axis of the diagram shows the drain voltage V DS, 1 graduation corresponds to 200 mV, the vertical axis represents the drain current I DS, 1 graduation corresponds to 1 mA. It can be seen that the characteristics of the DMT having the ohmic electrode of the first embodiment shown in this figure show normal FET characteristics.
【００２７】又、ｇｍについては、従来のオーミック電
極を有するＤＭＴが１５（ｍＳ／ｍｍ）であるのに対し
て、第１実施例のオーミック電極を有するＤＭＴが２０
０（ｍＳ／ｍｍ）で、第１実施例によって著しく改善さ
れていることがわかる。コンタクト抵抗（Ｒｓ）につい
ては、従来のオーミック電極を有するＤＭＴが１５０
（Ω・ｍｍ）であるのに対して、第１実施例のオーミッ
ク電極を有するＤＭＴが２．０（Ω・ｍｍ）であり、第
１実施例によって著しく低減されていることがわかる。Regarding gm, while the DMT having the conventional ohmic electrode is 15 (mS / mm), the DMT having the ohmic electrode of the first embodiment is 20 (mS / mm).
At 0 (mS / mm), it can be seen that the improvement is remarkably improved by the first embodiment. Regarding the contact resistance (Rs), DMT having a conventional ohmic electrode is 150
(Ω · mm), whereas the DMT having the ohmic electrode of the first embodiment is 2.0 (Ω · mm), which is remarkably reduced by the first embodiment.
【００２８】上記の実施例においては、ＤＭＴについて
説明したが、本発明はその他、電気伝導層と比較的高抵
抗の半導体層の積層構造を用いたＨＥＭＴ，ＭＥＳＦＥ
Ｔ，ＭＩＳＦＥＴ等の半導体に適用することができる。Although the DMT has been described in the above embodiments, the present invention is also applicable to HEMTs and MESFES using a laminated structure of an electric conductive layer and a relatively high-resistance semiconductor layer.
It can be applied to semiconductors such as T and MISFET.
【００２９】[0029]
【発明の効果】以上説明したように、本発明によると、
電気伝導層と比較的高抵抗の半導体層の積層構造を用い
た半導体装置に良好なオーミック電極を実現することが
でき、広く半導体装置の特性を改善する上で寄与すると
ころが大きい。As described above, according to the present invention,
A good ohmic electrode can be realized in a semiconductor device using a stacked structure of an electric conductive layer and a semiconductor layer having a relatively high resistance, which greatly contributes to improving characteristics of the semiconductor device.
【図１】本発明の一実施例のＤＭＴの構成説明図であ
る。FIG. 1 is an explanatory diagram of a configuration of a DMT according to an embodiment of the present invention.
【図２】従来のオーミック電極を用いたＤＭＴの静特性
図である。FIG. 2 is a static characteristic diagram of a DMT using a conventional ohmic electrode.
【図３】第１実施例のオーミック電極を用いたＤＭＴの
静特性図である。FIG. 3 is a static characteristic diagram of a DMT using the ohmic electrode of the first embodiment.
【図４】従来のＨＥＭＴの説明図であり、（Ａ）は構成
を示し、（Ｂ）は電流経路を示している。4A and 4B are explanatory diagrams of a conventional HEMT, wherein FIG. 4A shows a configuration, and FIG. 4B shows a current path.
【図５】従来のＤＭＴの構成説明図であ。FIG. 5 is a diagram illustrating the configuration of a conventional DMT.
１ ＧａＡｓ基板 ２ ＧａＡｓバッファ層 ３ ｎ−ＧａＡｓ層 ４ ｉ−ＡｌＧａＡｓ層 ５ ｎ+ −ＧａＡｓ層 ６ ゲート電極 ７ 絶縁膜 ８1 ソース電極 ８2 ドレイン電極 ９1 ，９2 電極金属拡散領域Reference Signs List 1 GaAs substrate 2 GaAs buffer layer 3 n-GaAs layer 4 i-AlGaAs layer 5 n + -GaAs layer 6 gate electrode 7 insulating film 8 1 source electrode 8 2 drain electrode 9 1 , 9 2 electrode metal diffusion region
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平１−220476（ＪＰ，Ａ) 特開 平５−90296（ＪＰ，Ａ) 特開 平５−218096（ＪＰ，Ａ) 特開 平６−204259（ＪＰ，Ａ) 特開 平３−104126（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/778 H01L 29/812 H01L 21/338 H01L 21/28 H01L 29/43 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-220476 (JP, A) JP-A-5-90296 (JP, A) JP-A-5-218096 (JP, A) JP-A-6-206 204259 (JP, A) JP-A-3-104126 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/778 H01L 29/812 H01L 21/338 H01L 21/28 H01L 29/43
Claims (6)
電極金属が該電気伝導層に充分拡散し得る膜厚の薄膜を
残してリセスされた高抵抗半導体層と、 前記高抵抗半導体層上に形成されソース抵抗を低減させ
る半導体層と、 前記高抵抗半導体層を介して前記電気伝導層に形成され
るオーミック電極とを備えてなる ことを特徴とする半導
体装置。An electric conductive layer and an electrode formed on the electric conductive layer are alloyed.
A thin film having a thickness that allows the electrode metal to sufficiently diffuse into the electrically conductive layer
Leaving the recessed high-resistance semiconductor layer, and reducing the source resistance formed on the high-resistance semiconductor layer.
Semiconductor layer, and formed on the electric conductive layer via the high-resistance semiconductor layer.
And a ohmic electrode .
た構造を有し、 該高抵抗半導体層は該電気伝導層が完全に空乏化しない
膜厚を有する薄膜を残してリセスされ、 該高抵抗半導体層を通して該電気伝導層にオーミック電
極が形成されてなることを特徴とする半導体装置。2. A high-resistance semiconductor layer having a structure in which a high-resistance semiconductor layer is laminated on an electric conduction layer , wherein the high-resistance semiconductor layer is recessed except for a thin film having a thickness such that the electric conduction layer is not completely depleted. wherein a the ohmic electrode is formed on the electric conductive layer through the high resistance semiconductor layer.
依って電極金属が該電気伝導層に充分拡散し得る膜厚の
薄膜を残してリセスされた高抵抗半導体層と、 前記高抵抗半導体層を介して前記電気伝導層に形成され
るオーミック電極とを備えてなることを特徴とする半導
体装置。 3. An electrically conductive layer and both ends formed on the electrically conductive layer for alloying the electrodes.
Therefore, the thickness of the electrode metal is such that the electrode metal can sufficiently diffuse into the electric conductive layer.
A high-resistance semiconductor layer recessed to leave a thin film, and formed on the electric conductive layer via the high-resistance semiconductor layer.
Semi-conductor comprising an ohmic electrode
Body device.
する請求項１乃至請求項３の何れか１記載のＨＥＭＴ、
ＤＭＴまたはＭＥＳＦＥＴ。 4. An apparatus comprising an ohmic electrode.
HEMT according to any one of claims 1 to 3,
DMT or MESFET.
た構造に対しドライエッチングに依って該高抵抗半導体
層の一部をリセスし電極を合金化処理する工程に於い
て、 該電気伝導層まで電極金属が充分に拡散し、或いは、該
電気伝導層が完全に空乏化しない膜厚の薄膜を残し、 該高抵抗半導体層のリセスした領域にオーミック電極を
合金化処理に依って形成することを特徴とする半導体装
置の製造方法。5. In contrast the high resistance semiconductor layer on electrically conductive layer are laminated a part of the high resistance semiconductor layer depending on dry etching step of alloying the recesses and electrodes
Then, an electrode metal is sufficiently diffused to the electric conductive layer, or a thin film having a thickness that does not completely deplete the electric conductive layer is left, and an ohmic electrode is alloyed in a recessed region of the high-resistance semiconductor layer. And a method for manufacturing a semiconductor device.
た構造に対しウエットエッチングに依って該高抵抗半導High resistance semiconductor by wet etching
体層の一部をリセスし電極を合金化処理する工程に於いIn the process of recessing part of the body layer and alloying the electrode
て、hand, 該電気伝導層まで電極金属が充分に拡散し、或いは、該The electrode metal is sufficiently diffused to the electrically conductive layer, or
電気伝導層が完全に空乏化しない膜厚の薄膜を残し、Leaving a thin film whose thickness does not completely deplete the electrical conduction layer, 該高抵抗半導体層のリセスした領域にオーミック電極をAn ohmic electrode is formed in the recessed region of the high resistance semiconductor layer.
合金化処理に依って形成することを特徴とする半導体装A semiconductor device characterized by being formed by an alloying process.
置の製造方法。Manufacturing method of the device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20331194A JP3338914B2 (en) | 1994-08-29 | 1994-08-29 | Semiconductor device and method of manufacturing semiconductor device |
| US08/517,041 US5818078A (en) | 1994-08-29 | 1995-08-21 | Semiconductor device having a regrowth crystal region |
| US09/071,888 US6121153A (en) | 1994-08-29 | 1998-05-05 | Semiconductor device having a regrowth crystal region |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20331194A JP3338914B2 (en) | 1994-08-29 | 1994-08-29 | Semiconductor device and method of manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0870117A JPH0870117A (en) | 1996-03-12 |
| JP3338914B2 true JP3338914B2 (en) | 2002-10-28 |
Family
ID=16471932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20331194A Expired - Lifetime JP3338914B2 (en) | 1994-08-29 | 1994-08-29 | Semiconductor device and method of manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3338914B2 (en) |
-
1994
- 1994-08-29 JP JP20331194A patent/JP3338914B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0870117A (en) | 1996-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0330310B2 (en) | ||
| JP3377022B2 (en) | Method of manufacturing heterojunction field effect transistor | |
| JPH0296375A (en) | Semiconductor device | |
| US5532507A (en) | MES field effect transistor possessing lightly doped drain | |
| JP3338914B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JPH02109360A (en) | Semiconductor device | |
| JPH0428149B2 (en) | ||
| US6410946B1 (en) | Semiconductor device with source and drain electrodes in ohmic contact with a semiconductor layer | |
| JP2641189B2 (en) | Field-effect transistor | |
| JP2991297B2 (en) | Field effect transistor and method of manufacturing the same | |
| JP3168968B2 (en) | Field effect transistor and manufacturing method thereof | |
| JP2695832B2 (en) | Heterojunction field effect transistor | |
| KR930007758B1 (en) | Step type high electrton mobility transistor and its manufacturing method | |
| JP2728427B2 (en) | Field effect transistor and its manufacturing method | |
| JPH05343435A (en) | Semiconductor device | |
| JP2004158772A (en) | Fet | |
| JP3311605B2 (en) | Method for manufacturing heterojunction field effect transistor | |
| JPH01155665A (en) | Semiconductor integrated circuit | |
| JPH0737905A (en) | Manufacture of semiconductor device | |
| JPS61102069A (en) | Field-effect transistor | |
| JPH04167531A (en) | Iii-v compound semiconductor device and manufacture thereof | |
| JPS61222176A (en) | Schottky gate field effect transistor and manufacture thereof | |
| JP2000340581A (en) | Semiconductor device and manufacture thereof | |
| JPH04320062A (en) | Semiconductor integrated circuit device | |
| JPS59147465A (en) | Manufacture of schottky-barrier-gate type field-effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20020709 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080816 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090816 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090816 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100816 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110816 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120816 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120816 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130816 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term |