JP3331846B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3331846B2 JP3331846B2 JP34207195A JP34207195A JP3331846B2 JP 3331846 B2 JP3331846 B2 JP 3331846B2 JP 34207195 A JP34207195 A JP 34207195A JP 34207195 A JP34207195 A JP 34207195A JP 3331846 B2 JP3331846 B2 JP 3331846B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- main surface
- igbt
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 230000015556 catabolic process Effects 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 230000003252 repetitive effect Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims 1
- 239000010410 layer Substances 0.000 description 94
- 230000001629 suppression Effects 0.000 description 52
- 238000009826 distribution Methods 0.000 description 22
- 230000005684 electric field Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 6
- 230000001965 increasing effect Effects 0.000 description 6
- 230000006378 damage Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 102100037338 F-box/LRR-repeat protein 5 Human genes 0.000 description 1
- 101001026853 Homo sapiens F-box/LRR-repeat protein 5 Proteins 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、帰還ダイオード及
び過電圧抑制ダイオードを内蔵したＩＧＢＴ、特にイン
バータ用ＩＧＢＴに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IGBT including a feedback diode and an overvoltage suppression diode, and more particularly to an IGBT for an inverter.
【０００２】[0002]
【従来の技術】近年、地球的規模でのエネルギー枯渇が
大きな問題となっており、電気システムの省エネルギー
化が強く求められている。また、産業機器の高度化，複
雑化に伴い、モーター等の駆動機器の高性能化，小型
化，低騒音化，使い勝手の向上等が望まれている。これ
らの要求に応えるために駆動機器のインバータ化が進め
られており、エアコンや照明等の民生用機器分野から、
鉄鋼，電車等の大電力分野に至るまで、インバータが広
く適用されてきている。2. Description of the Related Art In recent years, energy depletion on a global scale has become a major problem, and there is a strong demand for energy saving in electrical systems. Also, with the advancement and complexity of industrial equipment, it is desired that drive equipment such as motors have higher performance, smaller size, lower noise, improved usability, and the like. In order to respond to these demands, inverters in drive equipment are being promoted, and from the field of consumer equipment such as air conditioners and lighting,
2. Description of the Related Art Inverters have been widely applied to large electric power fields such as steel and electric trains.
【０００３】インバータの高性能化のためには、スイッ
チング素子の高性能化が必須である。最近では、サイリ
スタ，ＧＴＯに代わって、絶縁ゲートバイポーラトラン
ジスタ（以下ＩＧＢＴと呼ぶ）が広く用いられるように
なってきている。ＩＧＢＴは、MOSFETの高速スイッチン
グ特性とバイポーラトランジスタの高出力特性とを併せ
持つ素子であり、インバータの省エネルギー化，小型化
等に有効である。In order to improve the performance of an inverter, it is essential to improve the performance of a switching element. Recently, insulated gate bipolar transistors (hereinafter referred to as IGBTs) have been widely used in place of thyristors and GTOs. The IGBT is an element having both the high-speed switching characteristics of a MOSFET and the high output characteristics of a bipolar transistor, and is effective for energy saving and size reduction of an inverter.
【０００４】図２にＩＧＢＴを用いた三相フルブリッジ
インバータの回路を示す。図２において、２００はＩＧ
ＢＴ、２０１は帰還ダイオード、２１０，２１１は直流
電源に接続された直流端子、２１２〜２１４は負荷に接
続された交流端子である。FIG. 2 shows a circuit of a three- phase full-bridge inverter using an IGBT. In FIG. 2, 200 denotes IG
BT, 201 is a feedback diode, 210 and 211 are DC terminals connected to a DC power supply, and 212 to 214 are AC terminals connected to a load.
【０００５】ＩＧＢＴは電圧駆動型素子であるので、イ
ンバータに適用すると駆動回路の小型化，駆動電力の低
減を図れる。また、動作速度が高速であるのでインバー
タを高周波化でき、騒音を低減できる等のメリットがあ
る。これらの理由から、エアコンや照明，熱器具などの
民生機器分野への適用が盛んであり、今後更に、応用分
野を拡大して行くものと考えられる。しかしそのために
は、一層の高信頼化，低コスト化を図る必要がある。[0005] Since the IGBT is a voltage-driven element, when it is applied to an inverter, the drive circuit can be reduced in size and the drive power can be reduced. In addition, since the operation speed is high, there is an advantage that the frequency of the inverter can be increased and noise can be reduced. For these reasons, applications in the field of consumer electronics such as air conditioners, lighting, and heat appliances are prosperous, and it is thought that the fields of application will be further expanded in the future. However, for that purpose, it is necessary to further increase the reliability and reduce the cost.
【０００６】高信頼で低コストのインバータ用ＩＧＢＴ
の実現のために図３に示す回路構成を一体化したＩＧＢ
Ｔが検討されている。図４は図３の回路をＩＧＢＴに内
蔵したときの断面構造を示す図である。図３，図４にお
いて、共通の構成要素には同一の符号を付してある。図
３において、１１０はゲート電極、１１１はエミッタ電
極、１１２は過電圧抑制ダイオードゲート側電極、１１
３は過電圧抑制ダイオードコレクタ側電極、１１５はコ
レクタ電極、１３０は過電圧抑制ダイオード、３００は
ＩＧＢＴ、３０１はゲート−エミッタ間抵抗、３０２は
帰還ダイオードである。また、図４において、１００は
コレクタ層、１０１はバッファ層、102はドリフト層、
１０３はベース層、１０４はソース層、１０５は耐圧保
持のための電界緩和構造（以下これをField Limitting
Ring：ＦＬＲ層と呼ぶ）、１０６はカソード層、１１４
はカソード配線、１２０は層間絶縁膜、１２１は酸化
膜、４００は帰還ダイオードの電流経路を模式的に示し
た矢印、４０１は帰還ダイオードを便宜的に示した記号
である。過電圧抑制用ダイオード１３０は、ｐ型層とｎ
型層とが交互に配列された多結晶シリコンからなり、酸
化膜によりドリフト層１０２からは絶縁されている。こ
のｐ型層とｎ型層の繰り返し配列数はＩＧＢＴの耐圧に
より決まり、一般的には素子耐圧６００ＶのＩＧＢＴ
で、４０〜８０直列程度である。図示してはいないが、
ゲート電極１１０は過電圧抑制用ダイオードゲート側電
極１１２に接続されており、また、これも図示しない
が、ゲート電極１１０とエミッタ電極１１１の間にはゲ
ートエミッタ間抵抗３０１が接続されている。さらに、
ＩＧＢＴセルを形成した領域を導通領域，耐圧保持のた
めの構造を形成した領域を耐圧保持領域と呼ぶ。Highly reliable and low cost inverter IGBT
Integrated with the circuit configuration shown in FIG.
T is being considered. FIG. 4 is a diagram showing a cross-sectional structure when the circuit of FIG. 3 is built in an IGBT. Fig. 3 and Fig. 4
Therefore, common constituent elements are denoted by the same reference numerals. In FIG. 3, 110 is a gate electrode, 111 is an emitter electrode, 112 is an overvoltage suppression diode gate side electrode, 11
Reference numeral 3 denotes an overvoltage suppression diode collector side electrode, 115 denotes a collector electrode, 130 denotes an overvoltage suppression diode, 300 denotes an IGBT, 301 denotes a gate-emitter resistance, and 302 denotes a feedback diode. 4, 100 is a collector layer, 101 is a buffer layer, 102 is a drift layer,
103 is a base layer, 104 is a source layer, and 105 is an electric field relaxation structure for maintaining a withstand voltage (hereinafter referred to as Field Limiting).
Ring: FLR layer), 106 is a cathode layer, 114
Is a cathode wiring, 120 is an interlayer insulating film, 121 is an oxide film, 400 is an arrow schematically showing a current path of a feedback diode, and 401 is a symbol showing a feedback diode for convenience. The overvoltage suppression diode 130 includes a p-type layer and an n-type layer.
The mold layer is made of polycrystalline silicon arranged alternately, and is insulated from the drift layer 102 by the oxide film. The number of repeating arrangements of the p-type layer and the n-type layer is determined by the withstand voltage of the IGBT.
And about 40 to 80 series. Although not shown,
The gate electrode 110 is connected to the overvoltage suppressing diode gate side electrode 112, and a gate-emitter resistor 301 is connected between the gate electrode 110 and the emitter electrode 111, though not shown. further,
The region where the IGBT cell is formed is called a conduction region, and the region where a structure for holding a breakdown voltage is formed is called a breakdown voltage holding region.
【０００７】まず、過電圧抑制ダイオードの動作を簡単
に説明すると、コレクタ―エミッタ間に過電圧が印加さ
れると過電圧抑制ダイオード１３０が降伏し、コレクタ
―ゲート間に電流が流れる。この電流が、ゲート―エミ
ッタ間抵抗３０１を流れることによりゲート電位ＶＧを
上昇させ、ＩＧＢＴをオンして過電圧の上昇を抑制す
る。このダイオードをＩＧＢＴに付加することにより、
過電圧に対するＩＧＢＴの破壊耐量を向上でき、スナバ
レス化等により装置の小型化が図れる。また、図４に示
す構造でＩＧＢＴに内蔵すると、素子の体積を増大させ
ることなくこの機能を付加できる。過電圧抑制機能内蔵
ＩＧＢＴに関しては、特開平2−185069 号に開示になっ
ている。First, the operation of the overvoltage suppression diode will be briefly described. When an overvoltage is applied between the collector and the emitter, the overvoltage suppression diode 130 breaks down and a current flows between the collector and the gate. This current flows through the gate-emitter resistor 301 to increase the gate potential VG, thereby turning on the IGBT and suppressing an increase in overvoltage. By adding this diode to the IGBT,
The breakdown strength of the IGBT against overvoltage can be improved, and the size of the device can be reduced by making it snubberless. Further, if the structure shown in FIG. 4 is incorporated in the IGBT, this function can be added without increasing the volume of the element. An IGBT with a built-in overvoltage suppression function is disclosed in Japanese Patent Application Laid-Open No. H2-185069.
【０００８】次に、帰還ダイオードの動作について説明
する。インバータの回生モードで、ＩＧＢＴに逆バイア
スが印加されると、図３に示した帰還ダイオード３０２
が導通する。この帰還ダイオードは図４のベース層１０
３，ドリフト層１０２の接合部分に形成されており、図
４では４０１で示されている。帰還ダイオードの電流は
経路４００を流れ、コレクタ電極１１３に至る。帰還ダ
イオードをＩＧＢＴに内蔵することにより、従来１２個
の半導体素子で構成されていた図２の三相フルブリッジ
インバータ回路を、６個の半導体素子で構成できること
になり、より小型化が図れる。この様な帰還ダイオード
内蔵ＩＧＢＴは、例えば、特願平２−５１２０３８号に
開示されている。Next, the operation of the feedback diode will be described. When a reverse bias is applied to the IGBT in the regenerative mode of the inverter, the feedback diode 302 shown in FIG.
Becomes conductive. This feedback diode corresponds to the base layer 10 of FIG.
3, formed at the junction of the drift layer 102 and indicated by 401 in FIG. The current of the feedback diode flows through the path 400 and reaches the collector electrode 113 . By incorporating the feedback diode in the IGBT, the three- phase full-bridge inverter circuit shown in FIG. 2 which has conventionally been constituted by 12 semiconductor elements can be constituted by 6 semiconductor elements, and the size can be further reduced. Such an IGBT with a built-in feedback diode is disclosed, for example, in Japanese Patent Application No. 2-512038.
【０００９】以上の、高信頼化と、低コスト化の２つの
方策を同時にＩＧＢＴに実施すれば、信頼性が高く低コ
ストのＩＧＢＴが実現できる。If the above two measures of high reliability and low cost are simultaneously applied to the IGBT, a highly reliable and low cost IGBT can be realized.
【００１０】[0010]
【発明が解決しようとする課題】しかし、上述の過電圧
抑制ダイオード及び帰還ダイオードを内蔵したＩＧＢＴ
には次の問題点がある。However, an IGBT incorporating the above-mentioned overvoltage suppression diode and feedback diode is required.
Has the following problems.
【００１１】第１の問題点は、過電圧抑制用ダイオード
１３０の電位分布とＦＬＲ１０５の電位分布とが一致し
ないために、素子の耐圧が低下するという問題である。
図５(ａ）に過電圧抑制ダイオードによる電位分布を、
(ｂ）にＦＬＲによる電位分布を示す。過電圧抑制ダイ
オードの場合は、ｐ型ｎ型繰り返し層の各々で均等にコ
レクタ−エミッタ間電圧を分担するために、電位分布は
図５（ａ）の５００で示すように均等な等電位線を示
す。これに対して、ＦＬＲ構造の場合は、隣接するＦＬ
Ｒの間隔に依存して等電位線の分布が変化する。一般
に、ＩＧＢＴのＦＬＲでは、安定して耐圧を保持できる
ため、チップ端部に近づく程、電位変化が大きくなる様
な構成をとる場合が多い。The first problem is that the voltage distribution of the overvoltage suppressing diode 130 does not coincide with the voltage distribution of the FLR 105, so that the breakdown voltage of the element is reduced.
FIG. 5A shows the potential distribution by the overvoltage suppression diode,
(b) shows the potential distribution by the FLR. In the case of an overvoltage suppression diode, the potential distribution is set so as to equally share the collector-emitter voltage in each of the p-type and n-type repeating layers.
5 shows a uniform equipotential line as indicated by 500 in FIG . In contrast, in the case of the FLR structure, the adjacent FL
The distribution of equipotential lines changes depending on the interval of R. In general, the FLR of the IGBT can stably maintain a withstand voltage, and thus often has a configuration in which the potential change increases as approaching the end of the chip.
【００１２】しかしながら、過電圧抑制ダイオードとＦ
ＬＲ構造とを同時に適用した図４の構造では、過電圧抑
制ダイオードによる電位分布とＦＬＲによる電位分布が
一致しないため、耐圧が低下するという問題が生じる。
これを図６に示す。図６では、ＦＬＲによる電位の分布
と、過電圧抑制ダイオードによる電位の分布との相互作
用を考慮した電位分布を示す。図６に示すように、両者
の電位分布が一致しないために、電界が集中する箇所が
生じ、降伏現象を引き起こして素子耐圧を低下させると
いう問題点を有する。However, the overvoltage suppression diode and F
In the structure of FIG. 4 to which the LR structure is applied at the same time, the potential distribution by the overvoltage suppression diode and the potential distribution by the FLR do not match, so that a problem that the breakdown voltage is reduced occurs.
This is shown in FIG. FIG. 6 shows a potential distribution in consideration of the interaction between the potential distribution by the FLR and the potential distribution by the overvoltage suppression diode. As shown in FIG. 6, since the potential distributions of the two do not coincide with each other, a portion where the electric field is concentrated occurs, which causes a breakdown phenomenon to cause a problem of lowering the element withstand voltage.
【００１３】第２の問題点として、帰還ダイオードの電
流集中による破壊現象がある。これを図７を用いて説明
する。図７は過電圧抑制ダイオード及び帰還ダイオード
を内蔵したＩＧＢＴチップの平面図、特にチップ角部の
拡大図である。図７において、図２〜６と共通の構成要
素には同一の符号を付してある。図７において、700は
帰還ダイオードの電流を模式的を示す電流線である。図
７から分かるように、チップの角部では帰還ダイオード
の電流密度が、他の場所に比べて高く、通電による温度
上昇が大きくなる。よく知られているように、ダイオー
ドの電流は正の温度特性を持つために、温度上昇と共
に、チップ角部では帰還ダイオードの電流が増加する。
これが正帰還となって、電流は増加し続け、最終的に破
壊に至る。また、チップ角部以外でも、他の場所より電
流が流れやすい箇所があると電流集中を起こし、前述し
た正帰還により、ダイオードが破壊に至るという問題が
ある。As a second problem, there is a destruction phenomenon due to current concentration of the feedback diode. This will be described with reference to FIG. FIG. 7 is a plan view of an IGBT chip having a built-in overvoltage suppression diode and a feedback diode, particularly an enlarged view of a corner of the chip. 7, the same components as those in FIGS. 2 to 6 are denoted by the same reference numerals. In FIG. 7, reference numeral 700 denotes a current line schematically showing the current of the feedback diode. As can be seen from FIG. 7, the current density of the feedback diode is higher at the corners of the chip than at other locations, and the temperature rise due to energization increases. As is well known, since the current of the diode has a positive temperature characteristic, the current of the feedback diode increases at the corner of the chip as the temperature increases.
This becomes positive feedback, the current continues to increase, and eventually leads to destruction. In addition, there is a problem that if there is a portion other than the corner portion of the chip where current flows more easily than other portions, current concentration occurs and the diode is destroyed by the positive feedback described above.
【００１４】本発明の目的は、上述した問題点を解決す
るものであって、過電圧抑制ダイオードとＦＬＲの電位
分布の適正化により耐圧の低下を防止すると共に、帰還
ダイオードの電流集中による破壊を防止し、低コスト，
低損失で且つ信頼性の高いインバータ用ＩＧＢＴを提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to prevent a decrease in withstand voltage by optimizing a potential distribution of an overvoltage suppression diode and an FLR, and to prevent destruction of a feedback diode due to current concentration. And low cost,
An object of the present invention is to provide an inverter IGBT with low loss and high reliability.
【００１５】[0015]
【課題を解決するための手段】上述した問題を解決し、
本発明の目的を達成するための手段として、以下の手段
が考えられる。Means for Solving the Problems To solve the above problems,
The following means are conceivable as means for achieving the object of the present invention.
【００１６】すなわち、一対の主表面を有し、一方の主
表面に接する第１導電型の第１の層と、第１の層と他方
の主表面とに隣接する第２の導電型の第２の層と、一方
の主表面に形成された第１の電極とからなる半導体基体
と、第２の層内に他方の主表面に隣接して選択的に形成
された第１導電型の第３の層と、第３の層内に他方の主
表面に隣接して選択的に形成された第２導電型の第４の
層と、第３の層の他方の主表面の露出部分に絶縁膜を介
して形成された第２の電極と、第３の層と第４の層とに
接触形成された第３の電極とからなるIGBTが繰り返し配
置されたＩＧＢＴ領域と、前記ＩＧＢＴ領域を包囲し
て、前記第２の層内に前記他方の主表面に隣接して選択
的に形成された第１導電型の複数の第５の層と、第２の
層内に前記他方の主表面と前記半導体基体端面とに隣接
して選択的に形成された第２導電型の第６の層と、第６
の層に接触して形成され、前記第１の電極に電気的に接
続された第４の電極と、前記第６の層を除く他方の主表
面に形成された酸化膜と、一方の端部が第２の電極に他
方の端部が第４の電極に接続され、両端部間に繰り返し
配列された複数の第１導電型と第２導電型の層から成
り、前記酸化膜上に形成された多結晶シリコンダイオー
ドとを有する耐圧保持領域とからなる半導体素子におい
て、前記最もＩＧＢＴ領域に近い前記第５の層のＩＧＢ
Ｔ領域側の端部の位置から、最もＩＧＢＴ領域に遠い第
５の層のＩＧＢＴ領域と反対側の端部の位置との距離Ｌ
２が、前記多結晶シリコンダイオードの最もＩＧＢＴ領
域に近い接合から、最もＩＧＢＴより遠い接合までの距
離Ｌ１の４／５以下である。 That is, a first layer of a first conductivity type having a pair of main surfaces and in contact with one main surface, and a second layer of a second conductivity type adjacent to the first layer and the other main surface. A second substrate and a first electrode formed on one main surface; and a first conductive type first electrode formed selectively in the second layer adjacent to the other main surface. A third layer, a fourth layer of the second conductivity type selectively formed in the third layer adjacent to the other main surface, and an insulating portion at an exposed portion of the other main surface of the third layer. An IGBT region in which IGBTs composed of a second electrode formed through a film and a third electrode in contact with the third layer and the fourth layer are repeatedly arranged, and surround the IGBT region; A plurality of fifth layers of the first conductivity type selectively formed adjacent to the other main surface in the second layer; and the other main table in the second layer. A sixth layer of the second conductivity type selectively formed adjacent to the surface and the end face of the semiconductor substrate;
A fourth electrode formed in contact with the first layer and electrically connected to the first electrode; an oxide film formed on the other main surface excluding the sixth layer; Comprises a plurality of layers of the first conductivity type and the second conductivity type, the other end of which is connected to the second electrode and the fourth electrode, and which is repeatedly arranged between both ends, and is formed on the oxide film. In the fifth layer closest to the IGBT region, the semiconductor device comprising: a breakdown voltage holding region having a polycrystalline silicon diode ;
The distance L from the position of the end on the side of the T region to the position of the end on the side opposite to the IGBT region of the fifth layer farthest from the IGBT region.
2 is not more than 4/5 of the distance L1 from the junction closest to the IGBT region of the polycrystalline silicon diode to the junction farthest from the IGBT .
【００１７】また、一対の主表面を有し、一方の主表面
に接する第１導電型の第１の層と、第１の層と他方の主
表面とに隣接する第２の導電型の第２の層と、一方の主
表面に形成された第１の電極とからなる半導体基体と、
第２の層内に他方の主表面に隣接して選択的に形成され
た第１導電型の第３の層と、第３の層内に他方の主表面
に隣接して選択的に形成された第２導電型の第４の層
と、第３の層の他方の主表面の露出部分に絶縁膜を介し
て形成された第２の電極と、第３の層と第４の層とに接
触形成された第３の電極とからなるIGBTが繰り返し配置
されたＩＧＢＴ領域と、前記ＩＧＢＴ領域を包囲して、
前記第２の層内に前記他方の主表面と前記半導体基体端
面とに隣接して選択的に形成された第２導電型の第５の
層と、第５の層に接触して形成され、前記第１の電極に
電気的に接続された第４の電極と、前記第５の層を除く
他方の主表面に形成された酸化膜と、一方の端部が第２
の電極に他方の端部が第４の電極に接続され、両端部間
に繰り返し配列された複数の第１導電型と第２導電型の
層から成り、前記酸化膜上に形成された多結晶シリコン
ダイオードとを有する耐圧保持領域とからなる半導体素
子において、前記多結晶シリコンダイオードの第１導電
型と第２導電型の繰り返し配列の間隔が、第２の電極側
では広く、第４の電極側では狭くなっている手段であ
る。Also, a first layer of a first conductivity type having a pair of main surfaces and in contact with one main surface, and a second layer of a second conductivity type adjacent to the first layer and the other main surface. A semiconductor substrate consisting of two layers and a first electrode formed on one main surface;
A third layer of the first conductivity type selectively formed in the second layer adjacent to the other main surface; and selectively formed in the third layer adjacent to the other main surface. A fourth layer of the second conductivity type, a second electrode formed on an exposed portion of the other main surface of the third layer via an insulating film, and a third layer and a fourth layer. An IGBT region in which an IGBT including a third electrode formed in contact is repeatedly arranged, and an IGBT region surrounding the IGBT region;
A fifth layer of a second conductivity type selectively formed adjacent to the other main surface and the end face of the semiconductor substrate in the second layer, and formed in contact with the fifth layer; A fourth electrode electrically connected to the first electrode; an oxide film formed on the other main surface excluding the fifth layer;
The other end is connected to the fourth electrode, and a plurality of layers of the first conductivity type and the second conductivity type are repeatedly arranged between both ends, and the polycrystal formed on the oxide film In a semiconductor element comprising a breakdown voltage holding region having a silicon diode, the interval between the repetitive arrangements of the first conductivity type and the second conductivity type of the polycrystalline silicon diode is wide on the second electrode side, and the fourth electrode side Then it is a means that is becoming narrower.
【００１８】さらに、前記ＩＧＢＴ領域の端部に位置す
る第４の層に接触し、前記他方の主表面に隣接して選択
的に形成された第１導電型の第７の層を有し、第７の層
が、前記多結晶シリコンダイオードのＩＧＢＴ領域側端
部から最も近い接合よりも、ＩＧＢＴ領域側に形成され
ていることを特徴とする手段である。前記ＩＧＢＴ領域
端部に位置する前記第３の電極と前記第４の層との接触
位置から、前記第７の層の耐圧保持領域側の端部までの
距離Ｌ３が２０μｍ以上有る手段である。A seventh layer of a first conductivity type, which is formed in contact with a fourth layer located at an end of the IGBT region and is selectively formed adjacent to the other main surface; A seventh feature is that the seventh layer is formed closer to the IGBT region than the junction closest to the IGBT region side end of the polycrystalline silicon diode. The distance L3 from the contact position between the third electrode located at the end of the IGBT region and the fourth layer to the end of the seventh layer on the side of the breakdown voltage holding region is at least 20 μm.
【００１９】前記第４の電極に接続された少なくとも１
本以上の第１の配線を有し、前記第１の配線の任意の１
本から最も遠い第４の電極上の第１の点があり、この第
１の点と前記第１の配線の任意の１本との距離Ｌ４と、
前記第４の電極の断面積Ａと、前記第４の電極を流れる
電流Ｉと、第４の電極の抵抗率ρとが、 ０.０３５≧ρ×（Ｌ４／Ａ）×Ｉ／２ を満たす手段である。At least one of the electrodes connected to the fourth electrode
A plurality of first wirings, and any one of the first wirings
There is a first point on the fourth electrode furthest from the book, and a distance L4 between this first point and any one of the first wires;
The sectional area A of the fourth electrode, the current I flowing through the fourth electrode, and the resistivity ρ of the fourth electrode satisfy 0.035 ≧ ρ × (L4 / A) × I / 2. Means.
【００２０】[0020]
【発明の実施の形態】以下、本発明の実施例を図面を参
照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２１】（実施例１）図１に本発明による第１の実
施例の断面構成を示す。図１において、１００はコレク
タ層、１０１はバッファ層、１０２はドリフト層、１０
３はベース層、１０４はソース層、１０５はＦＬＲ層、
１０６はカソード層、１１０はゲート電極、１１１はエ
ミッタ電極、１１２は過電圧抑制ダイオードゲート側電
極、113は過電圧抑制ダイオードコレクタ側電極、１１
４はカソード配線、１１５はコレクタ電極、１２０は層
間絶縁膜、１２１は酸化膜、１３０は過電圧抑制ダイオ
ードである。また、図１で、Ｌ１は過電圧抑制ダイオー
ドの両端部の接合間の距離、Ｌ２は過電圧抑制ダイオー
ドのゲート電極側の端部の接合から、最外周のFLRの終
端までの距離である。(Embodiment 1) FIG. 1 shows a sectional configuration of a first embodiment according to the present invention. In FIG. 1, 100 is a collector layer, 101 is a buffer layer, 102 is a drift layer,
3 is a base layer, 104 is a source layer, 105 is an FLR layer,
106 is a cathode layer, 110 is a gate electrode, 111 is an emitter electrode, 112 is an overvoltage suppression diode gate side electrode, 113 is an overvoltage suppression diode collector side electrode, 11
4 is a cathode wiring, 115 is a collector electrode, 120 is an interlayer insulating film, 121 is an oxide film, and 130 is an overvoltage suppression diode. In FIG. 1, L1 is the distance between the junctions at both ends of the overvoltage suppression diode, and L2 is the distance from the junction at the gate electrode side end of the overvoltage suppression diode to the end of the outermost FLR.
【００２２】本実施例の特徴は、Ｌ１とＬ２が、 Ｌ２≦（４／５）×Ｌ１ …（１） の関係を満たすことである。Ｌ２が上記条件を満たさな
くなったとき、すなわち、 Ｌ２≧（４／５）×Ｌ１ となった時には、耐圧は急激に低下することが、実験的
に確認されている。A feature of this embodiment is that L1 and L2 satisfy the relationship of L2 ≦ (4/5) × L1 (1). It has been experimentally confirmed that when L2 no longer satisfies the above condition, that is, when L2 ≧ (4/5) × L1, the breakdown voltage sharply decreases.
【００２３】式（１）を満たすときには、図５（ｂ）示
したＦＬＲ外周部での電位変化を過電圧抑制ダイオード
が均等化するために図６で示したような電界集中が起こ
らず、耐圧は低下しない。ＦＬＲの電位分布と過電圧抑
制ダイオードの電位分布を一致させるためにはＬ１をＬ
２より２０％程長くすることが効果的である。この時の
電位分布を図８に示す。ＦＬＲ外周では、過電圧抑制ダ
イオードにより電位分布が均等になり、耐圧の劣化を防
止できる。When the equation (1) is satisfied, the overvoltage suppression diode equalizes the potential change at the outer periphery of the FLR shown in FIG. 5B, so that the electric field concentration does not occur as shown in FIG. Does not drop. In order to make the potential distribution of the FLR coincide with the potential distribution of the overvoltage suppression diode, L1 is set to L
It is effective to make the length about 20% longer than 2. FIG. 8 shows the potential distribution at this time. In the outer periphery of the FLR, the potential distribution is made uniform by the overvoltage suppression diode, and the deterioration of the breakdown voltage can be prevented.
【００２４】図９は第１の実施例のＩＧＢＴの平面構成
図である。図２〜図８と共通の構成には同一の符号を付
してある。図９において、９００はゲートワイヤーが接
続されるゲートパッド、９０１はエミッタワイヤーが接
続されるエミッタパッド、９０２はゲート配線である。
過電圧抑制ダイオードは１３０の矢印で示された範囲に
チップ周囲を包囲する形で形成されている。また、FLR1
05は図９においては過電圧抑制ダイオード１３０の下に
形成されており、点線で示してある。また、図示しては
いないが、カソード配線１１４はカソード電極１１３上
の任意の位置に任意の本数だけ接続することが出来る。FIG. 9 is a plan view of the IGBT of the first embodiment. The same components as those in FIGS. 2 to 8 are denoted by the same reference numerals. In FIG. 9, 900 is a gate pad to which a gate wire is connected, 901 is an emitter pad to which an emitter wire is connected, and 902 is a gate wiring.
The overvoltage suppression diode is formed so as to surround the periphery of the chip in a range indicated by an arrow 130. Also, FLR1
05 is formed below the overvoltage suppression diode 130 in FIG. 9 and is indicated by a dotted line. Although not shown, any number of the cathode wires 114 can be connected to an arbitrary position on the cathode electrode 113.
【００２５】本実施例では、過電圧抑制ダイオードのｐ
型ｎ型層の繰り返し配列数６回の例を示したが、勿論こ
れに限定されるものではなく、素子の耐圧に合わせて、
この繰り返し配列数を変化させることが出来る。また同
様に、ＦＬＲに関しても特に３本の場合について示した
が、この本数は何本でも良い。更に、本実施例中ではバ
ッファ層１０１を備えたいわゆるパンチスルー型ＩＧＢ
Ｔの例を示したが、バッファ層を備えていないノンパン
チスルー型ＩＧＢＴの場合も同様に本発明が適用可能で
ある。当然、これらの条件は、以下の実施例でも同様に
考えることが出来る。In this embodiment, the p of the overvoltage suppression diode is
Although an example in which the number of repetitive arrangements of the type n-type layer is six has been described, it is needless to say that the present invention is not limited to this.
The number of repeating sequences can be changed. Similarly, the number of FLRs is three, but the number of FLRs is not limited. Further, in this embodiment, a so-called punch-through type IGB having the buffer layer 101 is used.
Although the example of T is shown, the present invention is similarly applicable to a non-punch-through IGBT having no buffer layer. Naturally, these conditions can be similarly considered in the following embodiments.
【００２６】（実施例２） 図１０は本発明による第２の実施例を示す平面構成図で
ある。図１０において図２〜図９間と共通の構成要素に
は同一の符号を付してある。図１０において、図９と異
なる点は、過電圧抑制ダイオード１０００がゲートパッ
ドに隣接した領域にだけ形成されている点である。過電
圧抑制ダイオードの幅Ｌ１は実施例１でも述べたよう
に、ＦＬＲの幅Ｌ２よりも大きくしておかなければなら
ない。そのため、ＦＬＲだけの耐圧保持領域の構造より
も寸法が大きくなる。これに対し、本実施例では過電圧
抑制ダイオードをゲートパッドに隣接した領域に限定し
たことにより、この面積の損失を低減できる。つまり、
過電圧抑制ダイオードが形成されていない領域では耐圧
保持領域の面積を低減でき、素子サイズを縮小すること
が出来る。(Embodiment 2) FIG. 10 is a plan view showing a second embodiment of the present invention. In FIG. 10, the same components as those in FIGS. 2 to 9 are denoted by the same reference numerals. 10 differs from FIG. 9 in that the overvoltage suppression diode 1000 is formed only in a region adjacent to the gate pad. As described in the first embodiment, the width L1 of the overvoltage suppression diode must be larger than the width L2 of the FLR. Therefore, the size is larger than the structure of the breakdown voltage holding region including only the FLR. On the other hand, in this embodiment, the loss of this area can be reduced by limiting the overvoltage suppression diode to the region adjacent to the gate pad. That is,
In the region where the overvoltage suppression diode is not formed, the area of the breakdown voltage holding region can be reduced, and the element size can be reduced.
【００２７】しかしながら、本実施例による過電圧抑制
ダイオードは、素子サイズを縮小したために、ダイオー
ドの抵抗成分が増加し、過電圧抑制動作の遅れや、損失
を増加させることになる。そのため、素子面積の低減が
重要な場合と、過電圧動作の遅れや損失を低減が重要な
場合とで、実施例１もしくは実施例２の一方の適当な構
造を選択する必要がある。本実施例では、過電圧抑制ダ
イオード１０００をゲートパッド脇に形成した例を示し
たが、過電圧抑制ダイオードの位置はこれに限定される
ものではなが、ゲートパッドに隣接して形成した場合に
は、ゲートパッドから過電圧抑制ダイオードまでの配線
が短くなり、配線に生じる寄生容量や寄生インダクタン
スの影響を最小に出来るというメリットがある。However, in the overvoltage suppressing diode according to the present embodiment, since the element size is reduced, the resistance component of the diode increases, and the delay of the overvoltage suppressing operation and the loss increase. Therefore, it is necessary to select an appropriate structure of the first embodiment or the second embodiment depending on the case where the reduction of the element area is important and the case where the delay or loss of the overvoltage operation is important. In this embodiment, the example in which the overvoltage suppression diode 1000 is formed beside the gate pad is shown. However, the position of the overvoltage suppression diode is not limited to this, but when the overvoltage suppression diode is formed adjacent to the gate pad, There is an advantage that the wiring from the gate pad to the overvoltage suppression diode can be shortened, and the effect of parasitic capacitance and parasitic inductance generated on the wiring can be minimized.
【００２８】（実施例３）図１１は本発明による第３の
実施例を示す断面構成である。図１１において、図１か
ら図１０までと共通の構成要素には同一の符号を付して
ある。本実施例の特徴は、過電圧抑制ダイオードのｐ型
ｎ型層の繰り返し配列間隔を調整する事により、過電圧
抑制ダイオードに高い電界緩和効果を持たせ、ＦＬＲを
削除して内蔵の帰還ダイオードの抵抗を低減した点にあ
る。(Embodiment 3) FIG. 11 is a sectional view showing a third embodiment of the present invention. In FIG. 11, the same components as those in FIGS. 1 to 10 are denoted by the same reference numerals. The feature of the present embodiment is that by adjusting the repetitive arrangement interval of the p-type and n-type layers of the overvoltage suppression diode, the overvoltage suppression diode has a high electric field relaxation effect, the FLR is eliminated, and the resistance of the built-in feedback diode is reduced. The point is that it has been reduced.
【００２９】帰還ダイオードの電流は図４の４００で示
される経路を流れるため、ＦＬＲ層１０５が大きな抵抗
となっている。帰還ダイオードの抵抗の低減のためには
このＦＬＲ層１０５を削除する必要があるが、これを削
除してしまうと、十分な耐圧が得られないことが分かっ
ている。これは、過電圧抑制ダイオードの電界緩和効果
がドリフト層内部までは及ばず、表面から数μｍ以上深
いドリフト層領域では、電界集中が発生してしまうため
である。この傾向は、高耐圧のＩＧＢＴ、つまり耐圧保
持領域長が大きいＩＧＢＴで顕著となる。Since the current of the feedback diode flows through the path indicated by 400 in FIG. 4, the FLR layer 105 has a large resistance. In order to reduce the resistance of the feedback diode, it is necessary to delete the FLR layer 105. However, it has been found that if this is deleted, a sufficient withstand voltage cannot be obtained. This is because the electric field relaxation effect of the overvoltage suppression diode does not reach the inside of the drift layer, and electric field concentration occurs in a drift layer region several μm or more from the surface. This tendency is remarkable in an IGBT having a high withstand voltage, that is, an IGBT having a long withstand voltage holding region.
【００３０】そこで、本実施例では、過電圧抑制ダイオ
ードのｐ型ｎ型層の繰り返し配列間隔を、チップ端部に
近づくほど狭くし、過電圧抑制ダイオードの電界緩和効
果の強化を実現する。チップ外周部に近づくほど配列間
隔を狭くすることにより、ドリフト層内部での電界集中
を緩和することが可能となり、実施例２の構成よりも高
耐圧品に適用できる。但し、本実施例では実施例１，２
の構成に比べ耐圧保持領域幅が増加するために、チップ
サイズが増加してしまう。このため、帰還ダイオードの
損失低減を重視するか、あるいはチップサイズの縮小を
重視するかにより、選択する必要がある。Therefore, in the present embodiment, the repetitive arrangement interval of the p-type and n-type layers of the overvoltage suppression diode is made narrower as approaching the end of the chip, thereby enhancing the electric field relaxation effect of the overvoltage suppression diode. By narrowing the arrangement interval closer to the outer peripheral portion of the chip, it becomes possible to reduce the electric field concentration inside the drift layer, and it can be applied to a higher breakdown voltage product than the configuration of the second embodiment. However, in this embodiment, the first and second embodiments are used.
Since the width of the breakdown voltage holding region is increased as compared with the configuration of the above, the chip size is increased. Therefore, it is necessary to make a selection depending on whether importance is placed on reducing the loss of the feedback diode or reducing the chip size.
【００３１】（実施例４）図１２に本発明による第４の
実施例を示す。図１２において、図１から図１１と共通
の構成要素には同一の符号を付してある。図１２におい
て、１２００はウェル層である。本実施例の特徴は、ウ
ェル層１２００の終端が、過電圧抑制ダイオードのゲー
ト電極側端部の接合１２０１よりも導通領域側にある点
である。ウェル層１２００が、上記接合を越えてチップ
外周部に伸びるとウェル層１２００の端部で電界集中が
発生し、素子の耐圧を低下させる。これを図１３（ａ）
に示す。本発明の場合は図１３（ｂ）に示す様に電界は
緩和され、素子耐圧の低下を防止できる。(Embodiment 4) FIG. 12 shows a fourth embodiment according to the present invention. 12, the same components as those in FIGS. 1 to 11 are denoted by the same reference numerals. In FIG. 12, 1200 is a well layer. The feature of this embodiment is that the end of the well layer 1200 is closer to the conduction region than the junction 1201 at the gate electrode side end of the overvoltage suppression diode. When the well layer 1200 extends to the outer periphery of the chip beyond the junction, electric field concentration occurs at the end of the well layer 1200, and the breakdown voltage of the element is reduced. This is shown in FIG.
Shown in In the case of the present invention, the electric field is relaxed as shown in FIG.
【００３２】（実施例５）図１４に本発明による第５の
実施例の断面構成を示す。図１４において、図１から図
１３と共通の構成要素には同一の符号を付してある。本
実施例の特徴は、導通領域端部のベース層１０３及びウ
ェル層１２００とエミッタ電極１１１とのコンタクト部
から、ウェル層１２００の耐圧保持領域側の端部までの
距離Ｌ３が２０μｍ以上である点である。図７で説明し
たように、チップの角部では電流集中により素子の破壊
が起こりやすくなる。また、チップ角部以外でも、電流
が集中し易い箇所は、正帰還により素子が破壊しやす
い。(Embodiment 5) FIG. 14 shows a sectional configuration of a fifth embodiment according to the present invention. 14, the same components as those in FIGS. 1 to 13 are denoted by the same reference numerals. This embodiment is characterized in that the distance L3 from the contact portion between the base layer 103 and the well layer 1200 at the end of the conduction region and the emitter electrode 111 to the end of the well layer 1200 on the side of the breakdown voltage holding region is 20 μm or more. It is. As described with reference to FIG. 7, at the corners of the chip, the elements are liable to break down due to current concentration. In addition, other than the corners of the chip, elements where the current tends to concentrate are apt to be broken by positive feedback.
【００３３】本実施例では、Ｌ３を２０μｍ以上とする
ことにより、ウェル層１２００での抵抗を増大させ、ダ
イオードの正帰還を抑制している。具体的に説明する
と、ウェル層１２００の抵抗は温度上昇につれて増大す
るため、ウェル層１２００の抵抗を大きくすると、温度
上昇に伴う抵抗の増分も大きくなる。この抵抗の増分が
ダイオードの正帰還による電流増加を抑制する効果を持
つため、ウェル層1200の抵抗が大きい程、この効果が顕
著となる。一般的なＩＧＢＴのウェル層の場合、不純物
濃度は約１×１０18〜１×１０20程度であり、この値を
考慮して、計算によりＬ３の値を求めると、Ｌ３≧２０
μｍとなる。これにより、チップ角部及び、電流集中箇
所での破壊を防止できる。In the present embodiment, by setting L3 to 20 μm or more, the resistance in the well layer 1200 is increased, and the positive feedback of the diode is suppressed. More specifically, the resistance of the well layer 1200 increases as the temperature rises. Therefore, when the resistance of the well layer 1200 is increased, the resistance increases with the temperature rise. Since this increase in resistance has the effect of suppressing an increase in current due to positive feedback of the diode, this effect becomes more pronounced as the resistance of the well layer 1200 increases. For a typical IGBT well layer, the impurity concentration is about 1 × 10 18 ~1 × 10 20 mm, this value in consideration, when determining the value of L3 by calculation, L3 ≧ 20
μm. As a result, it is possible to prevent destruction at the corners of the chip and at the current concentrated portions.
【００３４】（実施例６） 図１５は本発明を適用した第６の実施例を示す平面構成
である。図１５において、図１から図１４と共通の構成
要素には同一の符号が付してある。図１５において、チ
ップの４つの角をそれぞれ角Ａ〜Ｄとし、チップの一辺
の長さをＬ４，カソード電極１１３を流れる電流をＩ
１、そして、帰還ダイオードに流れる電流をＩ２とす
る。(Embodiment 6) FIG. 15 is a plan view showing a sixth embodiment of the present invention. In FIG. 15 , the same components as those in FIGS. 1 to 14 are denoted by the same reference numerals. In FIG. 15, the four corners of the chip are referred to as corners A to D, the length of one side of the chip is L4, and the current flowing through the cathode electrode 113 is I
1, and the current flowing through the feedback diode is I2.
【００３５】本実施例の特徴は、カソード電極１１３の
断面積ＡとＬ４との関係が、 ０.０３５（Ｖ）≧Ｖ１×２＝ρ×（２×Ｌ４／Ａ）×Ｉ１／２ …（２） を満たす点である。式（２）において、ρは電極の抵抗
率である。帰還ダイオードを内蔵したＩＧＢＴの場合、
カソード配線１１４とカソード電極１１３の接続箇所を
チップの角にする場合が多い。これは、チップの角はカ
ソード電極の面積が大きいためである。カソード配線は
各４角にそれぞれ接続することが望ましいが、パッケー
ジの制約により、図１５のようにカソード配線１本の場
合も考慮する必要がある。この場合、カソード配線の接
続点がある角Ｃから最も遠い角Ｂでは、電流Ｉ１により
角Ｃよりも電位が高くなる。この角Ｂ−角Ｃ間の電圧
は、カソード配線が複数の角に接続されている場合には
小さいが図１５のように配線が１本の場合には最大とな
る。このためこれ以降は、カソード配線一本の場合につ
いて検討する。図１５において、角Ｂの電位は角Ｃの電
位より、Ｖ１×２だけ高くなる。この電位差は、帰還ダ
イオードの電流Ｉ２に分布を生じさせる。なぜなら、角
Ｂでは角Ｃよりも電位が高いために帰還ダイオードに印
加される電圧が最も小さくなって電流が流れにくく、ま
た角Ｃでは最も電流が流れやすい。この電位差が、ダイ
オードの順方向電圧降下０.７Ｖの５％、つまり０.０３
５Ｖを越えると、電流集中箇所による正帰還が顕著とな
り、破壊に至る。この時の、Ｌ４，Ｉ１，Ｖ１，Ａの関
係を求めると式（２）が得られる。本実施例の１０Ａ級
のＩＧＢＴの場合について、計算の一例を示す。１０Ａ
級のＩＧＢＴの場合、帰還ダイオードの電流も１０Ａと
なり、Ｉ１はこの１０Ａの半分であるので、５Ａとな
る。また、チップサイズは一般的には１cm×１cm程度で
あり、２×Ｌ４＝２cmである。カソード電極をアルミで
形成しているので、この抵抗率が５μΩ・cmであり、断
面積Ａ＝７.５×１０-3cm2 であるので、式（２）を満た
す。This embodiment is characterized in that the relationship between the cross-sectional area A and L4 of the cathode electrode 113 is as follows: 0.035 (V) ≧ V1 × 2 = ρ × (2 × L4 / A) × I1 / 2 ( 2) is satisfied. In equation (2), ρ is the resistivity of the electrode. In the case of an IGBT with a built-in feedback diode,
In many cases, the connection point between the cathode wiring 114 and the cathode electrode 113 is set at the corner of the chip. This is because the corner of the tip has a large area of the cathode electrode. Although it is desirable to connect the cathode wires to each of the four corners, it is necessary to consider the case of one cathode wire as shown in FIG. In this case, at the angle B farthest from the angle C where the connection point of the cathode wiring is located, the potential becomes higher than the angle C due to the current I1. The voltage between the corners B and C is small when the cathode wiring is connected to a plurality of corners, but becomes maximum when there is only one wiring as shown in FIG. Therefore, hereinafter, the case of one cathode wiring will be considered. In FIG. 15, the potential at the corner B is higher than the potential at the corner C by V1 × 2. This potential difference causes a distribution in the current I2 of the feedback diode. This is because the voltage applied to the feedback diode is the smallest at the angle B and the current is less likely to flow because the potential is higher than the angle C, and the current is most likely to flow at the angle C. This potential difference is 5% of the forward voltage drop of 0.7 V of the diode, that is, 0.03.
When the voltage exceeds 5 V, positive feedback due to a current concentrated portion becomes remarkable, leading to destruction. When the relationship among L4, I1, V1, and A at this time is obtained, Expression (2) is obtained. An example of calculation will be described for the case of a 10A class IGBT of the present embodiment . 10A
In the case of a class IGBT, the current of the feedback diode is also 10 A, and since I1 is half of this 10 A, it is 5 A. The chip size is generally about 1 cm × 1 cm, Ru 2 × L4 = 2 cm der. Since the cathode electrode is formed of aluminum, the resistivity is 5μΩ · cm, since the cross-sectional area A = 7.5 × 10 -3 cm 2 , satisfy formula (2)
You .
【００３６】カソード配線を各角に設けた場合も同様に
考えられる。これを図１６に示す。例えば、４角に設け
た場合には図１６に示すように、Ｉ１が図１５の場合の
１／４となり、また、Ｉ１が流れる経路Ｌ５も図１５の
場合の１／４になるために、カソード配線１本の場合に
比べてこの場合は発生する電圧は１／１６と小さくな
る。The same applies to the case where the cathode wiring is provided at each corner. This is shown in FIG. For example, as shown in FIG. 16, when provided at four corners, I1 is １ ／ of that in FIG. 15 , and the path L5 through which I1 flows is also shown in FIG.
In this case, the generated voltage is 1/16, which is smaller than that in the case of one cathode wiring.
【００３７】従って、カソード配線が１本の場合に式
（２）を満たせば、カソード配線が２本以上の場合も式
（２）の条件を満たす。Therefore, if the equation (2) is satisfied when the number of cathode wirings is one, the condition of the equation (2) is satisfied even when the number of cathode wirings is two or more.
【００３８】[0038]
【発明の効果】本発明によれば、耐圧保持領域における
ＦＬＲ形成領域の幅を過電圧抑制ダイオードの両接合端
間距離の４／５とすることにより、電位分布の不整合を
解消し、素子耐圧の低下を防止する。According to the present invention, the width of the FLR formation region in the breakdown voltage holding region is set to 4/5 of the distance between the two junction ends of the overvoltage suppression diode, thereby eliminating the potential distribution mismatch and the device breakdown voltage. To prevent a drop.
【００３９】また、本発明によれば、ウェル層の耐圧保
持領域側端部とエミッタ電極とのコンタクトとの距離を
２０μｍ以上とすることにより、帰還ダイオードのチッ
プ内での電流不均一、特にチップ角部での電流集中によ
る破壊を防止できる。Further, according to the present invention, the distance between the end of the well layer on the side of the breakdown voltage holding region and the contact between the emitter electrode and the emitter electrode is set to 20 μm or more, so that the current in the feedback diode chip becomes non-uniform, Breakage due to current concentration at the corners can be prevented.
【００４０】更に、本発明によれば、カソード配線の断
面積とチップサイズとの関係を式（２）で表される関係
にすることにより帰還ダイオードの電流集中を低減し、
高破壊耐量の帰還ダイオードを実現できる。Further, according to the present invention, the current concentration of the feedback diode is reduced by making the relationship between the cross-sectional area of the cathode wiring and the chip size into the relationship represented by the equation (2).
A feedback diode with high breakdown resistance can be realized.
【００４１】これらの発明により、高破壊耐量の帰還ダ
イオードを内蔵したＩＧＢＴを実現でき、高破壊耐量
で、低コストのインバータシステムを実現できる。According to these inventions, it is possible to realize an IGBT having a built-in feedback diode with a high breakdown strength, and a low-cost inverter system with a high breakdown strength.
【図１】本発明による第１の実施例を示す断面構造図で
ある。FIG. 1 is a sectional structural view showing a first embodiment according to the present invention.
【図２】従来のインバータの回路図である。FIG. 2 is a circuit diagram of a conventional inverter.
【図３】従来の過電圧抑制ダイオード内蔵ＩＧＢＴの回
路図である。FIG. 3 is a circuit diagram of a conventional IGBT with a built-in overvoltage suppression diode.
【図４】従来の過電圧抑制ダイオード内蔵ＩＧＢＴの断
面図である。FIG. 4 is a cross-sectional view of a conventional IGBT with a built-in overvoltage suppression diode.
【図５】従来の帰還ダイオード内蔵ＩＧＢＴの断面図で
ある。FIG. 5 is a cross-sectional view of a conventional feedback diode built-in IGBT.
【図６】過電圧抑制ダイオード及び帰還ダイオードを内
蔵した従来のＩＧＢＴの断面図である。FIG. 6 is a cross-sectional view of a conventional IGBT including an overvoltage suppression diode and a feedback diode.
【図７】従来の過電圧抑制ダイオード及びＦＬＲの電位
分布を示す断面図である。FIG. 7 is a cross-sectional view showing a potential distribution of a conventional overvoltage suppression diode and FLR.
【図８】過電圧抑制ダイオード及び帰還ダイオードを内
蔵した従来のＩＧＢＴの電位分布を示す断面図である。FIG. 8 is a cross-sectional view showing a potential distribution of a conventional IGBT including an overvoltage suppression diode and a feedback diode.
【図９】従来の帰還ダイオードの問題を説明する平面図
である。FIG. 9 is a plan view illustrating a problem of a conventional feedback diode.
【図１０】本発明による第１の実施例を示す平面図であ
る。FIG. 10 is a plan view showing a first embodiment according to the present invention.
【図１１】本発明による第１の実施例による電位分布を
示す断面図である。FIG. 11 is a sectional view showing a potential distribution according to the first embodiment of the present invention.
【図１２】本発明による第１の実施例の補足説明図であ
る。FIG. 12 is a supplementary explanatory diagram of the first embodiment according to the present invention.
【図１３】本発明による第２の実施例を示す断面図であ
る。FIG. 13 is a sectional view showing a second embodiment according to the present invention.
【図１４】本発明による第３の実施例を示す平面図であ
る。FIG. 14 is a plan view showing a third embodiment according to the present invention.
【図１５】本発明による第３の実施例の補足説明図であ
る。FIG. 15 is a supplementary explanatory diagram of the third embodiment according to the present invention.
【図１６】本発明による第４の実施例を示す平面図であ
る。FIG. 16 is a plan view showing a fourth embodiment according to the present invention.
１００…コレクタ層、１０１…バッファ層、１０２…ド
リフト層、１０３…ベース層、１０４…ソース層、１０
５…ＦＬＲ層、１０６…カソード層、１１０…ゲート電
極、１１１…エミッタ電極、１１２…過電圧抑制ダイオ
ードゲート側電極、１１３…過電圧抑制ダイオードコレ
クタ側電極、１１４…カソード配線、１１５…コレクタ
電極、１２０…層間絶縁膜、１２１…酸化膜、１３０…
過電圧抑制ダイオード、２００，３００…ＩＧＢＴ、２
０１…帰還ダイオード、２１０，２１１…直流端子、２
１２，２１３，２１４…交流端子、３０１…ゲート−エ
ミッタ間抵抗、４００…帰還ダイオード電流経路、４０
１…帰還ダイオード記号、５００…過電圧抑制ダイオー
ドによる等電位線、５０１…ＦＬＲによる等電位線、７
００…帰還ダイオードの電流線、９００…ゲートパッ
ド、９０１…エミッタパッド、９０２…ゲート配線、１
０００…ゲートパッドに隣接した過電圧抑制ダイオー
ド、１２００…ウェル層。100: collector layer, 101: buffer layer, 102: drift layer, 103: base layer, 104: source layer, 10
5 FLR layer, 106 cathode layer, 110 gate electrode, 111 emitter electrode, 112 overvoltage suppression diode gate side electrode, 113 overvoltage suppression diode collector side electrode, 114 cathode wiring, 115 collector electrode, 120 Interlayer insulating film, 121 ... oxide film, 130 ...
Overvoltage suppression diode, 200, 300 ... IGBT, 2
01: feedback diode, 210, 211: DC terminal, 2
12, 213, 214 ... AC terminal, 301 ... gate-emitter resistance, 400 ... feedback diode current path, 40
Reference numeral 1 represents a feedback diode symbol, 500 represents equipotential lines formed by overvoltage suppression diodes, 501 represents equipotential lines formed by FLR, 7
00: feedback diode current line, 900: gate pad, 901: emitter pad, 902: gate wiring, 1
000: overvoltage suppression diode adjacent to the gate pad, 1200: well layer.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−196706（ＪＰ，Ａ) 特開 平７−249765（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 21/336 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-196706 (JP, A) JP-A-7-249765 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/78 H01L 21/336
Claims (4)
る第１導電型の第１の層と、第１の層と他方の主表面と
に隣接する第２の導電型の第２の層と、一方の主表面に
形成された第１の電極とからなる半導体基体と、 第２の層内に他方の主表面に隣接して選択的に形成され
た第１導電型の第３の層と、第３の層内に他方の主表面
に隣接して選択的に形成された第２導電型の第４の層
と、第３の層の他方の主表面の露出部分に絶縁膜を介し
て形成された第２の電極と、第３の層と第４の層とに接
触形成された第３の電極とからなるIGBTが繰り返し配置
されたＩＧＢＴ領域と、 前記ＩＧＢＴ領域を包囲して、 前記第２の層内に前記他方の主表面に隣接して選択的に
形成された第１導電型の単数または複数の第５の層と、
第２の層内に前記他方の主表面と前記半導体基体端面と
に隣接して選択的に形成された第２導電型の第６の層
と、第６の層に接触して形成され、前記第１の電極に電
気的に接続された第４の電極と、前記第６の層を除く他
方の主表面に形成された酸化膜と、一方の端部が第２の
電極に他方の端部が第４の電極に接続され、両端部間に
繰り返し配列された複数の第１導電型と第２導電型の層
から成り、前記酸化膜上に形成された多結晶シリコンダ
イオードとを有する耐圧保持領域とからなる半導体素子
において、 前記多結晶シリコンダイオードのＩＧＢＴ側の端部の接
合から、最外周の前記第５の層の終端までの距離Ｌ２
が、前記多結晶シリコンダイオードの最もIGBT領域に近
い接合から、最もＩＧＢＴより遠い接合までの距離Ｌ１
の４／５以下であることを特徴とする半導体装置。1. A first layer of a first conductivity type having a pair of main surfaces and in contact with one main surface, and a second layer of a second conductivity type adjacent to the first layer and the other main surface. A second substrate and a first electrode formed on one main surface; and a first conductive type first formed selectively adjacent to the other main surface in the second layer. A third layer, a fourth layer of the second conductivity type selectively formed in the third layer adjacent to the other main surface, and an insulating portion at an exposed portion of the other main surface of the third layer. An IGBT region in which an IGBT including a second electrode formed through a film and a third electrode in contact with the third layer and the fourth layer is repeatedly arranged; and surrounding the IGBT region. And one or more fifth layers of the first conductivity type selectively formed adjacent to the other main surface in the second layer;
A sixth layer of a second conductivity type selectively formed adjacent to the other main surface and the end face of the semiconductor substrate in a second layer; and a sixth layer formed in contact with the sixth layer; A fourth electrode electrically connected to the first electrode, an oxide film formed on the other main surface excluding the sixth layer, one end of which is connected to the second electrode by the other end; Is connected to a fourth electrode and is made up of a plurality of layers of the first conductivity type and the second conductivity type repeatedly arranged between both ends, and has a polycrystalline silicon diode formed on the oxide film. A region of the polycrystalline silicon diode on the IGBT side.
From the end to the end of the fifth outermost layer, L2
Is the distance L1 from the junction closest to the IGBT region of the polysilicon diode to the junction farthest from the IGBT.
A semiconductor device characterized in that the ratio is not more than 4/5.
る第１導電型の第１の層と、第１の層と他方の主表面と
に隣接する第２の導電型の第２の層と、一方の主表面に
形成された第１の電極とからなる半導体基体と、 第２の層内に他方の主表面に隣接して選択的に形成され
た第１導電型の第３の層と、第３の層内に他方の主表面
に隣接して選択的に形成された第２導電型の第４の層
と、第３の層の他方の主表面の露出部分に絶縁膜を介し
て形成された第２の電極と、第３の層と第４の層とに接
触形成された第３の電極とからなるIGBTが繰り返し配置
されたＩＧＢＴ領域と、 前記ＩＧＢＴ領域を包囲して、 前記第２の層内に前記他方の主表面と前記半導体基体端
面とに隣接して選択的に形成された第２導電型の第５の
層と、第５の層に接触して形成され、前記第１の電極に
電気的に接続された第４の電極と、前記第５の層を除く
他方の主表面に形成された酸化膜と、一方の端部が第２
の電極に他方の端部が第４の電極に接続され、両端部間
に繰り返し配列された複数の第１導電型と第２導電型の
層から成り、前記酸化膜上に形成された多結晶シリコン
ダイオードとを有する耐圧保持領域とからなる半導体素
子において、 前記多結晶シリコンダイオードの第１導電型と第２導電
型の繰り返し配列の間隔が、第２の電極側では広く、第
４の電極側では狭くなっていることを特徴とする半導体
装置。2. A first conductive type first layer having a pair of main surfaces and being in contact with one main surface, and a second conductive type first layer adjacent to the first layer and the other main surface. A second substrate and a first electrode formed on one main surface; and a first conductive type first formed selectively adjacent to the other main surface in the second layer. A third layer, a fourth layer of the second conductivity type selectively formed in the third layer adjacent to the other main surface, and an insulating portion at an exposed portion of the other main surface of the third layer. An IGBT region in which an IGBT including a second electrode formed through a film and a third electrode in contact with the third layer and the fourth layer is repeatedly arranged; and surrounding the IGBT region. A fifth layer of a second conductivity type selectively formed in the second layer adjacent to the other main surface and the end face of the semiconductor substrate; A fourth electrode formed and electrically connected to the first electrode; an oxide film formed on the other main surface excluding the fifth layer;
The other end is connected to the fourth electrode, and a plurality of layers of the first conductivity type and the second conductivity type are repeatedly arranged between both ends, and the polycrystal formed on the oxide film In a semiconductor device comprising a breakdown voltage holding region having a silicon diode, the interval between the repetitive arrangements of the first conductivity type and the second conductivity type of the polycrystalline silicon diode is wide on the second electrode side and the fourth electrode side Then, a semiconductor device characterized by being narrowed.
層に接触し、前記他方の主表面に隣接して選択的に形成
された第１導電型の第７の層を有し、 第７の層が、前記多結晶シリコンダイオードのＩＧＢＴ
領域側端部から最も近い接合よりも、ＩＧＢＴ領域側に
形成されていることを特徴とする請求項１乃至２の何れ
かに記載の半導体装置。3. A semiconductor device according to claim 1, further comprising a seventh layer of a first conductivity type which is in contact with a fourth layer located at an end of said IGBT region and is selectively formed adjacent to said other main surface; The seventh layer is an IGBT of the polycrystalline silicon diode.
3. The semiconductor device according to claim 1, wherein the semiconductor device is formed closer to the IGBT region than a junction closest to the region side end.
の電極と前記第４の層との接触位置から、前記第７の層
の耐圧保持領域側の端部までの距離Ｌ３が２０μｍ以上
有ることを特徴とする請求項１乃至３の何れかに記載の
半導体装置。4. The third IGBT region end located at the end of the IGBT region.
4. The distance L3 from a contact position between the first electrode and the fourth layer to an end of the seventh layer on the side of the breakdown voltage holding region is 20 μm or more. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34207195A JP3331846B2 (en) | 1995-12-28 | 1995-12-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34207195A JP3331846B2 (en) | 1995-12-28 | 1995-12-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09186315A JPH09186315A (en) | 1997-07-15 |
| JP3331846B2 true JP3331846B2 (en) | 2002-10-07 |
Family
ID=18350939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34207195A Expired - Fee Related JP3331846B2 (en) | 1995-12-28 | 1995-12-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3331846B2 (en) |
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| Publication number | Publication date |
|---|---|
| JPH09186315A (en) | 1997-07-15 |
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