JP3327708B2 - Display control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control system in an information processing system or the like, and more particularly to a display control system suitable for performing image adjustment.

[0002]

2. Description of the Related Art Conventionally, in an information processing system or the like, an image display device that displays not only image information but also character information in pixel units in the same manner as image information has been generally used. , CRT display devices and liquid crystal display devices are widely known.

[0003] This type of image display device displays image information (including character image information) supplied from an image supply device such as a host computer, but usually operates a slide switch or a dial switch. Thereby, image adjustment such as contrast adjustment and brightness adjustment can be performed in real time according to the display environment or the external environment such as the state of illumination.

As a method of performing such image adjustment, there are:
An input device for inputting an image adjustment instruction signal such as a slide switch or a dial switch is provided on the image display device side, and the image display device changes image display parameters based on the image adjustment instruction signal input by the input device. First
And an input means for inputting an image adjustment instruction signal to an image supply apparatus such as a host computer, and the image supply apparatus provides an image display apparatus with an image adjustment instruction signal based on the image adjustment instruction signal input by the input means. A second technique of changing image processing parameters when generating image information to be supplied is used.

[0005]

However, the first method has a problem in that fine image processing (image adjustment) cannot be performed because the image display device alone changes the image display parameters.

On the other hand, in the second method, fine image processing can be performed on the image supply device side. However, when the distance between the image supply device and the image display device is long, the user can view the image while viewing the display screen. There is a problem that it becomes difficult to input an adjustment instruction signal, and that image adjustment cannot be performed smoothly.

The present invention has been made under such a background, and an object of the present invention is to enable fine image adjustment to be performed smoothly while watching a display screen.

[0008]

According to a first aspect of the present invention, there is provided an image supply means for supplying image information while performing image processing, and an image supply means for supplying image information supplied from the image supply apparatus. A display control system having an image display device for displaying, provided in the image display device,
Input means for inputting an image adjustment instruction signal, transfer means for transferring the image adjustment instruction signal input by the input means to the image supply device, provided in the image supply device,
Changing means for changing a coefficient for degamma processing based on the image adjustment instruction signal transferred by the transfer means.

According to another aspect of the present invention, there is provided an image processing apparatus for supplying image information while performing image processing.
Supply means, and image information supplied from the image supply device.
A display control system having an image display device for displaying.
The image adjustment device is provided in the image display device,
Input means for inputting, and an image input by the input means.
Transfer means for transferring an image adjustment instruction signal to the image supply device
Provided in the image supply device, and by the transfer unit
For error diffusion processing based on the transferred image adjustment instruction signal
And changing means for changing the coefficient.

[0010]

[0011]

[0012]

[0013]

According to the first aspect of the present invention, when an image adjustment instruction signal is input by the input unit provided in the image display device, the transfer unit transfers the image adjustment instruction signal to the image supply device. I do. The change unit provided in the image supply device is configured to perform a degamma process based on the image adjustment instruction signal transferred by the transfer unit.
By changing the number , fine image adjustment can be smoothly performed while watching the display screen.

In the invention according to claim 2, the transfer means
Is provided by the input means provided in the image display device.
When an image adjustment instruction signal is input, the image adjustment instruction signal
The number is transferred to the image supply device. And the image source
The change means provided in the feeding device is provided by the transfer means.
Error diffusion processing based on the transferred image adjustment instruction signal
By changing the coefficient of the image, fine image adjustment can be smoothly performed while watching the display screen.

[0015]

[0016]

[0017]

[0018]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an information processing system to which a display control system according to a first embodiment of the present invention is applied.

In FIG. 1, reference numeral 101 denotes a host CPU for controlling the entire information processing system, and an FPU for performing a numerical operation necessary for predetermined control and data processing. Reference numeral 102 denotes a ROM in which a control program code for starting the information processing system and partially controlling hardware is stored in advance, and 103 denotes a main memory 111 and various devices constituting the information processing system without the intervention of the host CPU 101. And a DMA controller (hereinafter, also referred to as DMAC) for transferring data between the DMA controller and the DMA controller.

An interrupt controller 104 controls interrupt requests from various devices constituting the information processing system.
Reference numeral 105 denotes a crystal oscillator, a real-time clock for clocking the accurate clock, 106 denotes a hard disk device and an interface as an external storage device, 107 denotes a floppy disk device and an interface as an external storage device, and 108 denotes a data bus and control. It is a system bus consisting of a bus and an address bus.

Reference numeral 109 denotes an FLC display device (hereinafter, FLCD) having a display screen using a ferroelectric liquid crystal as a display operation medium.
The display is controlled by the FLCD-I / F 110. A main memory 111 stores control program codes and various data for the information processing system. Reference numeral 112 denotes a keyboard for inputting character information and control information, and a controller for controlling the input. 113
Is a serial interface between the communication modem 114, the mouse 115, and the image scanner 116 and the information processing system, 117 is a parallel interface between the printer 118 and the information processing system, 119 is a LAN 120 such as Ethernet and the information processing system. It is a LAN interface to the system.

In this information processing system to which the various devices described above are connected, the operation is performed while viewing the various information displayed on the display screen of the FLCD 109. That is,
LAN 120, communication modem 113, mouse 115, image scanner 116, hard disk 106, floppy disk 107, character information and image information supplied from keyboard 112, and operation information related to the user's system operation stored in main memory 111 are stored in FLCD 10.
9 is displayed on the display screen, and the user performs information editing and instructs the system while watching the display.

FIG. 2 shows an FLCD-I according to the first embodiment.
3 is a block diagram showing the configuration of / F110. FIG. 2, the host CPU 101 (see FIG. 1) transfers display data to the VRAM 202 via the system bus 108 and the SVGA 201. In this display data, each RGB color is represented by 2
It is 24-bit data expressed in 56 gradations. Also, the SVGA 201 has a line address generation circuit 205
Display data of the VRAM 202 specified by the request line address transferred from the line address generation circuit 205 according to the line data transfer enable signal similarly transferred from the line address generation circuit 205.
Transfer to

The rewrite detection / flag generation circuit 203
The VRAM address generated by the GA 201 is monitored, and VR
The display data of AM202 has been rewritten (written)
The VRAM address at the time, that is, the VRAM address at the time when the write enable signal and the chip select signal CS become "1" is taken in, and this VRAM address is converted into a line address. Then, the rewrite detection / flag generation circuit 203 sets a partial rewrite line flag register provided therein according to the line address.

The CPU 204 reads the contents of the partial rewrite line flag register of the rewrite detection / flag generation circuit 203 and sends the line address where this flag is set via the line address generation circuit 205 to the SVGA2.
Send to 01. At this time, when partial rewriting is performed on a plurality of lines, the head line address and the number of continuous lines related to the partial rewriting are sent to the SVGA 201. At this time, the line address generation circuit 205 sends a line data transfer enable signal to the SVGA 201 according to the address data, and causes the SVGA 201 to transfer the display data of the address to the binary halftone processing circuit 206.

The binarized halftone processing circuit 206 converts multi-level display data of 256 gradations represented by 8 bits of each RGB color into binary pixel data corresponding to the display screen of the FLCD 109. In the present embodiment, one pixel of the display screen of the FLCD 109 is composed of three dots of R, G, and B. In this embodiment, an error diffusion method (ED method) is employed as a binarization processing method.

The error diffusion method will be described with reference to FIG.
In the error diffusion method, as shown in FIG. 3A, the input data (0 to 255) is compared with a threshold “127”, and if the input data (0 to 255) is smaller than the threshold, “0” is set; Is output, and the error generated between the input value and the output value is shown in FIG.
The halftone is expressed by diffusing the pixel indicated by the arrow with the weighting of FIG. In the present embodiment, FIG.
Error diffusion table T indicating the weight at the time of diffusion as shown in FIG.
1 is set by the CPU 204. That is, the error diffusion table T1 can be dynamically changed.

The binarized halftone processing circuit 206 sends the generated pixel data to the frame memory control circuit 207 in synchronization with the data enable signal. The frame memory control circuit 207 stores the transmitted pixel data in the frame memory 208 in accordance with the data enable signal.
The data is stored at the input line position specified by the PU 204.
In addition, the frame memory control circuit 207
9 in response to the data request signal from the frame memory 20.
The pixel data is read out from the output line position designated by the CPU 204 in 8 and sent to the FLCD 109. At this time, the frame memory control circuit 207 multiplexes the output line address and the pixel data instructed by the CPU 204 and outputs the multiplexed FLCD1 as the pixel data with address.
09.

The FLCD 109 has an FLCD-I / F 11
The pixel data received from 0 is displayed at the line position in the display panel specified by the line address. When the reception of the pixel data of one line is completed and the reception of the pixel data of the next line is enabled, the data request signal is sent to the frame memory control circuit 207.

The FLCD 109 has a slide switch S
W is attached, and by operating the slide switch SW, the error diffusion table T1 used for error diffusion processing in the binary halftone processing circuit 206 is changed. It is configured such that a suitable display image can be obtained according to the environment. In this case, the operation information of the slide switch SW, that is, the image adjustment instruction signal is transmitted to the serial communication line 210.
Is notified to the CPU 204 via.

Next, the operation when the slide switch SW is operated will be described with reference to FIG.

When the slide switch SW is operated, F
4 between the LCD 109 and the FLCD-I / F 110.
Is performed through the serial communication line 210.

First, the CPU 1 for controlling the FLCD 109
When detecting a change of the slide switch SW for changing the error diffusion table, 09a reads the value of the slide switch SW (S401). Then, the error diffusion table T
Attention to inform that there was a change request of 1
The data is transmitted to the LCD-I / F 110 (S402).

When this attention is received (S40)
3) The CPU 204 in the FLCD-I / F 110 provides detailed information of attention, that is, the slide switch S
A command requesting the number of the error diffusion table T1 designated by the operation of W is transmitted to the FLCD 109 (S4).
04). Upon receiving this request command (S405),
The CPU 109a in the FLCD 109 stores the detailed information of the attention (the number of the error diffusion table T1) on the FLCD-
Send to I / F110.

When detailed information of attention is received (S
407), CPU 204 in FLCD-I / F 110
Transmits a clear attention command to the FLCD 109 to inform that the detailed information of the attention has been normally received (S408). When this clear attention command is received (S409), the CP in FLCD 109 is
U109a correctly converts the attention details into FLC
The attention state is cleared assuming that the transmission was possible to the DI / F 110 (S410).

The CPU 204 in the FLCD-I / F 110 requested to change the error diffusion table T1 stores the error diffusion table T1 of the requested table number in the ROM 220.
And set in the binarized halftone processing circuit 206 (S411).

In this embodiment, FIGS. 5 (a) to 5 (h)
8 are selectable. Here, the error diffusion table T1 shown in FIG.
Is suitable for displaying a halftone image such as a natural image or a gradation pattern, since the halftone display with the largest error diffusion coefficient (weight) is possible. On the other hand, FIG.
The error diffusion table T1 in (h) is suitable for displaying a binary image such as a character image because the error diffusion coefficient (weight) is the smallest and the display is close to binary. FIG.
The error diffusion table T1 shown in FIG.
5 (b) → FIG. 5 (c) → FIG.
(D) Display becomes closer to binary in the order of FIG. 5 (g).

Therefore, by operating the slide switch SW, it is possible to change the error diffusion table T1 in real time and obtain a suitable display image according to the display contents and the like. At this time, the slide switch SW is set to FLCD1.
09, the change of the error diffusion table T1, that is, the change of the image generation parameter is performed by the FLCD-I.
/ F110, it is possible to perform fine image adjustment smoothly in real time while watching changes in the display screen.

[Second Embodiment] The second embodiment is different from the first embodiment in that the error diffusion table T1 is changed.
This is an example in which the degamma table T2 for degamma processing is changed, and the FLCD-I / F11 in the second embodiment is used.
0 is configured as shown in FIG.

FLCD in the second embodiment shown in FIG.
The configuration of the -I / F 110 is almost the same as the configuration of the FLCD-I / F 110 in the first embodiment shown in FIG.
Hereinafter, only the differences will be described. In FIG. 6, FIG.
The same components as those described above are denoted by the same reference numerals.

That is, the FLCD in the second embodiment
The I / F 110 has a degamma processing circuit 601 added to a stage preceding the binarized halftone processing circuit 206.
0 stores eight kinds of degamma tables T2 instead of the eight kinds of error diffusion tables T1 in the second embodiment.

The degamma processing circuit 601 determines whether each of the RGB colors 8
A degamma process is performed for converting the multi-valued display data of 256 gradations represented by bits into other multi-valued display data of 256 gradations according to the conversion value of the degamma table T2. The degamma process is a process for correcting display data that has already been subjected to gamma processing in accordance with the characteristics of the display device and displaying the corrected display data.

As shown in FIG. 7 (a), the degamma table T2 has 256 bits represented by 8 bits for each of RGB.
An input value and an output value (converted value) of the gradation multi-value display data are recorded. Note that the degamma table T2 in FIG. 7A is a conversion formula when the degamma coefficient is the power of 0.45.

## EQU00001 ## Output value (converted value) = 255.times. (Input value / 255) The relationship between the output value and the input value obtained by ^0.45 is shown. When the relationship between the output value and the input value is graphed, FIG.
(B).

In this embodiment, a degamma table T2 as shown in FIG.
The degamma table T2 can be dynamically changed.

The degamma processing circuit 601 sends the display data converted by the degamma table T2 to the binary halftone processing circuit 206 in synchronization with the data enable signal. Binarized halftone processing circuit 20 for this display data
6, frame memory control circuit 207, and FLCD1
Step 09 is the same as in the first embodiment.

In the second embodiment, the slide switch SW attached to the FLCD 109 is
It is used to change the degamma table T2 set to 1. FLCD 109 and FLCD for making this change
All communication with the LCD-I / F 110 is performed via the serial communication line 210, as in the first embodiment.

When the slide switch SW is operated,
In the second embodiment, the FLCD 109 and the FLCD-I / F1
By performing communication or the like according to the procedure shown in FIG. 8 with the degamma table 10, the degamma table T2 set in the degamma processing circuit 601 is changed. The communication operation of the first embodiment shown in FIG. 4 is different from the communication operation of the second embodiment shown in FIG. 8 only in that the change target is changed to the degamma table T2. Since both are completely the same, detailed description thereof is omitted.

In this embodiment, the ROM 220 stores
Eight degamma coefficients (0.36, 0.45,... 0.8,
Eight degamma tables T2 based on 1) are stored, and one degamma table T2 is selected from them according to the operation result of the slide switch SW and set in the degamma processing circuit 601.

Among them, the degamma coefficient “0.36”,
The input value and output value of the degamma table T2 based on “0.8” and “1” are respectively shown in FIGS.
(A) and FIG. 11 (a), and when these are graphed, it becomes as shown in FIG. 9 (b), FIG. 10 (b) and FIG. 11 (b). Note that the case of the degamma coefficient “0.45” is as shown in FIGS. 7A and 7B described above.

Here, the degamma table T2 shown in FIG. 9 (a) has the smallest degamma coefficient and the degree of conversion is large as shown in FIG. 9 (b). Suitable for displaying images. on the other hand,
In the degamma table T2 shown in FIG. 10A, the degamma coefficient is close to "1" and the degree of conversion is small as shown in FIG. Suitable for. The degamma table T2 shown in FIG. 11A has a degamma coefficient of “1”.
Since conversion is not substantially performed as shown in FIG. 11B, the method is suitable for displaying an image that has not been subjected to gamma processing. That is, for an image that has been gamma-processed with a larger gamma coefficient, a suitable image is displayed by selecting the degamma table T2 with a smaller degamma coefficient.

As described above, by operating the slide switch SW in accordance with the gamma processing state of the display content, the degamma table T2 can be changed in real time to obtain a suitable display image. At this time, the slide switch SW is attached to the FLCD 109, and the degamma table T2 is changed by the FLCD-I / F 110, that is, the image generation parameter is changed by the FLCD-I / F 110. It becomes possible to perform it smoothly in real time while watching.

[Third Embodiment] The third embodiment is an example in which the process of changing the error diffusion table T1 in the first embodiment and the process of changing the degamma table T2 in the second embodiment are performed. The FLCD-I / F 110 in the example is
It is configured as shown in FIG.

FLC in the third embodiment shown in FIG.
The configuration of the DI / F 110 is substantially the same as the configuration of the FLCD-I / F 110 in the second embodiment shown in FIG. 6, and the same components are denoted by the same reference numerals.

The FLCD 109 is provided with two slide switches SW1 and SW2.
W1 is used for changing the error diffusion table T1, and the slide switch SW2 is used for changing the degamma table T2.

The CPU 109a in the FLCD 109 transmits an attention corresponding to the operated slide switch SW1 or SW2 to the FLCD-I / F 110. CPU 204 in FLCD-I / F 110 determines the type of received attention and performs an operation corresponding to the type of attention. That is, when the slide switch SW1 for changing the error diffusion table T1 is operated, the same operation as in the first embodiment shown in FIG. 4 is performed, and the slide switch SW2 for changing the degamma table T2 is performed.
Is operated, the same operation as in the second embodiment shown in FIG. 8 is performed, so that fine image adjustment can be smoothly performed in real time while watching the change of the display screen.

It should be noted that the present invention is not limited to the above-described embodiment, and it is possible to add another change in image processing (generation) parameters. In this case, as described above, the display device (FLCD 109) and the image supply device (FLCD-
If the communication with the I / F 110) is performed by serial communication, another image processing (generation) parameter changing process can be easily added.

Further, communication between the display device and the image supply device can be performed by parallel communication using a plurality of signal lines. Furthermore, a dial switch or the like other than the slide switch may be used as an input unit for inputting the image adjustment instruction signal.

[0059]

As described above in detail, according to the present invention, an image supply apparatus for supplying image information while performing image processing, and an image display apparatus for displaying image information supplied from the image supply apparatus In the display control system having the above, it is possible to smoothly perform fine image adjustment while watching the display screen, and the usability is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an information processing system to which a display control system according to an embodiment of the present invention is applied.

FIG. 2 is an image supply device (F) according to the first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an LCD-I / F).

FIG. 3 is an explanatory diagram for explaining an error diffusion process.

FIG. 4 is a sequence diagram showing a communication procedure when an error diffusion table is changed.

FIG. 5 is a diagram showing an example of the contents of an error diffusion table.

FIG. 6 illustrates an image supply device (F) according to a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an LCD-I / F).

FIG. 7 is an explanatory diagram for explaining degamma processing.

FIG. 8 is a sequence diagram showing a communication procedure when a degamma table is changed.

FIG. 9 is a diagram showing an example of the contents of a degamma table.

FIG. 10 is a diagram showing another example of the contents of the degamma table.

FIG. 11 is a diagram showing another example of the contents of the degamma table.

FIG. 12 is a block diagram illustrating a configuration of an image supply device (FLCD-I / F) according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 ... Host CPU 102 ... ROM of the information processing system main body 109 ... FLCD (image supply device) 109a ... CPU in FLCD 110 ... FLCD-I / F (image supply device) 111 ... Main memory 112 ... Keyboard 116 ... Image scanner 204: CPU in FLCD-I / F 206: Binary halftone processing circuit 210: Serial line 220: ROM in FLCD-I / F 601: De-gamma processing circuit T1: Error diffusion table T2: De-gamma table SW, SW1, SW2 ... Slide switch

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI G09G 3/36 G09G 5/10 Z 5/10 5/00 520J (72) Inventor Masami Shimakura 3-30 Shimomaruko, Ota-ku, Tokyo 2 Canon Inc. (72) Inventor Junichi Tanahashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tatsuya Sakashita 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Within (72) Inventor Eiichi Matsuzaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Taketo Hasegawa 3-30-2, Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References JP-A-6-83291 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/00 G09G 3/20 G09G 3/36

Claims (2)

(57) [Claims] 1. A display control system comprising: an image supply unit that supplies image information while performing image processing; and an image display device that displays image information supplied from the image supply device. Input means for inputting an image adjustment instruction signal provided; transfer means for transferring the image adjustment instruction signal input by the input means to the image supply device; and transfer means provided for the image supply device and transferred by the transfer means engagement for de-gamma process on the basis of an image adjustment instruction signal
A display control system comprising: a change unit that changes the number . 2. A method for supplying image information while performing image processing.
Image supply means, and an image displaying image information supplied from the image supply device.
A display control system having a display device, wherein the display control system is provided in the image display device and receives an image adjustment instruction signal.
Input means, and an image adjustment instruction signal input by the input means.
Transfer means for transferring to the image supply device; and transfer means provided for the image supply device and transferred by the transfer means
Error diffusion processing based on the adjusted image adjustment instruction signal.
Display having changing means for changing the number
Control system.