JP3326016B2 - Oxide superconducting base transistor, manufacturing method thereof and integration method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oxide superconducting base transistor, a method for manufacturing the same, and a method for integrating the same.

[0002]

2. Description of the Related Art A conventional oxide superconducting base transistor is disclosed in the literature: "Oki R & D, January, 1994, No. 161.
No., Vol. 61, no. 1, pp81-86 ". The oxide superconducting base transistor proposed in the literature includes a niobium (Nb) -doped SrTiO ₃ (hereinafter, sometimes referred to as STO (Nb)) substrate as an emitter and a (Ba, Rb) BiO ₃ as a base.
(Hereinafter, it may be referred to as BRBO.) The oxide superconducting layer is formed by using indium (In) formed on BRBO as a collector.

[0003]

SUMMARY OF THE INVENTION BRBO / STO (N
b) Comparing the barrier height of the junction with the barrier height of the BRBO / In junction, the barrier of the BRBO / STO (Nb) junction is higher. For this reason, a conventional oxide superconducting base transistor uses an STO (Nb) substrate as an emitter. Then, carriers are injected from the STO (Nb) substrate to form a collector top structure. Also,
Since an STO (Nb) substrate is used as the emitter, the area of the emitter region is larger than the area of the collector region.

If the area of the emitter region is larger than the area of the collector region, carriers are scattered by phonons and defects while carriers injected from the emitter pass through the base. Therefore, the amount of carriers collected at the collector electrode is reduced, and a current flows as a leak to the base.

Therefore, there has been a demand for an oxide superconducting base transistor in which the number of carriers collected at the collector electrode is not reduced.

[0006]

In order to provide an oxide superconducting base transistor in which the number of carriers collected at the collector electrode does not decrease, the structure of the oxide superconducting base transistor according to the present invention is as follows. . First, the transistor includes an insulating substrate, a semiconductor region formed by doping a predetermined region of the substrate surface with a metal, and further formed on the substrate surface so as to cover a part of the semiconductor region, And an oxide superconducting layer forming a base region, and further comprising, on the oxide superconducting layer, a collector region provided in the semiconductor region so as to face the emitter region and having a larger area than the emitter region. I have.

In a preferred embodiment of the present invention, SrTiO _{3 is used as} an insulating substrate, Nb or V is used as a metal doped into the insulating substrate, and (Ba, Rb) B is used as an oxide superconducting layer.
It is preferable that iO ₃ or (Ba, K) BiO ₃ be In, which is formed on the oxide superconducting layer as a collector.

Further, in a preferred embodiment of the present invention, it is preferable that a predetermined region of the substrate surface is doped with a metal by an ion implantation method.

Further, an oxide superconducting base transistor is integrated by doping a predetermined region of the substrate with a metal by using an ion implantation method.

[0010]

In the oxide superconducting base transistor having such a structure, the area of the collector region is larger than the area of the emitter region. Therefore, while the carriers injected from the emitter pass through the base, the probability of the carriers being scattered by phonons, defects, and the like is reduced, and more carriers are collected at the collector electrode.

In addition, when an ion implantation method is used as a method for doping a predetermined region of the surface of the oxide insulating substrate with a metal, precise control of the implantation range becomes possible, and furthermore, integration of the oxide superconducting base transistor becomes possible. It becomes easy.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In these drawings, each component merely schematically shows the shape, size and arrangement of each component to the extent that the present invention can be understood.

FIGS. 1A to 1C and FIGS. 2A to 2C.
FIG. 3 is a cross-sectional view schematically showing a step of manufacturing the oxide superconducting base transistor of the present invention. Also, FIG.
FIG. 1 is a plan view schematically showing a structure of an oxide superconducting base transistor of the present invention.

First, an oxide insulating substrate 11 is prepared, and a predetermined region on the surface of the oxide insulating substrate 11 is doped with metal to form a semiconductor region 13 (FIG. 1A). As a method for doping a predetermined region on the surface of the oxide insulating substrate 11 with a metal, thermal diffusion or ion implantation is used. In this embodiment, SrTiO ₃ is used as the oxide insulating substrate 11.
A predetermined region on the surface of the SrTiO ₃ substrate 11 is doped with niobium (Nb) using a substrate. When doping a predetermined region of the surface of the SrTiO ₃ substrate 11 with Nb by thermal diffusion, first, Nb is added to the predetermined region at 10 ¹⁴ to 10 ¹⁷ atoms / cm 2.
^{About 2} vapor depositions, then at about 800-1100 ° C, 1
The heat treatment is performed in an atmosphere of a mixed gas of nitrogen gas and oxygen gas for a period of time to several tens of hours. When doping a predetermined region of the surface of the SrTiO ₃ substrate 11 with Nb by an ion implantation method, first, the STO substrate 11 is placed in an ion implantation chamber, and then a dose amount is about 10 ¹⁶ atoms / cm ² and an incident energy is 900 keV. The STO substrate 11 to 200
Nb is implanted into the STO substrate 11 to a depth of 0 °. Thus, for example, the semiconductor region 1 doped with Nb
Get 3.

Next, an oxide superconducting layer 15 is formed on the surface of the substrate 11 (FIG. 1B). This oxide superconducting layer 1
5 acts as a base. In this embodiment, a (Ba, Rb) BiO ₃ layer is used as the oxide superconducting layer 15,
It is formed by MBE (substrate temperature: 370 ° C., 30 minutes).

Next, a collector region 17a is formed on the oxide superconducting layer 15 (FIG. 1C). Therefore, in this embodiment, the indium (In) layer 1 is formed on the BRBO layer 15.
7 is placed at a position where it partially opposes the semiconductor region 13 by a vacuum evaporation method (room temperature, 5 minutes, thickness 7000 °), and has an area larger than this region so as to cover the opposing semiconductor region. It forms so that it may become. Then,
A substance generated at the interface between the BRBO layer 15 and the In layer 17 functions as a collector. In this embodiment, the BRBO layer 1
The remaining In layer portion other than the material layer 17a generated at the interface between the layer 5 and the In layer 17 functions as the collector electrode 17b.

Next, a base electrode 19 is formed (FIG. 2).
(A)). In this embodiment, Au is used as the base electrode. The base electrode 19 is provided at a position that does not face the semiconductor region 13 when viewed from above the substrate 11, that is, at a position where the base electrode 19 does not overlap with the In layer 17.

Next, the BRBO layer 15 is etched using an argon ion etching method (at a voltage of 1 kV and a current of 0.1 mA).
(6 mA / cm ² , 5 minutes) to pattern the BRBO layer 15 formed on the surface of the substrate 11 into a predetermined shape (FIG. 2B). At this time, the semiconductor region 13 covered with the BRBO layer 15 is the emitter region 13a. This patterning is performed such that the remaining BRBO layer has a larger region facing the emitter region 13a than the emitter region 13a, that is, the facing area is larger, and the area of the collector region is larger than the area of the emitter region. This is performed by etching the BRBO layer 15 so as to be as follows. When a predetermined region on the surface of the SrTiO ₃ substrate 11 is doped with Nb by thermal diffusion, the region 13a serving as an emitter after etching the BRBO layer has a square shape with one side of, for example, 50 μm. In the figure,
The patterned BRBO layer is indicated by 21.

Next, an emitter electrode 23 is formed (FIG. 2).
(C)). In this embodiment, Au /
Cr is used. The emitter electrode 23 is provided on the semiconductor region 13. The emitter electrode 23 is provided so as to entirely or partially overlap the region 13.
The n layer 17 and the base electrode 19 are provided apart from each other. Here, in the semiconductor region 13, a region excluding the emitter region 13a is referred to as a relay region 13b for electrically connecting the emitter region 13a and the emitter electrode 23.

In the oxide superconducting base transistor having such a structure (see FIG. 3), the collector region 17
The area of a is larger than the area of the emitter region 13a. Therefore, while the carriers injected from the emitter pass through the base, the carriers are scattered by phonons and defects, so that the amount of carriers collected at the collector electrode 17b decreases, and a current flows as a leak to the base. Can be solved.

When a predetermined region on the surface of the oxide insulating substrate 11 is doped with a metal by ion implantation, precise control of the implantation range becomes possible. Therefore, metal doping can be performed by setting a fine pattern. Further, since the substrate 11 has insulating properties, integration of the oxide superconducting base transistor can be performed.

Obviously, the invention is not limited to the embodiments described above. For example, in the above embodiment, the SrTiO ₃ substrate is doped with Nb, but may be doped with vanadium (V). Further, a BRBO layer is used as a base, but (Ba, K) BiO
_Three layers may be used. Further, when the In layer is formed on the BRBO layer, a substance generated at the interface is used as a collector, but aluminum (Al) or chromium (Cr) may be used. Although Au / Cr is used as the emitter electrode, Al may be used. In addition, A
Although u is used, silver (Ag) may be used.

[0023]

As is apparent from the above description, in the oxide superconducting base transistor according to the present invention, the area of the collector region is larger than the area of the emitter region. Accordingly, while carriers injected from the emitter pass through the base, the carriers are scattered by phonons and defects, so that the amount of carriers collected at the collector electrode is reduced, and a current flows as a leak to the base. Can be solved.

In addition, when an ion implantation method is used as a method for doping a predetermined region of the surface of the oxide insulating substrate with a metal, precise control of the implantation range becomes possible. for that reason,
Metal doping can be performed by setting a fine pattern. Further, since the substrate has insulating properties, integration of the oxide superconducting base transistor becomes possible.

[Brief description of the drawings]

FIGS. 1A to 1C are process diagrams for manufacturing an oxide superconducting base transistor according to an embodiment of the present invention.

FIGS. 2A to 2C are process diagrams following FIG. 1 for manufacturing an oxide superconducting base transistor according to an embodiment of the present invention.

FIG. 3 is a plan view of an oxide superconducting base transistor according to an embodiment of the present invention.

[Explanation of symbols]

 11: Oxide insulating substrate 13: Semiconductor region 13a: Emitter region 13b: Relay region 15: Oxide superconducting layer 17: In layer 17a: Collector region 17b: Collector electrode 19: Base electrode 21: Patterned BRBO layer 23: Emitter electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-102543 (JP, A) JP-A-5-275760 (JP, A) JP-A-3-228381 (JP, A) JP-A-4-228 130782 (JP, A) JP-A-2-181481 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 39/22-39/24 H01L 39/00

Claims (4)

(57) [Claims] An insulating substrate; a semiconductor region formed by doping a metal in a predetermined region of the substrate surface; a semiconductor region formed on the substrate surface so as to cover a part of the semiconductor region; An oxide superconducting layer forming a base region, and a collector region provided on the oxide superconducting layer so as to face an emitter region of the semiconductor region and having a larger area than the emitter region. An oxide superconducting base transistor characterized in that: 2. The oxide superconducting base transistor according to claim 1, wherein the insulating substrate is SrTiO.
₃ , Nb or V as a metal doped into the insulating substrate, and (Ba, Rb) BiO ₃ as the oxide superconducting layer.
Or (Ba, K) BiO ₃ , In being formed on the oxide superconducting layer as the collector, an oxide superconducting base transistor. 3. The method for manufacturing an oxide superconducting base transistor according to claim 2, wherein doping of a metal to a predetermined region of the substrate surface is performed by an ion implantation method. Method. 4. A method for integrating an oxide superconducting base transistor, comprising using the method for producing an oxide superconducting base transistor according to claim 3.