JP3321427B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a structure of a bump.

[0002]

2. Description of the Related Art Recently, a semiconductor device having a chip-on-chip structure, in which a plurality of semiconductor elements are superposed in two layers, has attracted attention. Further, a TAB (Tape Automated Bonding) technique of superposing a semiconductor element on a tape carrier has been practically used.

[0003] However, the substrate itself is often damaged due to the inability to absorb the stress, resulting in a decrease in yield. Further, in a state where the semiconductor element is mounted, the substrate may be warped due to heat or the like depending on the environment, and in this case, a large stress is applied to the joint portion of the bump. Therefore, it is possible to reduce the mechanical damage when joining the chips, thereby improving the production yield, and also to alleviate the stress applied to the substrate even in a use environment under a bad environment and to maintain the reliability. There has been a demand for a semiconductor device that can operate.

[0004]

At the time of this bonding,
Since a large stress is applied to the bump junction, the substrate on which the bump is provided may be mechanically damaged. So, in order not to receive this damage,
It is trying to absorb stress by the elasticity of the bump itself.

[0005] However, since the stress cannot be completely absorbed, the substrate itself is often damaged, resulting in a decrease in yield. Further, in a state where the semiconductor element is mounted, the substrate may be warped due to heat or the like depending on the environment, and in this case, a large stress is applied to the joint portion of the bump. Therefore, it is possible to reduce the mechanical damage when joining the chips, thereby improving the production yield, and also to alleviate the stress applied to the substrate even in a use environment under a bad environment and to maintain the reliability. There has been a demand for a semiconductor device that can be used.

[0006]

The semiconductor device according to the present invention comprises a first semiconductor element and a second semiconductor element.
A semiconductor device, wherein the semiconductor device is
The first semiconductor element has a surface facing the second semiconductor element.
And a frame surrounding the internal bumps
Peripheral bumps formed in the shape of
The semiconductor element is an internal bump of the first semiconductor element.
Connected to the first semiconductor element.
An internal bump for transmitting / receiving the first semiconductor element;
Frame-shaped peripheral bumps bonded to the peripheral bumps of the
And have a (claim 1). Here , the second semiconductor element
Has a "bump between the first semiconductor element"
These are bumps other than " internal bumps for transmitting and receiving signals " and are provided for the purpose of reducing stress at the joint (hereinafter, referred to as "stress relief bumps").

According to this structure, the first semiconductor element is provided.
Provided on the peripheral bump and the second semiconductor element.
The stress relief bumps (surrounding bumps) have a function of absorbing shock at the time of joining. Therefore, damage to the substrate during bonding can be prevented beforehand, and the manufacturing yield of the semiconductor device can be improved. In addition, even in the use state, the stress applied to the substrate by the joint portion of the bumps can be reduced, and the reliability of the semiconductor element can be maintained.

[0008] The stress relief bump ( the second semiconductor)
Bumps around the body element) are located inside the second semiconductor element.
If the bump is formed in the step of forming (claim 2), the bump can be formed without providing another step.

[0009]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the embodiments of the present invention, description will be made on the assumption that Si is used as the type of semiconductor, but other semiconductors such as GaAs and Ge may be used. FIG. 1 is a cross-sectional view of an element formation region and its periphery for explaining a bump formation step.

As shown in FIG. 1A, a Si semiconductor substrate 1
An Al electrode 3 is formed on a predetermined portion through the SiO ₂ film 2.
Are formed. SiN, PSG around Al electrode 3
And the like. In addition, a high-concentration impurity 10 having a predetermined polarity is implanted in a region (for example, a scribe line region) around the semiconductor substrate 1 where a stress relieving bump is to be formed in order to secure ohmic contact or insulation. The polarity of the impurity is the same as that of the substrate when it is in ohmic contact with the substrate, and is different from that of the substrate when it is insulated. Further, a metal layer such as Al may be deposited thereon.

On the semiconductor substrate 1, a TiW alloy layer for improving the adhesion between the Al electrode and the bump, and a seed layer 5 in which a layer of Au, Pt or the like for power supply is laminated by a method such as sputtering. (FIG. 1 (b)). Next, a photoresist 6 is applied and holes for bump plating are formed in the electrode portion and the stress relief bump portion (FIG. 1C).

Then, the bump metal is plated thickly by electrolytic plating (FIG. 1 (d)). As this bump metal,
Au, Pd, Pt, Ag, Ir (iridium) and the like can be mentioned. Among the formed bumps, the Al electrode 3
The bump formed above is indicated by reference numeral 8, and the stress relieving bump is indicated by reference numeral 7. Next, the photoresist 6 is removed and the seed layer 5 on the surface is removed (FIG. 1 (e)) to obtain the semiconductor element 12.

FIG. 2 is a manufacturing process diagram when an electroless plating method, which is a metal plating film forming method utilizing a reducing action by a chemical reaction, is used to form bumps. As shown in FIG. 2A, an Al electrode 3 is formed at a predetermined position on a device forming region of a Si semiconductor substrate 1 with an SiO ₂ film 2 interposed therebetween, and a portion other than the Al electrode 3 is a passivation film. Cover with 4. The area for forming the stress relief bump is
As in the case of FIG. 1, an impurity 10 having a predetermined polarity is implanted at a high concentration in order to secure ohmic contact or insulation.
Then, a seed layer 5a is laminated on the surface.

Next, a photoresist 6 is applied, holes are made in predetermined portions, and a thick bump metal is plated by an electroless plating method (FIG. 2B). Then, the photoresist 6 is removed, and the seed layer 5 on the surface is removed.
Get. As shown in FIGS. 3A and 3B, the semiconductor element 12 manufactured by the method of FIG. 1 or FIG. 2 has bumps (hereinafter referred to as “internal bumps”) 8 on the upper surface of the semiconductor element 12. Is formed, and the surroundings are bumps (hereinafter “surrounding bumps”).
7).

FIG. 4 shows a semiconductor device 1 having a peripheral bump 7.
FIG. 3 is an explanatory diagram of a case where two have a two-layer structure in the form of a so-called chip-on-chip. FIG. 6A is a perspective view showing a state in which the semiconductor elements 12 are joined together, and FIG. 6B is a sectional view after the joining. When joining the internal bumps 8 together,
The peripheral bumps 7 having a large area are joined together to form an internal bump 8.
Can be alleviated, and poor connection can be prevented. Further, the stress applied to the joint in the use state can be reduced.

In FIG. 4, one semiconductor element 1
Similarly, when a TAB pattern film is used instead of 2, a stress relieving effect can be expected. The present invention is not limited to the embodiment described above.
For example, in the description so far, the stress relieving bump 7 is
Although provided on the entire periphery of the semiconductor element 12, it may be provided on a part of the periphery of the semiconductor element 12.
Further, the device may be provided inside the surface of the semiconductor element 12. In addition, various changes can be made within the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor element region for explaining a bump forming step.

FIG. 2 is a cross-sectional view of a manufacturing process when electroless plating is used to form a bump.

FIG. 3A is a plan view of a semiconductor element 12 manufactured by surrounding the semiconductor element 12 with a stress relief bump 7, and FIG. 3B is a perspective view.

FIG. 4 is an explanatory view of a case where the semiconductor elements 12 with the peripheral bumps 7 have a two-layer structure in the form of a so-called chip-on-chip, and (a) is a perspective view showing a state in which the semiconductor elements 12 are joined to each other. (B) is a sectional view after bonding.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 SiO ₂ film 3 Al electrode 4 passivation film 5 seed layer 6 photoresist 7 peripheral bump 8 internal bump 10 impurity layer 12 semiconductor element

────────────────────────────────────────────────── ─── of the front page continued (58) investigated the field (Int.Cl. ^7, DB name) H01L 21/60 H01L 25/08

Claims (2)

(57) [Claims] 1. A semiconductor device comprising : a first semiconductor element and a second semiconductor element;
A semiconductor device overlapped and joined , wherein the first semiconductor element faces the second semiconductor element.
The internal bumps and the area around the internal bumps
A peripheral bump formed in a frame shape surrounding the first semiconductor element; and the second semiconductor element has the first semiconductor element.
To the first semiconductor element
Internal bumps for transmitting and receiving signals between the
Frame-shaped periphery joined to the peripheral bumps of the semiconductor element
Semiconductor device characterized in that it possess the circumference bump. 2. The method according to claim 1 , wherein the peripheral bumps of the second semiconductor element are formed on an upper surface.
2. The semiconductor device according to claim 1, wherein said semiconductor device is formed in a step of forming an internal bump of said second semiconductor element .