JP3721000B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3721000B2
JP3721000B2 JP04685399A JP4685399A JP3721000B2 JP 3721000 B2 JP3721000 B2 JP 3721000B2 JP 04685399 A JP04685399 A JP 04685399A JP 4685399 A JP4685399 A JP 4685399A JP 3721000 B2 JP3721000 B2 JP 3721000B2
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Japan
Prior art keywords
groove
bump
semiconductor element
semiconductor device
semiconductor
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JP2000243901A (en
Inventor
義和 中川
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP04685399A priority Critical patent/JP3721000B2/en
Publication of JP2000243901A publication Critical patent/JP2000243901A/en
Priority to US10/373,692 priority patent/US6965166B2/en
Priority to US11/150,129 priority patent/US7307349B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関し、特に半導体素子に他の半導体素子を重ね合わせるチップオンチップ構造に関するものである。
【０００２】
【従来の技術】
半導体装置の一層の集積化を図るため、複数の半導体素子を２層に重ね合わせる、チップオンチップ構造の半導体装置が注目されている。
このチップオンチップ構造にする場合、大小の半導体素子の素子形成面上に、内部配線を部分的に露出させたパッド開口部を設け、このパッド開口に「バンプ」という突起電極を設け、半導体素子同士をいわゆるフェイスツーフェイスで重ね合わせるという方法がとられている。そして、大きな方の半導体素子の素子形成面に電極を設けて、下地基板（配線板）の電極との間で接続し、この下地基板の電極を、プリント基板やセラミック基板に半田接続する。
【０００３】
【発明が解決しようとする課題】
前記チップオンチップ構造の半導体装置では、２層に重ね合わせる場合の半導体素子同士の位置合わせが重要となる。位置合わせができていないと、２層のバンプ同士が接合できない場合があるからである。
従来では、２つの半導体素子を重ねるときに、バンプ同士が正確な位置にくるように、光学的プリズムの全反射による像の重なりを利用するなどの手法を用いていた。しかし、光学的手法に頼っていたのでは、時間と手間がかかり、生産能率が上がらないという問題があった。
【０００４】
そこで、本発明は、半導体素子をチップオンチップ構造にする場合、半導体素子同士の重ね合わせの精度を確保することができ、もって生産能率に優れた半導体装置を実現することを目的とする。
【０００５】
【課題を解決するための手段及び発明の効果】
本発明の半導体装置は、互いに重ね合わせる半導体素子のうちの一方の重ね合わせ面の周辺部全周に渡る位置合わせ用の第１溝を設け、他方の半導体素子の重ね合わせ面には前記第１溝に対応する形状の位置合わせ用の第２溝を設けて、これらの位置合わせ用の溝に複数の金属球が配置されているものである（請求項１）。
この構成によれば、半導体素子をチップオンチップ構造にする場合、溝同士を、金属球を介して位置合わせすることができる。したがって、バンプ同士の接合が確実にできるようになり、製造の歩留りを向上させることができる。
【０００６】
また、前記金属球の半径は、半導体素子同士を重ね合わせたときに、溝に配置された金属球の中心の高さが、接合するバンプの上面よりも高くなるように設定されていることが必要である（請求項２）。半導体素子同士を重ね合わせるときに、バンプ同士が接合するよりも先に金属球が溝を案内して、位置決めを行う必要があるからである。また、接合時に、金属球が溝にぶつかることにより、バンプにかかる衝撃を緩和することができる。さらに、接合後半導体装置の使用時に、基板にかかる応力を吸収する役割も果たすことができる。
【０００７】
前記溝は、半導体素子の基板に形成されていてもよく、半導体素子に設けられたバンプの上に形成されていてもよい。
半導体素子に設けられたバンプの上に形成されている場合、半導体素子にかかる応力をバンプによっても吸収することができる。
前記バンプを半導体素子の素子形成面の電極配線に利用することもできる。これにより、素子内の配線の一部を、バンプを利用して行えるので、素子形成の一層の集積化ができる。
【０００８】
【発明の実施の形態】
以下、本発明の実施の形態を、添付図面を参照しながら詳細に説明する。本発明の実施の形態では、半導体の種類として、Ｓｉを使用することを前提としているが、他にＧａＡｓ、Ｇｅなどの半導体を使用してもよい。
図１(a)は、半導体素子１の要部斜視図である。半導体素子１の素子形成面にはバンプ３が設けられ、その周囲、例えばスクライブラインの領域の所定位置には、溝２が形成されている。この溝の形成方法としては、例えば、基板をエッチングする、切削具で切り込みを入れる、などの方法をとることができる。
【０００９】
この溝２に複数の金属球４が配置されている（図１(b)参照）。前記金属球４は、好ましくは半田、Ａｕ，Ｓｎのような柔らかい金属で形成されている。金属球の配置方法としては、作業員が顕微鏡を見ながら１球１球、ピンセットで溝２に置いていくという方法も考えられるが、実用的には、ガイドを使って金属球を溝２に流し込むという方法が採用できる。
【００１０】
図２(a)は、前記金属球の配置された半導体素子１に、他の半導体素子１を重ね合わせる前の状態を示す断面図、図２(b)は、重ね合わせた後の状態を示す断面図である。また図３は、半導体素子同士を重ね合わせる状態を示す斜視図である。
図２(a)に示すように、金属球４の半径は、金属球４を溝に配置したときに、金属球４の中心が、バンプ３の上面よりも高くなるように設定されている。実際には、金属球４の半径は、せいぜい数１０μｍ程度である。
【００１１】
他の半導体素子１には、周辺部の全周に渡って溝２が形成されており、素子同士を重ね合わせたときに、複数の金属球４が、溝２，溝２を案内して溝２同士が同位置になるようにする。より詳細には、図３において上側に描かれた半導体素子１には、重ね合わせ面の周縁部全周に渡って溝２（第１溝）が形成されており、図３において下側に描かれた半導体素子１には、その重ね合わせ面に、上側の半導体素子１の溝２に対応する形状の溝２（第２溝）が形成されている。
図２ (a) の状態で、半導体素子同士を圧縮すると（図３参照）、溝２，溝２の位置合わせができ、図２(b)に示すように、半導体素子を位置合わせした状態でバンプ３同士を確実に接合させることができる。
【００１２】
また、この金属球４は、接合時自ら変形することにより、接合時のバンプ３にかかる衝撃を緩和し、半導体装置の使用状態においても、基板の反りなどによって接合部分にかかる応力を吸収する役割を果たす。
図４は、参考例に係る構成を示す図である。図４(a)の参考例では、半導体素子の周辺部の一部に溝２が形成されている。また、図４(b)の参考例では、半導体素子の周辺部の複数箇所に溝２が設けられている。
【００１３】
また、溝２の形も任意であり、例えば図５(a)に示すように断面Ｖ形の溝２ｃ、図５(b)に示すように断面半円状の溝２ｄがあげられる。次に、半導体素子の周囲の所定位置にバンプを設け、その上に溝を形成する発明の実施の形態を説明する。
図６は、半導体素子１の平面図であり、素子形成面の周囲には、細長いバンプ６が設けられている（以下「周囲バンプ６」という）。周囲バンプ６には、溝７が形成されており、ここに複数の金属球４が配置される。なお、周囲バンプ３に電極としての機能を与えることも可能である。例えば図６では、周囲バンプ６は、橋渡しバンプ８によって電極であるバンプ３ａと接続されているので、周囲バンプ６を接地ラインにしたり、電源ラインにしたりすることができる。
【００１４】
図７は、周囲バンプ６を設けた半導体素子１同士を接合した状態を示す断面図である。金属球４によって、溝７同士の位置合わせができるので、半導体素子のバンプ３同士を確実に接合させることができる。
周囲バンプ６及び金属球４は、接合時自ら変形することにより、接合時のバンプ３にかかる衝撃を緩和する。また、半導体装置の使用状態においても、基板の反りなどにより接合部分にかかる応力を吸収する役割を果たす。
【００１５】
また、この構成で、周囲バンプ６を電極として用いているとき、金属球４によって上下の半導体素子１の周囲バンプ３同士の電気的な接続をさせことができる。
図８は、溝７の付いた周囲バンプ６を形成する方法を説明するための工程図である。
【００１６】
図８(a)は、半導体素子１の基板の所定位置に、溝２を紙面に垂直な方向に形成した状態を示す。この溝２の形成方法は、部分的なエッチングや機械的な切削など任意の方法が採用できる。なお、１２はＡｌパッド電極である。
この上から全面にＳｉＮ，ＳｉＯＮ，ＳｉＯ2，ＰＳＧ等のパッシベーション膜１３を形成する（図８(b)）。パッシベーション膜１３の形成方法として、例えばプラズマＣＶＤがあげられる。
【００１７】
次に、図８(c)に示すように、基板の全領域に、下地との密着性をよくするためのＴｉＷ合金層、メッキの給電のためのＡｕ，Ｐｔなどの層を積層したシード層１４をスパッタなどの方法で蒸着する。
次に、バンプメッキする領域を除いて、フォトレジスト１５を塗布する。そして電解メッキ法にてバンプ用金属を厚くメッキする（図８(d)）。このバンプ用金属として、Ａｕ，Ｐｄ，Ｐｔ，Ａｇ，Ｉｒ（イリジウム）等をあげることができる。電解メッキ法に代えて、化学反応による還元作用を利用した金属のメッキ成膜方法である無電解メッキ法を採用してもよい。この場合、バンプメッキする高さは、図８(e)に示すように、金属球４を置いたときに金属球の中心位置よりも低くなるようにする。
【００１８】
次に、フォトレジスト１５を除去し表面のシード層１４を除去して、アニール処理を行うことにより、バンプ３及び周囲バンプ６が形成された半導体素子を得る。この周囲バンプには、前に形成した溝２の深さの分だけの落ち込みがあり、これが周囲バンプに沿った溝７となる。この溝７の上に金属球４を配置する（図８(e)）。
【００１９】
なお、この発明は、以上説明した実施形態に限定されるものではなく、本発明の範囲内で種々の変更を施すことが可能である。
【図面の簡単な説明】
【図１】本発明に係る半導体素子１の要部斜視図である。
【図２】 (a)は、前記金属球の配置された半導体素子１に、他の半導体素子１を重ね合わせる前の状態を示す断面図、(b)は、重ね合わせた後の状態を示す断面図である。
【図３】半導体素子同士を重ね合わせる状態を示す斜視図である。
【図４】 (a)は半導体素子の周辺部の一部に溝２を形成した状態を示す平面図、 (b)は半導体素子の周辺部の複数箇所に溝２を形成した状態を示す平面図である。
【図５】溝の断面図である。
【図６】半導体素子の周囲の所定位置にバンプを設け、その上に溝を形成した半導体素子１の平面図である。
【図７】周囲バンプ６を設けた半導体素子１同士を接合した状態を示す断面図である。
【図８】溝７の付いた周囲バンプ６を形成する方法を説明するための工程図である。
【符号の説明】
１ 半導体素子
２ 溝
３ バンプ
４ 金属球
６ 周囲バンプ
７ 溝
１２ Ａｌ電極
１３ パッシベーション膜
１４ シード層
１５ フォトレジスト[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a chip-on-chip structure in which another semiconductor element is superimposed on a semiconductor element.
[0002]
[Prior art]
In order to further integrate a semiconductor device, a semiconductor device having a chip-on-chip structure in which a plurality of semiconductor elements are stacked in two layers has attracted attention.
In the case of this chip-on-chip structure, a pad opening part in which internal wiring is partially exposed is provided on an element formation surface of a large and small semiconductor element, and a bump electrode called “bump” is provided in the pad opening. The method of superimposing each other by so-called face-to-face is taken. Then, an electrode is provided on the element forming surface of the larger semiconductor element and connected to an electrode of the base substrate (wiring board), and the electrode of the base substrate is solder-connected to a printed board or a ceramic substrate.
[0003]
[Problems to be solved by the invention]
In the semiconductor device having the chip-on-chip structure, it is important to align the semiconductor elements when they are stacked in two layers. This is because the two-layer bumps may not be joined together if alignment is not possible.
Conventionally, when two semiconductor elements are overlapped, a method such as utilizing an overlap of images due to total reflection of an optical prism has been used so that the bumps are positioned accurately. However, relying on optical methods has been problematic in that it takes time and effort and production efficiency does not increase.
[0004]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize a semiconductor device that can ensure the accuracy of superposition of semiconductor elements when the semiconductor elements have a chip-on-chip structure, and that is excellent in production efficiency.
[0005]
[Means for Solving the Problems and Effects of the Invention]
The semiconductor device of the present invention, provided one of the overlapping surface perimeter first alignment grooves over the entire circumference of one of the semi-conductor elements that overlay each other, wherein the overlapping surface of the other semiconductor element and providing the second alignment grooves having a shape corresponding to the first groove, a plurality of metal balls into alignment grooves of these are arranged (claim 1).
According to this configuration, when the semiconductor element has a chip-on-chip structure, the grooves can be aligned via the metal sphere. Accordingly, the bumps can be reliably bonded to each other, and the manufacturing yield can be improved.
[0006]
Further, the radius of the metal sphere is set so that the height of the center of the metal sphere disposed in the groove is higher than the upper surface of the bump to be bonded when the semiconductor elements are overlapped with each other. It is necessary (Claim 2). This is because when the semiconductor elements are overlapped with each other, it is necessary to perform positioning by guiding the grooves with the metal balls before the bumps are joined. Further, when the metal ball hits the groove at the time of bonding, the impact applied to the bump can be reduced. Further, it can also serve to absorb stress applied to the substrate when the semiconductor device is used after bonding.
[0007]
The groove may be formed in the substrate of the semiconductor element or may be formed on a bump provided in the semiconductor element.
When formed on the bump provided in the semiconductor element, the stress applied to the semiconductor element can also be absorbed by the bump.
The bumps can also be used for electrode wiring on the element formation surface of the semiconductor element. Thereby, a part of the wiring in the element can be formed by using the bump, so that the element can be further integrated.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the embodiment of the present invention, it is assumed that Si is used as the semiconductor type, but other semiconductors such as GaAs and Ge may be used.
FIG. 1A is a perspective view of a main part of the semiconductor element 1. Bumps 3 are provided on the element formation surface of the semiconductor element 1, and grooves 2 are formed around the bumps 3, for example, at predetermined positions in the scribe line region. As a method for forming the groove, for example, a method of etching the substrate or cutting with a cutting tool can be used.
[0009]
The grooves 2 into a plurality of metal balls 4 are disposed (see Figure 1 (b)). The metal ball 4 is preferably made of a soft metal such as solder, Au, or Sn. As a method for arranging the metal spheres, it is conceivable that the worker puts one sphere into the groove 2 with tweezers while looking at the microscope. The method of pouring can be adopted.
[0010]
FIG. 2A is a cross-sectional view showing a state before another semiconductor element 1 is overlaid on the semiconductor element 1 on which the metal sphere is arranged, and FIG. 2B shows a state after being overlaid. It is sectional drawing. FIG. 3 is a perspective view showing a state in which semiconductor elements are overlapped with each other.
As shown in FIG. 2A, the radius of the metal sphere 4 is set such that the center of the metal sphere 4 is higher than the upper surface of the bump 3 when the metal sphere 4 is arranged in the groove. Actually, the radius of the metal sphere 4 is about several tens of μm at most.
[0011]
Other semiconductor elements 1 are grooves 2 over the entire circumference of the peripheral portion is formed, when the superimposed elements to each other, a plurality of metal balls 4, the groove 2, and guide grooves 2 grooves The two should be in the same position. More specifically, in the semiconductor element 1 drawn on the upper side in FIG. 3, a groove 2 (first groove) is formed over the entire periphery of the overlapping surface, and drawn on the lower side in FIG. A groove 2 (second groove) having a shape corresponding to the groove 2 of the upper semiconductor element 1 is formed on the overlapping surface of the semiconductor element 1.
In the state of FIG. 2 (a), when compressing together the semiconductor device (see FIG. 3), the groove 2 can align the groove 2, as shown in FIG. 2 (b), while aligning the semiconductor element The bumps 3 can be reliably bonded to each other.
[0012]
In addition, the metal sphere 4 deforms itself at the time of bonding, thereby relaxing the impact applied to the bump 3 at the time of bonding, and absorbing the stress applied to the bonded portion due to the warp of the substrate or the like even when the semiconductor device is used Fulfill.
FIG. 4 is a diagram illustrating a configuration according to a reference example. In the reference example of FIG. 4A , the groove 2 is formed in a part of the peripheral portion of the semiconductor element. Further, in the reference example of FIG. 4 (b), that have grooves 2 are provided at a plurality of positions of the peripheral portion of the semiconductor device.
[0013]
Further, the shape of the groove 2 is also arbitrary. For example, a groove 2c having a V-shaped cross section as shown in FIG. 5A and a groove 2d having a semicircular cross section as shown in FIG. Next, an embodiment of the invention in which bumps are provided at predetermined positions around the semiconductor element and grooves are formed thereon will be described.
FIG. 6 is a plan view of the semiconductor element 1, and elongated bumps 6 are provided around the element formation surface (hereinafter referred to as “peripheral bumps 6”). A groove 7 is formed in the peripheral bump 6, and a plurality of metal balls 4 are disposed here. It is possible to give the peripheral bump 3 a function as an electrode. For example, in FIG. 6, since the peripheral bump 6 is connected to the bump 3a as an electrode by the bridging bump 8, the peripheral bump 6 can be used as a ground line or a power supply line.
[0014]
FIG. 7 is a cross-sectional view showing a state in which the semiconductor elements 1 provided with the peripheral bumps 6 are joined to each other. Since the grooves 7 can be aligned by the metal balls 4, the bumps 3 of the semiconductor element can be reliably bonded.
The surrounding bumps 6 and the metal spheres 4 are deformed by themselves during bonding, so that the impact on the bumps 3 during bonding is reduced. Further, even when the semiconductor device is in use, it plays a role of absorbing stress applied to the bonded portion due to warpage of the substrate or the like.
[0015]
Further, in this configuration, when the peripheral bump 6 is used as an electrode, the peripheral bumps 3 of the upper and lower semiconductor elements 1 can be electrically connected by the metal ball 4.
FIG. 8 is a process diagram for explaining a method of forming the peripheral bump 6 with the groove 7.
[0016]
FIG. 8A shows a state in which the groove 2 is formed at a predetermined position on the substrate of the semiconductor element 1 in a direction perpendicular to the paper surface. As a method of forming the groove 2, any method such as partial etching or mechanical cutting can be adopted. Reference numeral 12 denotes an Al pad electrode.
A passivation film 13 such as SiN, SiON, SiO 2 , PSG or the like is formed on the entire surface from above (FIG. 8B). An example of a method for forming the passivation film 13 is plasma CVD.
[0017]
Next, as shown in FIG. 8 (c), a seed layer in which a TiW alloy layer for improving adhesion to the base and a layer of Au, Pt or the like for feeding a plating is laminated on the entire area of the substrate. 14 is deposited by a method such as sputtering.
Next, a photoresist 15 is applied except for a region to be bump plated. Then, the bump metal is thickly plated by electrolytic plating (FIG. 8D). Examples of the bump metal include Au, Pd, Pt, Ag, Ir (iridium), and the like. Instead of the electrolytic plating method, an electroless plating method that is a metal plating film formation method using a reducing action by a chemical reaction may be employed. In this case, as shown in FIG. 8E, the height for bump plating is set lower than the center position of the metal sphere when the metal sphere 4 is placed.
[0018]
Next, the photoresist 15 is removed, the surface seed layer 14 is removed, and an annealing process is performed to obtain a semiconductor element on which the bumps 3 and the peripheral bumps 6 are formed. This peripheral bump has a depression corresponding to the depth of the previously formed groove 2, which becomes the groove 7 along the peripheral bump. A metal ball 4 is disposed on the groove 7 (FIG. 8 (e)).
[0019]
The present invention is not limited to the embodiment described above, and various modifications can be made within the scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a perspective view of essential parts of a semiconductor device 1 according to the present invention.
2A is a cross-sectional view showing a state before another semiconductor element 1 is overlaid on the semiconductor element 1 on which the metal sphere is arranged, and FIG. 2B shows a state after being overlaid. It is sectional drawing.
FIG. 3 is a perspective view showing a state in which semiconductor elements are overlapped with each other.
4A is a plan view showing a state in which the groove 2 is formed in a part of the peripheral portion of the semiconductor element, and FIG. 4B is a plan view showing a state in which the groove 2 is formed in a plurality of locations in the peripheral portion of the semiconductor element. FIG.
FIG. 5 is a cross-sectional view of a groove.
FIG. 6 is a plan view of the semiconductor element 1 in which bumps are provided at predetermined positions around the semiconductor element and grooves are formed thereon.
FIG. 7 is a cross-sectional view showing a state in which semiconductor elements 1 provided with peripheral bumps 6 are joined together.
FIG. 8 is a process diagram for explaining a method of forming a peripheral bump 6 with a groove 7;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Groove 3 Bump 4 Metal sphere 6 Peripheral bump 7 Groove 12 Al electrode 13 Passivation film 14 Seed layer 15 Photoresist

Claims (2)

複数の半導体素子を重ねた構造を有する半導体装置であって、互いに重ね合わせる半導体素子のうちの一方の重ね合わせ面の周辺部全周に渡る位置合わせ用の第１溝を設け、他方の半導体素子の重ね合わせ面には前記第１溝に対応する形状の位置合わせ用の第２溝を設けて、これらの位置合わせ用の溝に複数の金属球が配置されていることを特徴とする半導体装置。A semiconductor device having a structure in which a plurality of stacked semiconductor elements, provided one of the overlapping surface perimeter first alignment grooves over the entire circumference of one of the semi-conductor elements that overlay each other, the other characterized in that the overlapping surface of the semiconductor device provided with a second alignment grooves having a shape corresponding to the first groove, a plurality of metal balls into alignment grooves of these is located A semiconductor device. 前記金属球の半径は、半導体素子同士を重ね合わせたときに、溝に配置された金属球の中心の高さが、接合するバンプの上面よりも高くなるように設定されていることを特徴とする請求項１記載の半導体装置。  The radius of the metal sphere is set such that the height of the center of the metal sphere disposed in the groove is higher than the upper surface of the bump to be bonded when the semiconductor elements are overlapped with each other. The semiconductor device according to claim 1.
JP04685399A 1999-02-24 1999-02-24 Semiconductor device Expired - Lifetime JP3721000B2 (en)

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JP04685399A JP3721000B2 (en) 1999-02-24 1999-02-24 Semiconductor device
US10/373,692 US6965166B2 (en) 1999-02-24 2003-02-27 Semiconductor device of chip-on-chip structure
US11/150,129 US7307349B2 (en) 1999-02-24 2005-06-13 Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface

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DE10308871B3 (en) * 2003-02-28 2004-07-22 Infineon Technologies Ag Semiconductor chip for use in semiconductor chip stack in complex electronic circuit with surface structure for alignment of stacked semiconductor chip
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