JP3320614B2 - Bonding method and bonding apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method and apparatus for bonding an inner lead corresponding to an electrode bump of a semiconductor chip.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become more compact, semiconductor devices, which are the main electronic components of those electronic devices, are also required to have higher capacities and smaller sizes. As means for manufacturing and assembling these semiconductor devices, for example, the inner leads (tips) of a film provided with intermittent input / output lead units are aligned with the corresponding electrode bumps on the semiconductor chip surface, and electric power is supplied. Connect
TAB (Tape Automated Bonding) method is adopted.
And the bonding equipment that implements this TAB method is
Since it does not have a function to automatically select and determine the inner lead to be connected and the electrode (for example, electrode bump) of the semiconductor chip, the operator generally looks at the video image from the ITV camera of the bonding device while watching the video image. Teaching partner to be bonded.

FIGS. 7A and 7B schematically show an embodiment of alignment between an inner lead and a corresponding electrode bump on a semiconductor chip surface in a conventional TAB method. In this bonding, as shown in FIG. 7 (a), when a part of the inner lead 1 and the electrode bump 3 on the surface of the semiconductor chip 2 are misaligned on the video image, as shown in an enlarged plan view, For example, with respect to the semiconductor chip stage 4 on which the semiconductor chip 2 is mounted, the adjustment of the XY-θ axis is repeated to partially enlarge the inner lead 1 as shown in FIG. The semiconductor chip 2 is set in a state where there is no misalignment with the electrode bumps 3.

In this way, when the position of the semiconductor chip stage 4 is determined and the position of the inner lead 1 and the position of the electrode bump 3 are accurately matched, the position is input to the bonding apparatus. When the bonding operation is performed continuously, two detection points are detected for each of the inner lead 1 and the electrode bump 3, and the positions of the inner lead 1 and the electrode bump 3 which are first input to the bonding apparatus side are detected. Semiconductor chip stage 4
The TAB method is implemented by correcting the position of.

After the completion of the above-described positioning, the bonding condition (bonding load) is set, and the bonding between the inner lead 1 and the electrode bump 3 is performed. here,
The bonding conditions are set according to the number of inner leads 1. For example, if each inner lead 1 (unit bonding position), for example, with a load of 0.2 (N) and 450 per inner lead (number of bonding positions), then 0.
Since 2 (N) x 450 = 90 (N), a load of 90 (N) is input. That is, each time the number of the inner leads 1 is different (each time the type is different), the corresponding bonding condition is input. FIG. 8 is a flowchart when the inner lead 1 and the electrode bump 3 are aligned and bonded in the TAB method.

[0006]

The above-mentioned TAB method has attracted attention in terms of productivity or mass productivity. However, conventional means have the following disadvantages, and still have problems such as yield and productivity. There is a problem in point.

First, since the position of the inner leads 1 and the electrode bumps 3 is set while the operator visually observes the image displayed on the monitor, many adjustments are required for accurate (accurate) adjustment of the XY-θ axes. Not only takes time,
It is feared that the yield is inferior. In other words, the time required to start up the bonding apparatus or change the product type becomes longer, which lowers the operation rate and adversely affects the productivity. In addition, since positioning and adjustment are performed visually by an operator, the position accuracy is reduced. There is a concern that the yield may decrease due to the problem.

Next, in the continuous bonding, both the inner lead 1 side and the electrode bump 3 side are 2
Alignment is performed by detecting a position. For example, if a part of the inner lead 1 is deformed, the alignment is performed ignoring the deformation, and therefore bonding is performed to cause a positional deviation defect or an outer lead deformation defect. There is fear.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made in consideration of the above circumstances, and is capable of performing highly reliable bonding without complicated operations even in the case of an inner lead having a narrow pitch. A method and a bonding apparatus are provided.

[0010]

According to a first aspect of the present invention, there is provided a method of bonding an electrode group provided on one main surface of a semiconductor chip to a corresponding inner lead group. and electrode coordinate information of the design value coordinates and semiconductor chips, detected the In'nari
Based on the two-point mark on the lead and the two-point mark on the electrode.
Then , the bonding method is characterized in that, for all of the inner leads, the positional relationship between the corresponding inner leads and the electrodes is coordinate-checked and positioned, and then the inner leads and the electrodes are joined.

According to a second aspect of the present invention, there is provided one main surface of a semiconductor chip.
Bore the electrode group provided above to the corresponding inner lead group.
In the bonding apparatus for bonding, the bond
The design value coordinates of the inner lead and
A function for inputting electrode coordinate information of the semiconductor chip;
Two-point mark on inner lead and two-point mark on the electrode
And a function for detecting each of the
Inner lead design value coordinates, semiconductor chip electrode coordinates
Information, the detected two-point mark of the inner lead and
And the two-point mark on the electrode,
For all leads, the corresponding inner leads and
The position of the electrodes is collated and the semiconductor chip stage
Operate X, Y, θ and corresponding inner leads and electrodes
And a mechanism for positioning
It is a binding device.

[0012]

[0013]

According to a third aspect of the present invention, there is provided a bonding apparatus for bonding an electrode group provided on one main surface of a semiconductor chip to a corresponding inner lead group, the bonding apparatus comprising: a design value coordinate of the inner lead; Equipped with a function to input chip electrode coordinate information,
And a mechanism for positioning the corresponding inner lead and the electrode by operating the X, Y, and θ of the semiconductor chip stage by coordinate-checking the positional relationship between the corresponding inner lead and the electrode; and setting the bonding load to the number of bonding locations × unit. A mechanism for inputting a load and controlling a bonding load.

According to a fourth aspect of the present invention, there is provided a bonding apparatus for bonding an electrode group provided on one principal surface of a semiconductor chip to a corresponding inner lead group, wherein the bonding apparatus comprises: a design value coordinate of the inner lead; It has a function of inputting the electrode coordinate information of the chip and the detection area information of the semiconductor chip, and performs coordinate matching of the positional relationship between the corresponding inner lead and the electrode based on the detection area information to perform X, Y, θ of the semiconductor chip stage. And a mechanism for positioning the corresponding inner lead and the electrode by operating the bonding load;
A mechanism for inputting as a unit load and controlling the bonding load.

That is, according to the present invention, when electrically connecting and joining the inner lead and the electrode on the semiconductor chip electrically and mechanically, the coordinates of the design value of the inner lead and the coordinate information of the electrode of the semiconductor chip are previously stored in the external device. It is assumed that input is made from. Here, the electrodes of the semiconductor chip are
Although a so-called electrode terminal may be used, a configuration in which a bump is formed and arranged on this electrode terminal surface may be used. Then, the coordinates of the input design values and the coordinate information are collated with the positional relationship between the image of the inner lead and the image of the electrode captured by an ITV camera, and if necessary, the chip stage is moved to the XY-axis.
After the θ adjustment, the positional relationship between the inner lead and the electrode is automatically corrected and adjusted, the corresponding inner lead and the electrode are bonded.

According to the means of the present invention, two alignment marks of the inner lead and two alignment marks of the electrode imaged by the ITV camera are input, respectively, while the design value of the TAB inner lead design value input from outside in advance is input. The coordinate and the coordinate information of the electrode bump of the semiconductor chip to be bonded are coordinate-checked, and the position of the corresponding inner lead and electrode bump is automatically adjusted based on the coordinate check. That is, since the position is not visually adjusted by the operator, the mass production or the productivity is high, and the positioning is performed with high accuracy, so that highly reliable bonding can be performed.

In addition to the coordinates of the design values and the so-called reference values of the coordinate information, when the detection area information of the semiconductor chip is also input, and when various bonding condition data are input, these detection values are detected. According to the area information and the bonding condition data, the detection target area can be set in advance, the selection and setting of the bonding condition can be automated, and the automation of the bonding operation can be easily performed.

[0019]

FIG. 1, FIG. 2, FIG. 3, FIG.
An embodiment will be described with reference to FIGS. FIG.
FIG. 1 is a perspective view showing a main part configuration of a bonding apparatus according to a first embodiment. This bonding equipment
Basically, although not different from the conventional case, the coordinates of the design values of the inner leads and the coordinate information of the electrodes (for example, electrode bumps) of the semiconductor chip to be bonded can be externally input. The difference is that it has a function that can collate the positional relationship between the image and the ITV camera image. Specifically, this bonding apparatus is configured as follows.

That is, the TAB tape transport system 5 and the TB
A semiconductor chip stage 6 disposed along and close to the AB tape transport system 5, a drive mechanism 7 for operating the semiconductor chip stage 6 in XY-θ, and a semiconductor chip 8 mounted on the semiconductor chip stage 6; The semiconductor chip transport system 9 for transporting and the TAB tape transport system 5
A first ITV camera 11 for taking an image of the unit inner lead portion 10 'of the TAB tape 10 and inputting a two-point mark of the unit inner lead portion 10', and a semiconductor chip 8 mounted above the semiconductor chip stage 6; A second ITV camera that captures 12 groups of electrode bumps and inputs the two-point mark of 12 groups of electrode bumps
13 and.

Further, a memory unit 14 for inputting design value coordinates of the unit inner lead portion 10 'of the TAB tape 10 and coordinate information (for example, CAD data and floppy) of the group of electrode bumps 12 of the semiconductor chip 8; ITV
The corresponding two-point marks from the cameras 11 and 13 are used for coordinate matching with the design value coordinates of the unit inner lead portion 10 ′ and the coordinate information of the electrode bumps 12 group of the semiconductor chip 8 input to the memory portion 14. The semiconductor chip stage 6 is moved to the X-
A control system 16 for controlling the Y-θ drive (positioning) drive mechanism 7 and a bonding means 17 for pressing and bonding the corresponding and aligned unit inner lead portions 10 ′ and the electrode bumps 12 are provided. ing.

Next, T
The positioning and bonding operation of the semiconductor chip 8 with respect to the AB tape 10 will be described.

FIG. 2 shows a TAB tape in this embodiment.
FIG. 4 is a plan view conceptually showing a state of alignment of the semiconductor chip 8 with respect to 10, and FIG. 3 is a flowchart showing an implementation procedure. First, a TAB tape in the memory unit 14
The design value coordinates of the ten unit inner lead portions 10 'and the coordinate information of the electrode bumps 12 of the semiconductor chip 8 are input. Thereafter, the TAB tape 10 is transported intermittently by the TAB tape transport system 5, and the semiconductor chip 8 is transported and set on the semiconductor chip stage 6 by the semiconductor chip transport system 9.

At this stage, the corresponding unit inner lead portion 10 'of the TAB tape transport system 5 is read by the first ITV camera 11, and the two-point marks 10a, 10b previously attached to the unit inner lead portion 10'. Is input to the memory unit 14.
The second ITV camera 13 reads the group of electrode bumps 12 of the semiconductor chip 8 on the semiconductor chip stage 6, and the two-point marks 12a, 12a,
12b is also input to the memory unit 14.

The two-point marks 10a, 10b of the unit inner lead portion 10 'and the two-point marks 12a, 12a,
Corresponding to the input information of 12b, the design value coordinates of the unit inner lead portion 10 'and the coordinate information of the group of electrode bumps 12 of the semiconductor chip 8 are read out from the memory portion 14, and the coordinate matching means 15 performs coordinate matching.

In the above operation, when coordinates detected for all the leads of the unit inner lead portion 10 'and the electrode bumps 12 are within the permissible range with respect to the design value coordinates, the semiconductor chip stage 6 is attached to the TAB tape. The unit moves to the ten unit inner lead portions 10 ', and the electrode bumps 12 on the surface of the semiconductor chip 8 and the corresponding inner lead groups are collectively bonded. On the other hand, in the coordinate verification, when the detected coordinate value with respect to the design value coordinate exceeds the allowable range, the unit inner lead portion 10 'of the TAB tape 10 is carried out (without performing bonding) and newly conveyed. The detection operation and the coordinate collation are performed in the same manner as described above for the unit inner lead portion 10 'of the next stage, and the bonding is continuously advanced.

In the above bonding, the TAB tape 10
That the unit inner lead portion 10 'and the electrode bumps 12 of the semiconductor chip 8 can be easily aligned and collated.
The time required for setting up the bonding operation and setting up when changing the product type is greatly reduced. In other words, the time required for position adjustment and collation can be greatly reduced to about 1/2 to 1/3 as compared with the position adjustment and position adjustment performed visually by the operator at one time. In addition, since there is no variation in position accuracy due to individual differences, the quality and yield can be improved. In particular, after detecting the current state of all the inner leads, it is possible to prevent positional deviation defects such as deformation of the inner leads due to TAB tape by collation with the design value coordinates beforehand.
This will greatly contribute to improving the yield.

FIGS. 4A and 4B are plan views conceptually showing an embodiment of the second embodiment. This embodiment is different from the first embodiment in the following points.
That is, the coordinates of the design values of the inner leads and the electrodes (for example, electrode bumps) of the semiconductor chip to be bonded
The difference is that in addition to the coordinate information described above, the position detection area information of the semiconductor chip is input from the outside, and a function that allows the input data and the ITV camera image to perform the coordinate collation of the positional relationship is the difference. .

Next, the bonding operation will be described with reference to FIG.
This will be described with reference to the flowchart of FIG. First, the design value coordinates of the unit inner lead portion 10 ′ of the TAB tape 10, the position detection area information 12 a ′ of the semiconductor chip 8,
12b 'and the coordinate information of the electrode bumps 12 of the semiconductor chip 8 are input. Here, the position detection area information
12a 'and 12b' are two-point marks for positioning 12a and 12b
It has a shape that includes After that, TAB tape transport system 5
While the TAB tape 10 is intermittently conveyed, the semiconductor chip 8 is conveyed and set on the semiconductor chip stage 6 by the semiconductor chip conveying system 9.

At this stage, the corresponding unit inner lead portion 10 'of the TAB tape transport system 5 is read by the first ITV camera 11, and the two-point marks 10a, 10b previously attached to the unit inner lead portion 10'. Is input to the memory unit 14.
The second ITV camera 13 reads the group of electrode bumps 12 of the semiconductor chip 8 on the semiconductor chip stage 6, and positions the two groups of positioning marks 12a and 12b near the group of electrode bumps 12 in advance. Detection area information 12a ', 1
2b 'is also input to the memory unit 14.

Corresponding to the input information on the two-point marks 10a and 10b of the unit inner lead section 10 'and the position detection area information 12a' and 12b 'of the electrode bump 12, the memory section 14 sends the unit inner lead section 10'. Design value coordinates and position detection area information 12a ', 12b' of the semiconductor chip 8
Are read out, and the primary position is adjusted. Then, the coordinate information of the electrode bumps 12 is read out, and the coordinate matching means 15 performs the two-point mark 12a, 12b coordinate matching.

When the coordinates of all the leads of the unit inner lead portion 10 'and the electrode bumps 12 are collimated by the above operation and the detected coordinate values with respect to the design value coordinates are within the allowable range, the semiconductor chip stage 6 is connected to the TAB tape. The unit moves to the ten unit inner lead portions 10 ', and the electrode bumps 12 on the surface of the semiconductor chip 8 and the corresponding inner lead groups are collectively bonded. On the other hand, in the coordinate verification, when the detected coordinate value with respect to the design value coordinate exceeds the allowable range, the unit inner lead portion 10 'of the TAB tape 10 is carried out (without performing bonding) and newly conveyed. The detection operation and the coordinate collation are performed in the same manner as described above for the unit inner lead portion 10 'of the next stage, and the bonding is continuously advanced.

FIG. 5 is a block diagram of a bonding apparatus according to the third embodiment. This embodiment also has basically the same configuration as the first embodiment (see FIG. 1). For example, a configuration is adopted in which not only coordinate information of the electrode bumps 12 group but also lead area information (bonding area... Corresponding to the number of leads) is input from CAD or a floppy disk. Here, since the reading by the ITV cameras 11 and 13 and the collation of the coordinate information with the coordinate information, the correction of the XY-θ axis, and the like are as described above, the description thereof will be omitted. On the other hand, based on the lead area information, the load is calculated by the set load calculator of the memory unit 14, and the required load is selected and set by the load converter and applied to the bonding tool. That is, the die bond load is calculated based on the read lead area information, the load is automatically set, and the bonding proceeds.

FIG. 6A is a sectional view schematically showing a bonding mode of the fourth embodiment, and FIG. 6B is a plan view schematically showing a bonding mode. That is, T
Although the bonding between the inner leads of the AB tape and the electrode bumps 12 of the semiconductor chip 8 has been exemplified, LOC (Lead
on chip) method. More specifically,
On the electrode forming surface of the semiconductor chip 8 ′ having no electrode bumps 12, a group of inner leads 1 is disposed via an insulating tape 18, and the tips of the inner leads 1 and the electrodes on the surface of the semiconductor chip 8 ′ are LOC to wire bond 19
The present invention can be similarly applied to a bonding method or a bonding apparatus of a system.

The present invention is not limited to the above-described configuration, and various modifications can be made without departing from the spirit of the present invention. For example, the inner lead may be of a so-called lead frame type as well as being installed on a TAB tape.

[0036]

As can be seen from the above description, according to the first and second aspects of the present invention, a high-quality semiconductor device can be manufactured with high yield while ensuring high productivity or mass productivity.

Further, according to the third to sixth aspects of the present invention, it is possible to provide a high-quality semiconductor device with a high operation rate and a high productivity at a high yield.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a main configuration of a bonding apparatus according to a first embodiment.

FIG. 2 shows a TAB in the bonding apparatus shown in FIG. 1;
FIG. 4 is a plan view schematically showing an embodiment of alignment between an inner lead portion of a tape and an electrode bump of a semiconductor chip.

FIG. 3 is a flowchart for explaining the bonding operation of the first embodiment.

FIG. 4 is a plan view schematically showing an embodiment of positioning of an inner lead portion of a TAB tape and an electrode bump of a semiconductor chip in a bonding apparatus according to a second embodiment.

FIG. 5 is a block diagram illustrating a schematic configuration of a bonding apparatus according to a third embodiment.

FIGS. 6A and 6B show an embodiment of the fourth embodiment, in which FIG. 6A is a cross-sectional view and FIG. 6B is a plan view.

FIGS. 7A and 7B are plan views schematically showing an embodiment of alignment between a conventional inner lead portion of a TAB tape and an electrode bump of a semiconductor chip.

FIG. 8 is a flowchart for explaining a conventional bonding operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Inner lead 2,8,8 '... Semiconductor chip 3,12 ... Electrode bump (electrode) 4,6 ... Semiconductor chip stage 5 ... TAB tape transport system 7 ... Semiconductor chip stage drive mechanism 9 ... ... Semiconductor chip transport system 10 ... TAB tape 10 ', 19 ... Inner lead part 10a, 10b ... Inner lead part mark 11 ... First ITV camera 12a, 12b ... Electrode bump group mark 12a' 12b '... … Position detection area information 13… Second ITV camera 14… Memory unit 15… Coordinate collating means 16… Control system of drive mechanism 17… Bonding means 18… Insulating tape

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-2-250345 (JP, A) JP-A-4-321247 (JP, A) JP-A-2-218142 (JP, A) JP-A-2- 250343 (JP, A) JP-A-3-72645 (JP, A) JP-A-4-33349 (JP, A) JP-A-4-102339 (JP, A) JP-A-6-66028 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/60

Claims (4)

(57) [Claims] In a method of bonding an electrode group provided on one main surface of a semiconductor chip to a corresponding inner lead group, a design value coordinate of the inner lead and electrode coordinate information of the semiconductor chip which are input in advance. And the detection
The two-point mark of the inner lead and the electrode
Based on the two-point mark, all of the inner leads
And a method of bonding the inner lead and the electrode after positioning the corresponding inner lead and the electrode by coordinate matching. 2. A bonding apparatus for bonding an electrode group provided on one main surface of a semiconductor chip to a corresponding inner lead group, the bonding apparatus comprising: a design value coordinate of the inner lead; and electrode coordinate information of the semiconductor chip. And the function of the inner lead
Two-point mark and two-point mark of the electrode are detected respectively
And a function of the input inner lead.
Design value coordinates, semiconductor chip electrode coordinate information,
The two-point mark of the inner lead and the two-point mark of the electrode
Based on the dot marks, all of the inner leads
Te, X of the corresponding inner leads and the semiconductor chip stage the positional relationship with the coordinate matching electrode, Y, characterized by comprising a mechanism for positioning the inner lead and the electrode corresponding by operating the θ to Bonding equipment. 3. A bonding apparatus for bonding an electrode group provided on one main surface of a semiconductor chip to a corresponding inner lead group, the bonding apparatus comprising: a design value coordinate of the inner lead and electrode coordinate information of the semiconductor chip. And a mechanism for positioning the corresponding inner lead and electrode by operating the X, Y, and θ of the semiconductor chip stage by coordinate-checking the positional relationship between the corresponding inner lead and electrode; and a bonding load. Is input as the number of bonding points x unit load,
A mechanism for controlling a bonding load. 4. A bonding apparatus for bonding an electrode group provided on one main surface of a semiconductor chip to a corresponding inner lead group, the bonding apparatus comprising: a design value coordinate of the inner lead; and electrode coordinate information of the semiconductor chip. And a function for inputting the detection area information of the semiconductor chip. The position relation of the corresponding inner lead and electrode is coordinate-matched based on the detection area information to operate the X, Y, and θ of the semiconductor chip stage. A bonding apparatus comprising: a mechanism for positioning an inner lead and an electrode; and a mechanism for controlling a bonding load by inputting a bonding load as the number of bonding locations × a unit load.