JP3313664B2 - Test method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor device having a DA converter and an AD converter.

[0002]

2. Description of the Related Art In a semiconductor device equipped with a DA converter and an AD converter, when testing the DA converter and the AD converter, it is necessary to examine an analog signal output from the DA converter and an analog signal input to the AD converter. Therefore, an expensive semiconductor device test device for analog testing has been used as a semiconductor device test device. FIG. 20 is a block diagram showing an example of a conventional semiconductor device. The semiconductor device 940 includes a DA converter 902 and an AD converter 903. The output of the DA converter 902 is connected to a terminal 915 and the AD converter 90
3 inputs are connected to terminals 916 respectively. When the test is executed, the selectors 905 and 906 are controlled under the control of the test control circuit 904 so that a test digital signal can be supplied to the DA converter from the terminal 913 through the selector 905, and the AD converter 903 outputs the signal. The digital signal is supplied to the terminal 91 through the selector 906.
4 can be obtained.

An analog signal output from the DA converter 902 when a test digital signal is input from a terminal 913 is obtained through a terminal 915. When a test analog signal is input through the terminal 916, A
The digital signal output from the D converter 903 is supplied to a terminal 91
Get 4 more. The supply of the test signal and the acquisition of the converted signal are performed by the analog test device, and the test signal supplied to the semiconductor device is compared with the converted signal output by the semiconductor device in the test device to thereby provide a DA converter. 902, pass / fail of the AD converter 903 is determined.

[0004] However, since a semiconductor device test device for analog testing is extremely expensive, the provision of such a test device causes an increase in equipment cost, which is not desirable.
Therefore, as a method of testing a DA converter and an AD converter without using a test device for an analog test,
As in the semiconductor device shown in FIG.
When both the D converters are mounted, it is conceivable to test the DA converter and the AD converter by connecting the analog output of the DA converter and the analog input of the AD converter in the semiconductor device.

[0005] However, since the change width and the DC level of the output signal of the DA converter and the change width and the DC level of the input signal of the AD converter are different even if the resolution of the DA converter and the AD converter are the same,
Simply connecting the output of the D / A converter to the input of the A / D converter does not allow a complete test to be performed in all signal ranges. If the resolution of the DA converter and the resolution of the AD converter are different, the test cannot be performed with the required resolution because the pitch of change is different even if the change width and the DC level of the signal are the same.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem.
Converter output signal change width and DC level and AD
Even if the change width and the DC level of the input signal of the converter are different and the resolution of the DA converter and the AD converter are different, the test of the DA converter and the AD converter can be performed without using the test equipment for the analog test. It is an object of the present invention to provide a test method of a semiconductor device which can be performed.

[0007]

According to the present invention, there is provided a method for testing a D / A converter and an A / D converter constituting a semiconductor device, wherein a signal is supplied to the D / A converter from outside the semiconductor device. Input, attenuate or amplify the output signal of the DA converter in the semiconductor device, change the DC level of the output signal of the DA converter in the semiconductor device, attenuate or amplify, and Is supplied to the AD converter, the output signal of the AD converter is taken out of the semiconductor device, and the input signal of the DA converter and the output of the AD converter are output outside the semiconductor device. Whether the test results of the DA converter and the AD converter are good It is determined that the resolution of the DA converter is lower than the resolution of the AD converter, and N is a natural number, and the width of the change range of the signal supplied to the AD converter is the width of the input range of the AD converter as 2 N times. The output signal of the D / A converter is attenuated so as to match the divided width, and then the change range of the signal supplied to the A / D converter is obtained by dividing the input range of the A / D converter by 2N. The attenuated DC level of the output signal of the DA converter is sequentially changed so as to match each of the divided ranges. Further, the present invention provides a DA converter and an AD converter constituting a semiconductor device.
A method for testing a converter, comprising: inputting a signal from outside the semiconductor device to the DA converter;
The output signal of the converter is attenuated or amplified in the semiconductor device, the DC level of the output signal of the DA converter is changed in the semiconductor device, the attenuated or amplified, and the DC level is changed. The output signal of the converter is supplied to the AD converter,
The output signal of the converter is taken out of the semiconductor device, and the input signal of the D / A converter and the output signal of the A / D converter are compared outside the semiconductor device to determine whether the test results of the D / A converter and the A / D converter are good. The resolution of the D / A converter is higher than the resolution of the A / D converter, and the width of each range obtained by dividing the output range of the D / A converter by 2 N and taking N as a natural number is equal to the input of the A / D converter. Each range obtained by amplifying the output signal of the D / A converter so as to match the width of the range and equally dividing the change range of the output signal of the D / A converter by 2 to the Nth power is referred to as the A / D converter. And sequentially changing the DC level of the amplified output signal of the DA converter so as to match the input range. To.

Further, the present invention provides a semiconductor device comprising a D
A method for testing an A converter and an AD converter, comprising: inputting a signal to the DA converter from outside the semiconductor device; attenuating or amplifying an output signal of the DA converter in the semiconductor device; Changing the DC level of the output signal in the semiconductor device, attenuating or amplifying, and supplying the output signal of the DA converter with the changed DC level to the AD converter, and changing the output signal of the AD converter to Taking out the semiconductor device, and comparing the input signal of the DA converter and the output signal of the AD converter outside the semiconductor device to determine whether the test results of the DA converter and the AD converter are good or not,
The resolution of the converter is higher than the resolution of the AD converter, and N is a natural number, and the DA converter is designed so that the output range of the DA converter is divided by 2 to the Nth power and equally divided so that signals in each range have a specific DC level. Changing the DC level of the output signal, and amplifying the output signal of the DA converter so that the signals in each of the equally divided ranges change in accordance with the input range of the AD converter. And

Further, the present invention provides a semiconductor device comprising a D
A method for testing an A converter and an AD converter, comprising: inputting a signal to the DA converter from outside the semiconductor device; attenuating or amplifying an output signal of the DA converter in the semiconductor device; Changing the DC level of the output signal in the semiconductor device, attenuating or amplifying, and supplying the output signal of the DA converter with the changed DC level to the AD converter, and changing the output signal of the AD converter to Taking out the semiconductor device, and comparing the input signal of the DA converter and the output signal of the AD converter outside the semiconductor device to determine whether the test results of the DA converter and the AD converter are good or not,
The converter and the A / D converter have the same resolution, and the change amount of one pitch of the output signal of the D / A converter is larger than half of the change amount of one pitch of the input signal of the A / D converter, and N is a natural number of 2 or more. The above D
The output signal of the D / A converter is attenuated so that the output signal of the A converter changes within a width obtained by dividing the input range of the A / D converter into N equal parts, and then the attenuated change of the output signal of the D / A converter is performed. The attenuated DC level of the output signal of the DA converter is changed so that the range matches each of the input range of the AD converter divided into N equal parts.

In the semiconductor device testing method of the present invention, the DA
The output signal of the converter is attenuated or amplified in the semiconductor device, and the DC level of the output signal of the DA converter is changed in the semiconductor device and supplied to the AD converter. Therefore, even if the output range of the D / A converter is different from the input range of the A / D converter, the test can be performed by matching the output range and the A / D converter.
Even if the resolution of the D converter is different, amplify the output signal of the D / A converter to 2N times as a natural number or attenuate it to 1 / Nth power and perform the test at the required resolution. Can be. As a result, in the method of testing a semiconductor device according to the present invention, no expensive test device for analog testing is required.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a block diagram showing an example of a semiconductor device in a method of the present invention, and FIGS. 2A to 2D are graphs for explaining the operation of the semiconductor device of FIG. is there. Hereinafter, a first embodiment of a method for testing a semiconductor device according to the present invention will be described with reference to these drawings.

The semiconductor device 40 shown in FIG. 1 includes a digital signal processing circuit 1 including a logic circuit for performing arithmetic processing and the like and a temporary storage memory, and converts a digital signal processed by the digital signal processing circuit 1 into an analog signal. DA to convert
A converter 2A and an A for converting an analog signal into a digital signal for performing signal processing in the digital signal processing circuit 1
And a D converter 3A.

The semiconductor device 40 selects one of a test digital signal input from a plurality of input terminals 13 and a digital signal output from the digital signal processing circuit 1 and supplies the selected digital signal to the DA converter 2A. The digital signal processing circuit 1 includes a selector 5, a digital signal processing circuit 1, and a selector 6 that selects and outputs a digital signal from one of a plurality of output terminals 14.
Here, the input terminal 13 and the selector 5 constitute signal input means according to the present invention, and the selector 6 and the output terminal 1
Reference numeral 4 denotes signal output means according to the present invention.

Further, the semiconductor device 40 comprises an analog switch 7 for switching the analog output signal of the DA converter 2A to one of the output terminal 15 and the attenuator 9, and outputting the analog output signal; and an attenuator 9 for attenuating the analog output signal of the DA converter 2A. And a level shifter 10A for changing a DC level of an output signal of the attenuator 9;
And an analog signal input from the input terminal 16;
Select one of the output signals of the level shifter 10A and
It has an analog switch 8 (signal supply means according to the present invention) for supplying to the D converter 3A, and a test control circuit 4. The test control circuit 4 supplies a control signal to the digital signal processing circuit 1, the selector 5, the selector 6, the analog switch 7, the analog switch 8, etc.
It is configured to control to perform a test of the converter and the AD converter. The analog switch 7,
8, the attenuator 9, and the level shifter 10A constitute an analog test block 30. The above-described components of the semiconductor device 40 are mounted on a single semiconductor substrate.

FIG. 16 is a circuit diagram showing an example of the attenuator 9, and FIG. 18 is a circuit diagram showing an example of the level shifter.
As shown in FIG. 16, the attenuator 9 has a configuration in which a signal input from an input terminal 50 is divided by a resistor 52 and a resistor 53 and output to an output terminal 51. The attenuator 9 is not limited to the one having such a configuration, and may be, for example, a level shifter 10 described later.
The circuit constant of A may be set so as to attenuate the input signal so that the level shifter 10A also has a function as an attenuator. In the present embodiment, the level shifter 10A is connected to the input terminal 5 as shown in FIG.
By adding a voltage obtained by dividing the power supply voltage 62 by the resistors 63 and 64 to the signal input from
The DC level of the input signal is changed.

Next, the semiconductor device 4 configured as described above
0, the DA converter 2A and the AD converter 3
How to test A will be described in detail. Here, the DA converter 2A and the AD converter 3A have the same resolution, and the DA converter 2A has an output range wider than the input range of the AD converter 3A.
Note that the input range of the AD converter refers to a range from the minimum value to the maximum value of the input signal of the AD converter, and a value represented by a digital signal output from the AD converter when the input signal of the minimum value is supplied, that is, the output The code has the minimum value, and the output code of the AD converter has the maximum value when the input signal having the maximum value is supplied. The output range of the DA converter refers to a range from the minimum value to the maximum value of the output signal of the DA converter. When the input code of the minimum value (the code represented by the input digital signal) is supplied, the DA converter outputs the minimum value. And the DA converter outputs the maximum value output signal when the maximum value input code is supplied.

First, a predetermined signal is input to the external terminal 12 to set a test mode. Thereby, the test control circuit 4 controls the selector 5 and the selector 6, and
The digital signal from the external terminal 13 is a DA converter 2A
And the output signal of the AD converter 3A is output to the external terminal 14. The test control circuit 4 also controls the analog switch 7 and the analog switch 8 so that the output signal of the DA converter 2A is input to the attenuator 9 and the output signal of the level shifter 10A is input to the AD converter 3A.

In this state, a test digital signal is input from the external terminal 13 and the code value is changed at a constant speed.
Increase the binary number by one. In the present embodiment, the attenuation of the attenuator 9 is set as follows. That is, the output signal of the DA converter 2A is attenuated by the attenuator 9 such that the width of the change range of the signal supplied to the AD converter 3A matches the width of the input range of the AD converter 3A. The shift amount of the level shifter 10A is set as follows. That is, the output signal of the DA converter 2A, that is, the DC level of the output signal of the attenuator 9 is changed by the level shifter 10A so that the signal supplied to the AD converter 3A changes in accordance with the input range of the AD converter 3A. .

FIG. 2A shows the input code of the DA converter 2A and the DA converter 2A in the semiconductor device 40.
(B) shows the change over time of the output voltage of the attenuator 9. In addition, FIG.
Indicates a time change of the output voltage of the level shifter 10A,
(D) shows the relationship between the input voltage and the output code of the AD converter 3A.

As shown in FIG. 2A, when the input code of the DA converter 2A increases at a constant speed, the DA
The output voltage (output signal) of the converter 2A is also constant,
The voltage increases in proportion to the input code, and this voltage is supplied to the attenuator 9. Since the attenuation of the attenuator 9 is set as described above, the width of the change range of the output voltage (output signal) of the attenuator 9 is, as shown in FIG. 2B, the input range of the AD converter 3A. Match the width of The DC voltage of the output voltage of the attenuator 9 is changed by the level shifter 10A.
Since A is set as described above, the level shifter 1
The output voltage of 0A changes in accordance with the input range of the AD converter 3A.

Since the output signal of the AD converter 3A is output from the external terminal 14 through the selector 6,
By comparing the value of this digital signal with the expected value,
It is possible to determine whether the DA converter 2A and the AD converter 3A are operating correctly. As described above, in the present embodiment, although the DA converter 2A has an output range wider than the input range of the AD converter 3A, the entire output range of the DA converter 2A and the entire input range of the AD converter 3A. The test can be performed at Therefore, no expensive test equipment for analog testing is required.

Second Embodiment Next, a test method for a semiconductor device according to a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a semiconductor device according to the second embodiment, and FIGS. 4A to 4D are graphs for explaining the operation of the semiconductor device of FIG. In FIG. 3, the same elements as those in FIG. 1 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

The semiconductor device 140 shown in FIG. 4 differs from the semiconductor device 40 in that an analog test block 130 using an amplifier 117 instead of the attenuator 9 is provided. FIG. 17 is a circuit diagram showing the amplifier 117 in detail. As shown in FIG. 17, the amplifier 117 includes:
It is a non-inverting amplifier using an OP amplifier, and is configured to amplify a signal input from an input terminal 54 at an amplification factor determined by a ratio of a resistor 57 to a resistor 58 and output the amplified signal to an output terminal 55. Note that the circuit constant of the level shifter 10A is
It is also possible to adopt a configuration in which the amplifier 117 is not separately provided as a circuit in which the input signal is set to be amplified and the level shifter 10A has both functions of the amplifier and the level shifter.

Next, the operation of the semiconductor device 140 will be described. Here, the DA converter 102B and the AD converter 103B have the same resolution,
B has an output range narrower than the input range of the AD converter 103B. First, as in the above case,
A predetermined signal is input to the external terminal 12 to set a test mode. Thus, the selectors 5 and 6 and the analog switches 7 and 8 are set by the test control circuit 4 in the same manner as in the case of the semiconductor device 40. DA converter 10
The output signal of 2B is amplified by the amplifier 117 so that the width of the change range matches the width of the input range of the AD converter 3A (FIGS. 4A and 4B). Then, the DA converter 10 amplified by the amplifier 117
The DC level of the output signal of 2B is shifted by the level shifter 10A, and the change range of the output signal of the level shifter 10A matches the input range of the AD converter 103B (FIGS. 4B, 4C, 4C). D)). Therefore, also in the second embodiment, a test digital signal is input from the external terminal 13 and the external terminal 14
By comparing the value of the digital signal output from the A / D converter with the expected value, a test can be performed in the entire output range of the DA converter 102B and the entire input range of the AD converter 103B. Not necessary at all.

Next, a method of testing a semiconductor device according to a third embodiment of the present invention will be described. FIG. 5 is a block diagram showing a semiconductor device according to the third embodiment, FIGS. 6A and 6B are graphs showing the operation of an attenuator included in the semiconductor device of FIG. 5, and FIG. 6F are graphs for explaining the operation of the semiconductor device of FIG. In FIG. 5, the same elements as those in FIG. 1 are denoted by the same reference numerals, and a detailed description thereof will be omitted here.

The semiconductor device 240 shown in FIG. 5 differs from the semiconductor device 40 in that an analog test block 230 using a level shifter 210B instead of the level shifter 10A is provided. FIG. 19 shows the level shifter 2
It is a circuit diagram which shows 10B in detail. As shown in FIG. 19, the level shifter 210B responds to an analog input signal input from the input terminal 74 with a resistor 78, a resistor 79,
And adding the voltage selected by the analog switch 88 among the voltages obtained by dividing the power supply voltage 62 by the resistor 80, thereby changing the DC level of the input signal,
Output to the output terminal 75. The analog switch 83 is controlled by a control signal input from the test control circuit 4 through the input terminal 73 to switch the voltage to be added to the input signal, and as a result, the shift amount of the DC level of the input signal changes.

Next, the operation of the semiconductor device 240 will be described. Here, it is assumed that the DA converter 202C has a lower resolution by one bit than the AD converter 203C. First, as in the case described above, a predetermined signal is input to the external terminal 12 to set the test mode. Thus, the selectors 5 and 6 and the analog switches 7 and 8 are set by the test control circuit 4 in the same manner as in the case of the semiconductor device 40. In the present embodiment, the attenuator 9 attenuates the output signal of the DA converter 202C. At this time, as shown in FIGS. 6A and 6B, one pitch of the output signal of the DA converter 202C is used. The output signal of the DA converter 202C is attenuated so that the amount of change matches the amount of change in one pitch of the input signal of the AD converter 203C. In the graph of FIG. 6A, the horizontal axis represents the input code of the DA converter 202C, and the vertical axis represents the output voltage of the DA converter. In the graph of FIG. 6B, the horizontal axis represents the AD converter 203.
C represents an output code, and the vertical axis represents an input voltage of the AD converter.

The change amount of one pitch in the output signal (output voltage) of the DA converter means that the input code is 2
This is the amount of change in the output signal of the D / A converter when the value changes by 1 in radix. On the other hand, the change amount of one pitch of the input signal (input voltage) of the AD converter is a change amount of the input signal of the AD converter such that the output code changes by one binary number.

At this time, as shown in FIGS. 7A and 7B, the attenuator 9
The output signal of the DA converter is attenuated so that the change width of the signal supplied to C is equal to the width of the input range of the AD converter divided by 2. Thereafter, the level shifter 210B first operates as shown in FIGS.
As shown in (D), the output signal of the D / A converter is changed so that the signal supplied to the A / D converter changes in the lower range among the equally divided ranges obtained by dividing the input range of the A / D converter by two. Change the DC level of

Therefore, in this state, the external terminal 13
By inputting a digital signal for test from the external terminal 14 and comparing the value of the digital signal output from the external terminal 14 with the expected value, the entire output range of the DA converter 202C and the lower half of the input range of the AD converter 203C are obtained. Test can be performed.

Next, a predetermined signal is input from the external terminal 12 to operate the test control circuit 4, and the level shifter 210B
7B, the output signal of the DA converter 202C attenuated by the attenuator B209 is changed to the input range of the AD converter 203C as shown in FIGS. 7B, 7E, and 7F. To change in the upper half range. Then, in this state, a digital signal for testing is input from the external terminal 13 and the value of the digital signal output from the external terminal 14 is compared with an expected value, whereby the entire output range of the DA converter 202C and the AD converter Testing can be performed on the upper half of the 203C input range.

As described above, in the third embodiment, the input range of the AD converter 203C is divided into the lower half and the upper half by the attenuator 9 and the level shifter 210B, so that the AD converter 203C is one bit larger than the AD converter 203C. With the DA converter 202C having only a low resolution, a test can be performed without reducing the resolution in the entire input range of the AD converter 203C. Here, it is assumed that the resolution of the AD converter is one bit larger than the resolution of the DA converter. However, if the resolution of the AD converter is N bits larger than the resolution of the DA converter, the input of the AD converter is performed by the attenuator 9 and the level shifter. Similarly, by dividing the range by 2 N and equally dividing, the entire input range of the AD converter can be tested without reducing the resolution.

Next, a method of testing a semiconductor device according to a fourth embodiment of the present invention will be described. FIG. 8 is a block diagram showing a semiconductor device according to the fourth embodiment, FIGS. 9A and 9B are graphs showing the operation of an attenuator included in the semiconductor device of FIG. 8, and FIG. 8 (F) is a graph for explaining the operation of the semiconductor device of FIG. In FIG. 8, the same elements as those in FIGS. 3 and 5 are denoted by the same reference numerals, and a detailed description thereof will be omitted here.

The semiconductor device 340 shown in FIG. 8 differs from the semiconductor device 240 in that an analog test block 330 using an amplifier 117 instead of the attenuator 9 is provided. Here, the DA converter 302D
Is 1 bit higher in resolution than the AD converter 303D. First, as in the case described above, a predetermined signal is input to the external terminal 12 to set the test mode. Thereby, the selectors 5 and 6 and the analog switches 7 and 8 are controlled by the test control circuit 4 to the semiconductor device 240.
Is set in the same way as In the present embodiment, the amplifier 117 amplifies the output signal of the DA converter 302D. At this time, as shown in FIGS. 9A and 9B,
The output signal of the DA converter 302D is amplified so that the change amount of one pitch in the output signal of the DA converter 302D matches the change amount of one pitch of the input signal of the AD converter 303D.

At this time, as shown in FIGS. 10A and 10B, the amplifier 117
The output signal of the DA converter is amplified so that the width of each range obtained by dividing the output range of D into two equals the width of the input range of the AD converter 303D.

After that, as shown in FIGS. 10B, 10C, and 10D, the level shifter 210B first shifts the lower half of the output range of the DA converter 302D.
The DC level of the output signal of the amplifier 117 is changed so as to match the range from the minimum value to the maximum value of the input signal of the AD converter 303D. Therefore, in this state, by inputting a test digital signal from the external terminal 13 and comparing the value of the digital signal output from the external terminal 14 with the expected value, the lower half of the output range of the DA converter 302D is obtained. The test can be performed on the entire input range of the AD converter 303D.

Next, a predetermined signal is input from the external terminal 12 to operate the test control circuit 4, and the level shifter 210B
, The shift amount of the DC level is changed, and as shown in FIGS.
The DC level of the output signal of the amplifier 117 is changed so that the upper half of the output range of the DA converter 302D amplified by the above step matches the input range of the AD converter 303D. Then, in this state, a digital signal for testing is input from the external terminal 13 and the value of the digital signal output from the external terminal 14 is compared with an expected value, thereby obtaining the upper half of the output range of the DA converter 302D, The test can be performed on the entire input range of the AD converter 303D.

As described above, in the fourth embodiment, the output range of the DA converter 302D is
And the level shifter 210B divides the output range into two in the lower half and the upper half, so that the AD converter D302 having a resolution lower by one bit than the DA converter 302D performs a test without reducing the entire output range of the DA converter 302D. be able to. Here, the resolution of the AD converter is assumed to be one bit lower than the resolution of the DA converter. However, if the resolution of the AD converter is N bits lower than the resolution of the DA converter, the output of the DA converter is determined by the attenuator 9 and the level shifter. Similarly, by dividing the range by 2 N and dividing equally,
The entire output range of the A-converter can be tested without reducing the resolution.

Next, a method of testing a semiconductor device according to a fifth embodiment of the present invention will be described. FIG. 11 is a block diagram showing a semiconductor device according to the fifth embodiment.
(A) to (G) are graphs for explaining the operation of the semiconductor device of FIG. In FIG. 11, FIG.
The same elements as those described above are denoted by the same reference numerals, and a detailed description thereof will be omitted here.

The semiconductor device 540 shown in FIG. 11 is different from the semiconductor device 340 in that the amplifier 117 and the level shifter 210B in the analog test block 530 are different from each other.
Is that the order has been changed. Such a configuration is used when the output range of the DA converter is wide or when the resolution difference between the DA converter and the AD converter is large.
This is effective when the output of the No. 17 is saturated. The amplification factor of the amplifier 117 is such that the change amount of one pitch in the output signal of the DA converter 302D is
Is set so as to correspond to the amount of change of one pitch in the input signal of. The output signal of the DA converter 302D is output to the DA converter 3D by the level shifter 210B.
The DC level is changed so that the signal in each range obtained by bisecting the output range of 02D has a specific DC level. That is, first, the lower half of the output range of the DA converter 302D is amplified by the amplifier 117 so that the DA shift by the level shifter 210B matches the input range of the AD converter 303D.
The DC level of the output signal of converter 302D is shifted ((A) and (B) in FIG. 12).

Next, the output signal of the level shifter 210B is amplified by the amplifier 117 so that the signal in each range of the DA converter 302D changes in accordance with the input range of the AD converter D302. That is, the output signal of the DA converter 302D whose DC level has been shifted by the level shifter 210B is amplified by the amplifier 117 so that the first lower half of the output range of the DA converter 302D matches the input range of the AD converter 303D (FIG. 1
2 (B), (C), (D)).

In this state, a digital signal for testing is input from the external terminal 13 and the value of the digital signal output from the external terminal 14 is compared with the expected value, thereby obtaining the lower half of the output range of the DA converter 302D. , Can be tested over the entire input range of the AD converter 303D.

Next, a predetermined signal is input from the external terminal 12 to operate the test control circuit 4, and the level shifter 21
By changing the shift amount of the DC level of 0B, the DC level of the output signal of the DA converter 302D is shifted so that the upper half of the output range of the DA converter 302D matches the input range of the AD converter 303D after amplification by the amplifier 117. ((A) and (E) of FIG. 12). And DA
DA converter 30 whose DC level is changed by level shifter 210B so that the upper half of the output range of converter 302D matches the input range of AD converter 303D.
The 2D output signal is amplified by the amplifier 117 ((E), (F), (G) in FIG. 12). In this state, a test digital signal is input from the external terminal 13 and the external terminal 1
By comparing the value of the digital signal output from 4 with the expected value, a test can be performed on the upper half of the output range of the DA converter 302D and the entire input range of the AD converter 303D.

As described above, by adopting a configuration in which the order of the amplifier 117 and the level shifter is switched, the same effect as that of the fourth embodiment can be obtained, and the output of the amplifier 117 is saturated. A new effect of preventing such a situation is obtained.

Next, a method of testing a semiconductor device according to a sixth embodiment of the present invention will be described. FIG. 13 is a block diagram showing a semiconductor device according to the sixth embodiment, and FIGS. 14A and 14B are graphs for explaining the operation of an attenuator included in the semiconductor device of FIG. FIGS. 15A to 15F are graphs for explaining the operation of the semiconductor device of FIG. 13, the same elements as those in FIG. 5 are denoted by the same reference numerals, and a detailed description thereof will be omitted here.

The semiconductor device 440 shown in FIG.
Resolution of A converter 402E and AD converter 40
3E have the same resolution, and the DA converter 402E
Is different from the semiconductor device 240 in FIG. 5 in that the amount of change of one pitch in the output signal of the AD converter 403E is larger than half of the amount of change of one pitch in the input signal of the AD converter 403E.

Hereinafter, the operation of the semiconductor device 440 will be described with reference to FIGS. First, as in the case described above, a predetermined signal is input to the external terminal 12 to set the test mode. Thus, the selectors 5 and 6 and the analog switches 7 and 8 are set by the test control circuit 4 in the same manner as in the case of the semiconductor device 240. In the semiconductor device 440, as shown in FIGS. 14A and 14B, the attenuator 9 changes the amount of change of one pitch in the output signal of the DA converter 402E by the A / D converter 4E.
The output signal of the DA converter 402E is attenuated so as to coincide with half of the change amount of one pitch in the input signal of 03E.

That is, the attenuator 9 attenuates the output signal of the D / A converter so that the width of the output range of the D / A converter coincides with half the width of the input range of the A / D converter. Thereafter, the level shifter 210B changes the DC level of the output signal of the attenuated DA converter 402E so that the output range of the attenuated DA converter 402E matches each of the ranges obtained by bisecting the input range of the AD converter 403E. I do.

That is, the level shifter 210 B shifts the DC level of the output signal of the DA converter 402 E attenuated by the attenuator 9, and
Is made to coincide with the lower half of the input range of the AD converter 403E ((B), (C), (D) in FIG. 15). In this state, a test digital signal is input from the external terminal 13 and the value of the digital signal output from the external terminal 14 is compared with an expected value, thereby performing a test on the lower half of the input range of the AD converter 403E. It can be carried out.

Next, a predetermined signal is input from the external terminal 12 to operate the test control circuit 4, and the level shifter 210B
Change the DC level shift amount of. Accordingly, the level shifter 210B changes the output range of the DA converter 402E attenuated by the attenuator 9 to the AD converter 403E.
(B in FIG. 15)
(E), (F)). In this state, a digital signal for a test is input from the external terminal 13 and the value of the digital signal output from the external terminal 14 is compared with an expected value to obtain an AD signal.
Testing can be performed on the upper half of the input range of converter 403E.

As described above, in this embodiment,
The input range of the AD converter 403E is divided into a lower half and an upper half by the attenuator 9 and the level shifter 210B, so that the DA has the same resolution as the AD converter 403E.
The AD converter 403E is provided by the converter 402E.
In the entire input range.
The test can be performed with twice the resolution, and thus with twice the accuracy.

Although the input range of the AD converter is divided into two in this embodiment, N is an integer of 3 or more, and the A / D converter is operated by the attenuator 9 and the level shifter.
By dividing the input range of the converter by N, it is also possible to test the AD converter with N times the resolution of the DA converter.

[0053]

As described above, according to the method of testing a semiconductor device, the output signal of the DA converter is attenuated or amplified in the semiconductor device, and the DC level of the output signal of the DA converter is reduced in the semiconductor device. And supply it to the AD converter. Therefore, even if the output range of the D / A converter is different from the input range of the A / D converter, the test can be performed by matching them, and
Even if the resolution of the D / A converter is different from that of the A / D converter, the output signal of the D / A
The test can be performed at a required resolution by amplifying the signal to the Nth power or attenuating it by a factor of 2N. As a result, in the method of testing a semiconductor device according to the present invention, no expensive test device for analog testing is required.

[0054]

[0055]

[0056]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a semiconductor device according to the present invention.

FIGS. 2A to 2D are graphs for explaining the operation of the semiconductor device of FIG. 1;

FIG. 3 is a block diagram showing a semiconductor device according to a second embodiment.

FIGS. 4A to 4D are graphs for explaining the operation of the semiconductor device of FIG. 3;

FIG. 5 is a block diagram showing a semiconductor device according to a third embodiment.

FIGS. 6A and 6B are graphs showing the operation of an attenuator included in the semiconductor device of FIG. 5;

FIGS. 7A to 7F are graphs for explaining the operation of the semiconductor device of FIG. 5;

FIG. 8 is a block diagram showing a semiconductor device according to a fourth embodiment.

FIGS. 9A and 9B are graphs showing the operation of an attenuator included in the semiconductor device of FIG.

FIGS. 10A to 10F are graphs for explaining the operation of the semiconductor device of FIG. 8;

FIG. 11 is a block diagram showing a semiconductor device according to a fifth embodiment.

FIGS. 12A to 12G are graphs for explaining the operation of the semiconductor device of FIG. 11;

FIG. 13 is a block diagram showing a semiconductor device according to a sixth embodiment.

FIGS. 14A and 14B are graphs for explaining the operation of an attenuator included in the semiconductor device of FIG. 13;

15A to 15F are graphs for explaining the operation of the semiconductor device 40 in FIG.

FIG. 16 is a circuit diagram illustrating an example of an attenuator.

FIG. 17 is a circuit diagram illustrating an example of an amplifier.

FIG. 18 is a circuit diagram illustrating an example of a level shifter.

FIG. 19 is a circuit diagram showing another example of the level shifter.

FIG. 20 is a block diagram illustrating an example of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Digital signal processing circuit, 3A ... AD converter, 4 ... Test control circuit, 5 ... Selector, 7 ... Analog switch, 9 ... Attenuator, 10A ... Level shifter, 13 ... Input terminal, 14 ... ... Output terminals, 30
…… Analog test block, 40 …… Semiconductor device, 4
0 ... semiconductor substrate, 40 ... semiconductor device, 57 ... resistor, 102B ... DA converter, 103B ... AD converter, 117 ... amplifier, 130 ... analog test block, 140 ... semiconductor device, 202C ... DA
Converter, 203C ... AD converter, 210B ...
... Level shifter, 240 ... Semiconductor device, 302D ...
DA converter, 303D ... AD converter, 330
…… Analog test block, 340 …… Semiconductor device,
402E ... DA converter, 403E ... AD converter, 440 ... Semiconductor device, 530 ... Analog test block, 540 ... Semiconductor device.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-199113 (JP, A) JP-A-6-186291 (JP, A) JP-A-57-24121 (JP, A) JP-A-10-1998 268004 (JP, A) JP-A-6-85577 (JP, A) JP-A-63-187428 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28-31 / 3193 H03M 1/10 H03M 1/18

Claims (4)

(57) [Claims] 1. A DA converter and a DA converter constituting a semiconductor device.
And a method for testing an AD converter, wherein a signal is supplied to the DA converter from outside the semiconductor device.
And the output signal of the DA converter is reduced in the semiconductor device.
Attenuates or amplifies the DC level of the output signal of the DA converter.
Changed, attenuated or amplified, and changed the DC level in the body device
Output signal of the DA converter to the AD converter
And supplies the output signal of the AD converter to the outside of the semiconductor device.
And the DA converter outside the semiconductor device.
Data and the output signal of the AD converter
Comparing the DA converter and the AD converter
To determine the quality of the data of test results, the resolution of the DA converter minute of the AD converter
A signal supplied to the AD converter , where N is a natural number , lower than the resolution
Is the width of the input range of the AD converter.
Is divided by 2 to the Nth power so that the DA converter
Attenuates the output signal of the converter, and then changes the range of the signal supplied to the AD converter.
Is the input range of the AD converter divided by 2 N
Before being attenuated to match each equally divided range
Change the DC level of the output signal of the DA converter sequentially
A method for testing a semiconductor device. 2. A DA converter and a DA converter constituting a semiconductor device.
And a method for testing an AD converter, wherein a signal is supplied to the DA converter from outside the semiconductor device.
And the output signal of the DA converter is reduced in the semiconductor device.
Attenuates or amplifies the DC level of the output signal of the DA converter.
Changed, attenuated or amplified, and changed the DC level in the body device
Output signal of the DA converter to the AD converter
And supplies the output signal of the AD converter to the outside of the semiconductor device.
And the DA converter outside the semiconductor device.
Data and the output signal of the AD converter
Comparing the DA converter and the AD converter
To determine the quality of the data of test results, the resolution of the DA converter minute of the AD converter
Higher than the resolution, N is a natural number, and the output range of the DA converter is 2
Is divided by the Nth power of the A
The DA converter is adjusted to match the width of the input range of the inverter.
The output signal of the converter is amplified, and the change range of the output signal of the DA converter is further adjusted.
Each range divided equally by dividing by 2 to the power of N is the AD converter
The amplified DA to match the input range of the data.
A method for testing a semiconductor device , wherein a DC level of an output signal of a converter is sequentially changed . 3. A DA converter and a DA converter constituting a semiconductor device.
And a method for testing an AD converter, wherein a signal is supplied to the DA converter from outside the semiconductor device.
And the output signal of the DA converter is reduced in the semiconductor device.
Attenuates or amplifies the DC level of the output signal of the DA converter.
Changed, attenuated or amplified, and changed the DC level in the body device
Output signal of the DA converter to the AD converter
And supplies the output signal of the AD converter to the outside of the semiconductor device.
And the DA converter outside the semiconductor device.
Data and the output signal of the AD converter
Comparing the DA converter and the AD converter
To determine the quality of the data of test results, the resolution of the DA converter minute of the AD converter
Higher than the resolution, N is a natural number, and the output range of the DA converter is 2
The signal in each range divided equally by the Nth power of
Level of the output signal of the DA converter so that
Level, and then the signals in each of the equally divided ranges are mixed with the AD
The DA is changed so as to match the input range of the inverter.
A method for testing a semiconductor device , comprising: amplifying an output signal of a converter . 4. A DA converter and a DA converter constituting a semiconductor device.
And a method for testing an AD converter, wherein a signal is supplied to the DA converter from outside the semiconductor device.
And the output signal of the DA converter is reduced in the semiconductor device.
Attenuates or amplifies the DC level of the output signal of the DA converter.
Changed, attenuated or amplified, and changed the DC level in the body device
Output signal of the DA converter to the AD converter
And supplies the output signal of the AD converter to the outside of the semiconductor device.
And the DA converter outside the semiconductor device.
Data and the output signal of the AD converter
Comparing the DA converter and the AD converter
The test results of the data converter are judged to be good or bad.
One pitch of the output signal of the DA converter.
The amount of change is one pitch of the input signal of the AD converter.
The output of the DA converter , where N is a natural number greater than or equal to 2
The signal has a width obtained by equally dividing the input range of the AD converter by N
Output signal of the D / A converter so that
Is Decay, thereon, wherein the DA converter output signal obtained by attenuating
The change range divides the input range of the AD converter into N equal parts.
The DA core is attenuated so as to correspond to each range.
A method for testing a semiconductor device , comprising changing a DC level of an output signal of an inverter .