JP3309572B2 - Multi-layer wiring formation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring in a process of manufacturing a semiconductor device having a multilayer wiring structure, wherein a connection hole can be formed in a self-aligned manner in a region where upper and lower wirings overlap.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated and higher in density as seen in VLSI, ULSI, and the like, the proportion of wiring on a device chip tends to increase. In order to prevent an increase in chip area due to this, multilayer wiring has been developed. In a process of manufacturing a semiconductor device having such a multilayer wiring structure, a process of opening a connection hole for electrically connecting an upper wiring pattern and a lower wiring pattern is indispensable.

A process of forming a connection hole facing a lower wiring pattern and forming an upper wiring pattern so as to cross over the lower wiring pattern will be described below with reference to FIGS.
4 will be described. First, an interlayer insulating film 103 is formed by covering a lower wiring pattern 102 on a substrate 101, and a region facing the lower wiring pattern 102 in the interlayer insulating film 103 is subjected to photolithography and etching as shown in FIG. A connection hole 104 is opened.
Next, as shown in FIG. 22, a conductive material layer 105 is formed by a CVD method or a sputtering method so as to cover the interlayer insulating film 103 while filling the connection holes 104. Then, by photolithography and etching, the conductive material layer 105 is
Then, an upper wiring pattern 106 as shown in FIG. 23 is formed.

[0004]

FIG. 24 shows the positional relationship among the lower wiring pattern 102, the connection holes 104, and the upper wiring pattern 106 in a wafer formed as described above, as viewed from above. Show. Connection hole 1
In the region where the layer 04 is formed, the line width of both the lower wiring pattern 102 and the upper wiring pattern 106 is increased as shown in the figure.

[0005] This is because when the pattern of the connection hole 104 is aligned with the position facing the lower wiring pattern 102, the upper wiring pattern 10 is further moved to the processing position of the connection hole 104.
6 is a result in consideration of misalignment generated when aligning No. 6.

More specifically, when a square connection hole 104 having a side length of 0.7 μm is formed on the lower wiring pattern 102, considering that a processing variation of about 0.2 μm occurs in one direction, the lower wiring pattern The line width of 102 needs to be about 1.1 μm. The connection hole 10
4 is formed on the upper wiring pattern 106.
Further, the misalignment of the photomask pattern is about 0.15
In consideration of μm, it is necessary to increase the line width by about 0.35 μm in one direction, and it is necessary to secure a line width of about 1.4 μm.

However, increasing the line widths of the upper and lower wiring patterns in this manner increases the wiring pitch and hinders high integration of the wiring.

Accordingly, the present invention has been proposed in view of the above-mentioned conventional circumstances, and is a method of forming a multilayer wiring which does not need to secure a large line width in the upper and lower wiring patterns, that is, in a region where the upper and lower wiring patterns overlap. It is an object of the present invention to provide a method for forming a multilayer wiring in which connection holes can be formed in a self-aligned manner.

[0009]

A multilayer wiring forming method according to the present invention has been proposed to achieve the above-mentioned object, and a lower wiring pattern formed on a substrate is covered with an interlayer insulating film. An interlayer insulating film forming step, a groove forming step of forming a groove by removing a part of the interlayer insulating film in the thickness direction according to the upper wiring pattern, and a step of forming an area where the lower wiring pattern and the groove overlap. A photoresist coating film forming step of forming a flat photoresist coating film on the interlayer insulating film at a film thickness capable of causing a difference in sensitivity to exposure light in the photoresist coating film between the region and the photoresist film; By performing exposure processing on the resist coating film,
A photolithography in which the solubility in a developing solution of the region where the lower wiring pattern and the groove overlap with each other is relatively increased between the other region and the developing region, and then the developing process is performed to form an opening that follows the connection hole pattern. A resist coating patterning step, an etching step of etching the remaining portion of the interlayer insulating film exposed in the opening to open a connection hole facing the lower wiring pattern, and forming the connection hole and the groove with a conductive material. By embedding, a plug and an upper layer wiring pattern are formed.

That is, in the present invention, a groove is provided in a region where an upper wiring pattern is to be formed, and a region where the lower wiring pattern overlaps the groove (hereinafter referred to as an overlap region) and another region. By causing a difference in sensitivity between the photoresist coatings between the resists, the resist reaction occurring during the exposure causes the solubility in the developer in the overlapping area to be relatively higher than that in the other areas. It is to become.

In order to set the difference in sensitivity between the overlapping region and the other region based on the difference in the thickness of the photoresist coating film, the following method may be used. First, the horizontal axis indicates the thickness of the photoresist coating film.
A swing curve is prepared with the amount of light absorbed by the photoresist coating film as the vertical axis, and the amount of light serving as an exposure threshold is set within the amplitude of the swing curve. Then, in the photoresist coating film, a film thickness region capable of absorbing the light amount exceeding the exposure threshold value and a film thickness region capable of absorbing the light amount exceeding the exposure threshold value appear periodically. The cycle of this swing curve is equal to the wavelength of the standing wave generated in the photoresist coating film, and this wavelength can be expressed by λ / 2n from the wavelength λ of the exposure light and the refractive index n of the photoresist coating film.

The difference in the thickness of the photoresist coating film between the overlapping region and the other region corresponds to the depth of the groove formed in the interlayer insulating film. What is necessary is just to set it so that it may become an odd multiple (however, 3 times or more) of [lambda] / 4n which is a period. However, the depth of the groove portion becomes the thickness of the upper wiring pattern as it is, and if it is too thin, the wiring resistance will increase. As a result, the thickness difference between the photoresist film in the overlapping region and the photoresist film in the other region is such that the light amount exceeding the exposure threshold can be absorbed on the one hand and the light amount exceeding the exposure threshold cannot be absorbed on the other hand. Will occur.

However, when the complex amplitude refractive index (n + ik) is used in consideration of the light absorption of the photoresist coating film itself, a slight correction is required.

The difference in the sensitivity of the photoresist coating is as follows:
Not only the difference in the thickness of the photoresist coating film but also the intensity of the light reflected from the underlayer contributes. For this reason, the thickness of the photoresist coating film in the overlapping region needs to be set in consideration of the contribution of the reflected light from the underlying layer. And
In other regions, if the intensity of the reflected light from the underlayer is almost the same as that of the overlapping region, the sensitivity difference from the overlapping region may be provided by the difference in the thickness of the photoresist coating film as described above. . However, if the intensity of the reflected light from the underlayer is different from that of the overlapping area, a swing curve under this condition is created, and the swing curve in the overlapping area is compared with the common exposure threshold to determine the overlapping area. Means that the thickness of the photoresist film is selected so that a difference in sensitivity occurs. Conversely, in this case, if the thickness of the photoresist coating is properly set in the overlapping region and the other region, the difference in the intensity of the reflected light from the underlayer can be obtained even if the thickness of the photoresist coating is equal. This makes it possible to provide a sensitivity difference.

In the present invention, either a negative photoresist material or a positive photoresist material can be used. In particular, when a positive photoresist material is used, only the photoresist coating in the above-mentioned overlapping region is used. The sensitivity difference is provided so that the light can absorb the light amount exceeding the exposure threshold value. For this reason, the thickness of the photoresist coating film in the overlapping region is set to a thickness at which the amount of absorbed light in the swing curve is maximized. It is preferable to set the film thickness so that the amount of light is minimal. As described above, even if the thickness of the photoresist coating film is the same, it can be set so that the light amount exceeding the exposure threshold value is absorbed only in the overlapping region by the difference in the intensity of the reflected light from the underlayer.
Then, only the overlapping area can be opened by the development.

The groove can be formed in various positional relations with respect to the lower wiring pattern. In particular, as shown in FIG. 1, a groove 5 is formed in a direction intersecting the lower wiring pattern 2 with an interlayer insulating film interposed therebetween, and a photoresist coating film on an intersecting region (hereinafter, referred to as a region A). When an opening is formed following the rectangular connection hole pattern, an opening E having all four sides defined in a self-aligned manner can be formed.

This is because the region A, in which the lower wiring pattern 2 exists but the groove 5 is not formed (hereinafter referred to as region B).
And ), Although the same exposure light is incident on any of the regions where the groove portion 5 is formed but the lower layer wiring pattern 2 does not exist (hereinafter referred to as region C), the region A This is because it is possible that only the photoresist coating absorbs an amount of light exceeding the exposure threshold, and that the photoresist coating on the regions B and C does not absorb the amount of light exceeding the exposure threshold. .

In order to expose the photoresist coating in the area A above the exposure threshold and to expose the photoresist coating in the areas B and C below the exposure threshold,
The amount of exposure light and the amount of light reflected from the underlayer, and the thickness of the photoresist coating film may be optimized. For example, in the areas A and B, the photoresist coating on the area A can absorb an amount of light exceeding the exposure threshold, and the photoresist coating on the area b can be absorbed by a constant amount of exposure light and reflected light. The film thickness of the photoresist coating may be selected so that only the light amount below the exposure threshold can be absorbed. Note that this difference in film thickness may be formed in advance depending on the depth of the groove 5. Further, in the regions A and C, the thickness of the photoresist coating film is the same, but the influence of the reflected light differs depending on the presence or absence of the lower wiring pattern 2. For this reason, in the region A, the reflected light from the lower wiring pattern 2 is incident to exceed the exposure threshold, and in the region C, since the reflected light from the lower wiring pattern 2 is not incident, the exposure threshold is lower. First, the resist sensitivity may be set.

As described above, since the opening E can be selectively formed in the photoresist coating on the region A, the opening region M where the photomask pattern can project onto the photoresist coating is It may be larger than the area A. That is, a margin for the misalignment of the photomask pattern with the wafer can be obtained without increasing the line width of the groove portion following the lower wiring pattern 2 and the upper wiring pattern.

If an anti-reflection film is formed on the surface of the interlayer insulating film after the interlayer insulating film forming process and prior to the groove portion forming process, the effect of strong reflected light from the lower wiring pattern 2 can be prevented. Therefore, patterning of the groove 5 can be performed with good line width stability. After patterning the connection hole in the region A after the groove 5 is formed, the region A and the region B
Since the influence of the reflected light from the underlayer also differs, the thickness of the photoresist coating film is set under each reflected light condition.

By the way, the connection hole of the semiconductor device is generally provided in a region where the upper and lower wirings completely intersect (in most cases, at right angles) as described above. In the case of overlapping, it is applicable although some restrictions arise.

For example, as shown in FIG. 2, a region where the lower wiring pattern 2 and the groove 5 following the upper wiring pattern overlap in a T-shape via an interlayer insulating film (hereinafter, referred to as a region A '). Even when an opening is formed in the upper photoresist coating film following the rectangular connection hole pattern, all four sides of the opening E can be defined in a self-aligned manner. That is, the sensitivity difference between the region A ′, the region B, and the region C can be set in the same manner as described when the groove 5 intersects the lower wiring pattern 2 described above. The difference in sensitivity between the region A ′ and the region (region D) where neither the lower wiring pattern 2 nor the groove portion 5 is present also indicates the difference between the influence of the reflected light from the underlying layer and the thickness of the photoresist coating film. Considering this, it is sufficient to set the region A ′ so that the light amount exceeding the exposure threshold can be absorbed and the region D can absorb only the light amount below the exposure threshold. Therefore, even if a photomask pattern capable of projecting an opening region M larger than the region A 'is used, the opening E can be formed only in the region A'. However, when the area of the region A 'itself is reduced due to misalignment between the lower wiring pattern 2 and the groove 5, the opening E formed in the photoresist coating film thereon is also reduced.

Further, as shown in FIG. 3, a rectangle is formed on the photoresist coating film on a region (hereinafter, referred to as A ″) where the lower wiring pattern 2 and the groove 5 overlap in parallel via the interlayer insulating film. In the case of forming an opening following the connection hole pattern, two of the four sides of the opening E can be defined in a self-aligned manner. That is, the sensitivity difference between the region A ″ and the region D can be set in the same manner as the sensitivity difference between the region A ′ and the region D described above. A ''
Region M on which the photomask pattern can be projected rather than
Is widened, the width of the opening E is defined in a self-aligned manner. On the other hand, in the longitudinal direction of the region A ″, the length l of the opening region M on which the photomask pattern can be projected is
Since the length of the opening E of the photoresist coating film is directly used, the length l of the opening region M on which the photomask pattern can be projected may be adjusted to the size of the desired connection hole pattern.

When a negative photoresist material is used in place of the positive photoresist material, the photoresist coating film in the region where the lower wiring pattern 2 and the groove 5 overlap is opposite to the positive photoresist material. The photoresist coating below the exposure threshold and in other areas needs to be exposed above the exposure threshold. This can also be realized by optimizing the film thickness of the photoresist coating in the overlapping region and the surrounding region, and optimizing the amount of exposure light given to the photoresist coating and the amount of light reflected from the underlayer. .

For example, when a region A shown in FIG. 1 is opened using a negative type photoresist material, a difference in sensitivity is provided between the region A and the photoresist coating of the regions B and C, and only the region A is used. If the setting is made so that the light amount exceeding the exposure threshold cannot be absorbed, all four sides of the rectangular opening E following the connection hole pattern can be defined in a self-aligned manner, and a light-shielded area smaller than the area A can be projected. Photomask patterns can be used. Similarly, in the case where the region A ′ shown in FIG. 2 is opened, a photomask pattern capable of projecting a light-shielding region smaller than the region A ′ can be used.
All four sides of the opening E can be defined in a self-aligned manner. Further, when opening a predetermined range of the region A ″ shown in FIG. 3, the width is smaller in the width direction of the region A ″, and follows the connection hole pattern in the longitudinal direction of the region A ″. A photomask pattern capable of projecting a light-shielded region having a length may be used.

In the present invention, the plug and the upper wiring pattern are formed simultaneously by forming a conductive material after the connection hole is formed. This may be achieved by depositing a conductive material over the entire surface of the wafer while filling the connection holes and the grooves, and then etching back to the upper surface of the grooves, or by selectively growing the conductive material only in the connection holes and the grooves. Good. In particular, when the plug and the upper wiring pattern are formed simultaneously by selective growth, the number of steps spent in the process of forming the multilayer wiring can be reduced.

[0027]

According to the present invention, if a difference in sensitivity is generated in the photoresist coating between the overlapping region where the lower wiring pattern and the groove overlap and the other region, the photoresist coating is formed only in the overlapping region. Since the openings can be formed in a self-aligned manner, it is not necessary to increase the line width of the upper and lower wiring patterns at the expected positions of the connection holes. For this reason, the wiring pitch can be further reduced, and it is possible to increase the wiring layout density.

When a photoresist coating is formed using a positive photoresist material, a sensitivity difference from other regions is set so that only the photoresist coating in the overlapping area absorbs the light amount exceeding the exposure threshold. By doing so, it is possible to form an opening by dissolving and removing only the photoresist coating film in this overlapping region during development. In particular, when the lower wiring pattern and the groove intersect via the interlayer insulating film, the photoresist coating on the region surrounding the intersection can be set so as not to absorb the light amount exceeding the exposure threshold. In addition, all four sides of the rectangular opening following the connection hole can be defined in a self-aligned manner.

When an anti-reflection film is provided on the surface of the interlayer insulating film, strong reflected light from the lower wiring pattern does not enter the photoresist coating on the anti-reflection film. Lithography can be performed stably, and grooves can be formed with good line width stability. further,
For example, as shown in FIG. 1, the overlapping area (area A)
The influence of the reflected light due to the presence or absence of the antireflection film is different between the region A and the region B where the trench 5 is not formed but the region where the trench 5 is not formed. It becomes easy to provide a sensitivity difference in the film.

After the connection hole is formed, the connection hole and the groove are simultaneously filled with a conductive material, so that the plug and the upper wiring pattern can be formed simultaneously.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments to which the present invention is applied will be described below with reference to the drawings. Here, in a manufacturing process of a semiconductor device having a multilayer wiring structure, a step of collectively forming a connection hole (via hole) facing the lower wiring pattern, a plug filling the connection hole, and an upper wiring pattern intersecting the lower wiring pattern. About FIG.
This will be described with reference to FIGS.

First, as shown in the perspective view of FIG. 4, a lower wiring pattern 2 made of an Al--Si material is formed on a substrate 1.
Is formed, and S is applied to cover the lower wiring pattern 2.
After an interlayer insulating film 3 made of an iO ₂ -based material was formed to a thickness of 1.0 μm, an antireflection film 4 made of a SiN-based material was formed to a thickness of 30 nm by a plasma CVD method.

Then, a photoresist coating film (not shown) on the antireflection film 4 is patterned in a direction perpendicular to the lower wiring pattern 2 so as to follow the upper wiring pattern, and using the mask as a mask, Further, a part of the interlayer insulating film 3 in the thickness direction was removed by RIE, and the photoresist coating film was further removed by ashing. As a result, as shown in FIG. 5, a groove 5 perpendicular to the lower wiring pattern was formed at a depth a = 0.605 μm.

FIG. 6 shows the relationship between the lower wiring pattern 2 and the groove 5 from above. A region where the lower wiring pattern 2 and the groove 5 overlap (hereinafter, referred to as a region A).
Are areas where the lower wiring pattern 2 is present but the groove 5 is not provided (hereinafter referred to as area B ′), and areas where the groove 5 is provided but the lower wiring pattern 2 is not present (hereinafter referred to as the area B ′). Area C). That is, in the cross section taken along line XX ′ in FIGS.
As shown in FIG. 7, the region A is sandwiched between the regions B ′,
Similarly, in the section taken along the line YY ′, the region A is interposed between the regions C, as shown in FIG.

Next, a positive photoresist material (trade name: IP-300, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used to fill the groove 5 in the above-mentioned wafer and flatten the wafer surface.
0) was applied. Thereby, XX ′ shown in FIG.
FIG. 9 is a sectional view taken along the line Y-Y ′ shown in FIG.
As shown in FIG. 0, a photoresist coating film 7 for planarizing the wafer surface was formed. At this time, the thickness b of the photoresist coating film 7 on the region where the groove 5 is not provided is set to 1.1.
Since the thickness was set to μm, the thickness c of the photoresist coating film 7 on the region where the groove 5 was provided was increased by the depth a of the groove 5 to 1.705 μm.

Thereafter, exposure was performed on the photoresist coating film 7 on the region A on the wafer in order to form an opening following the connection hole pattern. Specifically, the i-line (3
65 nm) Photomask pattern 6 using a stepper
Through 650-800 msec.

As shown in FIG. 11, a region projected by the photomask pattern 6 on the wafer as an exposure region (hereinafter, referred to as an opening region M) is adjusted in consideration of misalignment with the region A. The area A is wider than the area A. That is,
In FIG. 9, the width e of the opening region M is larger than the width d of the groove 5.
Are larger than the lower wiring pattern 2 in FIG.
The width g of the opening area M is larger than the width f. However, in the exposure using a stepper, the size of the photomask pattern 6 differs from that of the pattern actually projected on the wafer.
For convenience, the opening area M projected on the wafer is shown as an opening pattern of the photomask pattern 6.

Although the opening area M formed by the photomask pattern also covers the area B 'and the area C, as a result of the above-described exposure, only the photoresist coating on the area A is developed. A resist reaction occurred such that it became soluble.

This is because the photoresist film 7 in the region A can absorb the light amount exceeding the exposure threshold value by the above-mentioned exposure, and absorb the light amount exceeding the exposure threshold value in the region B ′ and the region C. It was not possible. In other words, the thickness of the photoresist coating film 7 in the region A is set to easily absorb light under the above-described exposure conditions and the condition of receiving strong reflected light from the lower wiring pattern 2, but the region B ′ In this case, light was hardly absorbed due to the difference in the thickness of the photoresist coating film and the effect of the reflected light, and in the region C, due to the difference in the effect of the reflected light.

For this reason, when the above-mentioned wafer was subjected to a developing treatment, only the photoresist coating film 7 on the region A was dissolved and removed, and an opening 8 was formed as shown in FIG. Although an opening equal to the area of the region A should have been formed after the development, the cross section taken along the line XX ′ in FIG. 13 and the cross section taken along the line YY ′ in FIG.
The opening 8 actually formed has a width h smaller than the width d of the groove 5 in the cross section direction along the line XX ′, and a width i smaller than the width f of the lower wiring pattern 2 in the cross section direction along the line YY ′. Had become. This is because the amount of light absorbed by the photoresist coating film 7 remaining in the groove 5 in the cross-sectional direction along the line XX ′ changes under the influence of light reflected from the wall surface of the groove 5 (the interlayer insulating film 3). It can be inferred that the reason is that the exposure threshold value was exceeded. Similarly, the amount of light absorbed by the photoresist coating film 7 remaining on the lower wiring pattern 2 in the cross-sectional direction of the line YY ′ is also reduced due to the reason that the reflected light from the lower wiring pattern 2 is not sufficiently incident. It can be guessed that it has fallen below the threshold.

Thereafter, RIE is performed using the photoresist coating film 7 in which the opening 8 has been formed as described above as a mask to remove the remaining part of the interlayer insulating film 3, and the connection hole facing the lower wiring pattern 2 is obtained. 9 was formed. FIG. 15 shows a cross section of the wafer along the line XX ′, and FIG. 16 shows a cross section along the line YY ′ of FIG.
In the XX ′ line direction, the width of the connection hole 9 is formed according to the width h of the opening 8 in the photoresist coating film 7, and Y
In the direction of the line Y ′, the connection hole 9 is formed according to the width i of the opening 8.
Thus, the connection hole 9 is opened inside the region A.

FIG. 17 shows a state in which the photoresist coating film 7 has been removed by ashing. Also, the connection hole 9
17 is open between the bottom surface of the groove 5 and the upper surface of the lower wiring pattern 2 in order to make it easier to see the state.
FIG. 18 is a perspective view as viewed from a cross section taken along line X ′.

On the wafer on which the connection holes 9 are formed as described above, an Al-based material is formed by high-temperature sputtering to cover the surface of the antireflection film 4 while filling the connection holes 9 and the grooves 5. Subsequently, the entire surface was etched back to a depth position where the surface of the interlayer insulating film 3 was exposed.
As a result, as shown in FIG. 19, a cross section taken along the line XX ′ is shown in FIG. 19, and a plug 10 made of an Al-based material is An upper wiring pattern 11 made of a base material was formed.

As described above, in the present embodiment, the formation position of the connection hole 9 can be defined in the region A in a self-aligning manner, so that the lower wiring pattern 2 and the upper wiring pattern 11 are formed at the connection hole 9 formation position. There is no need to increase the line width,
High integration of wiring becomes possible.

As described above, the specific example to which the multilayer wiring forming method according to the present invention is applied has been described. However, the present invention is not limited to the above-described embodiment. For example, the antireflection film 4 does not have to be present on the interlayer insulating film 3 at the time of performing the exposure step for forming the opening following the connection hole pattern. In this case, the intensity of the reflected light incident on the photoresist coating film 7 on the region A and the region B ′ is substantially the same. Good. That is, the film thickness difference is set to an odd multiple of a half wavelength (λ / 4n) of the standing wave generated in the photoresist coating film 7, exceeds the exposure threshold in the region A, and exposes in the region B ′. What is necessary is just to make it fall below a threshold value. Even when the lower wiring pattern 2 and the groove 5 overlap in a T-shape or in parallel with the interlayer insulating film 3 interposed therebetween, by optimizing the exposure conditions, the lower wiring pattern can be obtained. Only the photoresist coating 7 on the area where the groove 2 and the groove 5 overlap can be opened.

Further, the material constituting each material layer is not limited to those described above, and a high melting point metal material such as tungsten may be used as the wiring and plug material.
At the time of filling the groove 5, the film may be formed by using an Al reflow method, a blanket tungsten method, or the like. Note that the photoresist coating film may be formed using a negative photoresist material.

[0047]

As is apparent from the above description, when the present invention is applied, the photoresist coating film can be opened in a self-aligned manner in the region where the lower wiring pattern and the groove overlap, so that the connection hole is to be formed. There is no need to increase the line width of the upper and lower wiring patterns at the position. Therefore,
The wiring pitch can be reduced, and high integration of the wiring can be achieved.

In the present invention, since the plug and the upper wiring pattern can be formed at the same time, a multilayer wiring structure with a narrow wiring pitch can be formed without greatly increasing the number of steps as compared with the related art.

When the present invention is applied to the most common connection hole formation in the region where the lower wiring pattern and the upper wiring pattern intersect, all four sides of the rectangular connection hole pattern can be defined in a self-aligned manner, and It is possible to form a simple connection hole.

Further, as long as the lower wiring pattern and the groove following the upper wiring pattern overlap each other, the present invention can be applied irrespective of the relationship between the pattern shapes of the upper and lower wiring and the material of the members constituting the wafer. The degree of freedom in designing a device manufactured by applying the present invention is very large.

[Brief description of the drawings]

FIG. 1 shows a wafer in which a lower wiring pattern and a groove part following the upper wiring pattern intersect via an interlayer insulating film.
It is a schematic diagram which shows the opening area which a photomask pattern projects from an upper surface.

FIG. 2 is a schematic diagram showing, from above, an opening region projected by a photomask pattern on a wafer in which a lower wiring pattern and a groove portion following the upper wiring pattern overlap in a T-shape via an interlayer insulating film. .

FIG. 3 is a schematic diagram showing, from above, an opening area projected by a photomask pattern on a wafer in which a lower wiring pattern and a groove portion following the upper wiring pattern overlap in parallel via an interlayer insulating film.

FIG. 4 is a perspective view schematically showing a part of a wafer in which a lower wiring pattern, an interlayer insulating film, and an antireflection film are formed on a substrate in one embodiment to which the multilayer wiring forming method of the present invention is applied. is there.

FIG. 5 is a perspective view schematically showing a state in which a groove is formed in an interlayer insulating film by patterning in the wafer shown in FIG. 4;

FIG. 6 is a schematic diagram showing a relationship between a lower wiring pattern and a groove in the wafer shown in FIG. 5 from above.

FIG. 7 is a sectional view taken along line XX ′ of the wafer shown in FIG. 5;

8 is a sectional view taken along line YY 'of the wafer shown in FIG.

FIG. 9 is a sectional view taken along line XX ′ showing a state where a photoresist coating film is formed on the wafer shown in FIG. 5;

FIG. 10 is a sectional view taken along the line YY ′ showing a state where a photoresist coating film is formed on the wafer shown in FIG. 5;

FIG. 11 is a schematic diagram showing, from the top, an opening area projected by the photomask pattern onto the wafer shown in FIGS. 9 and 10;

FIG. 12 is a perspective view schematically showing a state in which a developing process is performed on the wafer shown in FIGS. 9 and 10 and an opening is formed.

FIG. 13 is a sectional view taken along line XX ′ of the wafer shown in FIG. 12;

FIG. 14 is a sectional view taken along line YY ′ of the wafer shown in FIG. 12;

FIG. 15 is a cross-sectional view taken along the line XX ′ in a state where etching has been performed on the wafer shown in FIG. 12 and connection holes have been formed.

FIG. 16 is a cross-sectional view taken along the line YY ′ in a state where etching is performed on the wafer illustrated in FIG. 12 and connection holes are formed.

FIG. 17 is a perspective view schematically showing a state in which a photoresist coating film has been removed from the wafer shown in FIGS. 15 and 16;

FIG. 18 is a perspective view schematically showing the wafer shown in FIG. 17 from a cross section taken along line XX ′.

19 shows a state in which a conductive material is formed on the wafer shown in FIG. 17 and etched back to the surface of the interlayer insulating film.
FIG. 4 is a cross-sectional view taken along line -X ′.

20 shows a state in which a conductive material is formed on the wafer shown in FIG. 17 and etched back to the surface of the interlayer insulating film.
FIG. 4 is a sectional view taken along line −Y ′.

FIG. 21 is a schematic cross-sectional view showing a wafer in which connection holes facing the lower wiring pattern are formed by patterning an interlayer insulating film covering a lower wiring pattern on a substrate in an example of a conventional method for forming a multilayer wiring. .

22 is a schematic cross-sectional view showing a state in which a conductive material layer is formed while filling the connection holes in the wafer shown in FIG. 21.

23 is a schematic cross-sectional view showing a state in which a conductive material layer is patterned on the wafer shown in FIG. 22 to form an upper wiring pattern.

24 is a schematic diagram showing a positional relationship among a lower wiring pattern, an upper wiring pattern, and a connection hole in the wafer shown in FIG. 23 from above.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Lower wiring pattern 3 Interlayer insulating film 4 Antireflection film 5 Groove 7 Photoresist coating film 8 Opening 9 Connection hole 10 Plug 11 Upper wiring pattern

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/30 H01L 21/3205-21/3213 H01L 21/768

Claims (6)

(57) [Claims] An interlayer insulating film forming step of covering a lower wiring pattern formed on a substrate with an interlayer insulating film, and removing a part of the interlayer insulating film in a thickness direction according to the upper wiring pattern. A groove forming step of forming a groove, and the interlayer insulating film having a thickness capable of causing a difference in sensitivity to exposure light in a photoresist coating film between a region where the lower wiring pattern overlaps the groove and another region. Forming a photoresist coating film on the photoresist coating film, and performing an exposure process on the photoresist coating film.
Thus, the area where the lower wiring pattern and the groove overlap with each other
The solubility in the developer relative to the other areas
And then, by performing a development process, a photoresist coating patterning step of forming an opening following the connection hole pattern, and etching the remaining portion of the interlayer insulating film exposed in the opening, A multilayer wiring forming method, comprising: an etching step of opening a connection hole facing the lower wiring pattern; and a filling step of forming a plug and an upper wiring pattern by filling the connection hole and the groove with a conductive material. 2. The method according to claim 1, wherein the difference in sensitivity of the photoresist coating film is set in consideration of the contribution of light reflected from the lower wiring pattern. 3. The method according to claim 1, wherein the photoresist coating is formed using a positive photoresist material, and the exposure is performed only in a region where the lower wiring pattern and the groove overlap with each other due to a difference in sensitivity of the photoresist coating. 3. The method according to claim 1, wherein a light amount exceeding a threshold value is absorbed. 4. The semiconductor device according to claim 1, wherein the groove is formed in a direction intersecting the lower wiring pattern with an interlayer insulating film interposed therebetween, and the connection hole is formed in the intersection area. 2. The method for forming a multilayer wiring according to claim 1. 5. The method according to claim 4, wherein the exposing is performed through a photomask pattern capable of projecting an opening larger than the intersection area onto the photoresist coating film.
The method for forming a multilayer wiring according to the above. 6. An anti-reflection film is formed on the surface of the interlayer insulating film after the interlayer insulating film forming step and before the groove forming step. 2. The method for forming a multilayer wiring according to claim 1.