JP3309056B2 - Package for storing high-frequency elements - Google Patents

Package for storing high-frequency elements

Info

Publication number
JP3309056B2
JP3309056B2 JP34951696A JP34951696A JP3309056B2 JP 3309056 B2 JP3309056 B2 JP 3309056B2 JP 34951696 A JP34951696 A JP 34951696A JP 34951696 A JP34951696 A JP 34951696A JP 3309056 B2 JP3309056 B2 JP 3309056B2
Authority
JP
Japan
Prior art keywords
frequency
dielectric substrate
transmission line
main conductor
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP34951696A
Other languages
Japanese (ja)
Other versions
JPH10189824A (en
Inventor
弘志 内村
健 竹之下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP34951696A priority Critical patent/JP3309056B2/en
Publication of JPH10189824A publication Critical patent/JPH10189824A/en
Application granted granted Critical
Publication of JP3309056B2 publication Critical patent/JP3309056B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations

Abstract

PROBLEM TO BE SOLVED: To obtain a package which eliminates the generation of reflection loss, the resonance and the like of an electric signal by a method, wherein a high-frequency transmission line is formed of one pair of main conductor layers which are faced, so as to sandwich a part of a dielectric substrate and of two rows of via-hole groups which connect the main conductor layers electrically and which are arranged and installed at a specific interval in the transmission direction of a signal. SOLUTION: A dielectric substrate which constitutes a package used to house a high-frequency element comprises a mounting part on which the high-frequency element is mounted in the center on its surface, and a high-frequency transmission line 8 by which the high-frequency element is connected to an external electric circuit is formed on the dielectric substrate. The high-frequency transmission line 8 is formed of a pair of main conductor layers 8a, 8b which face each other by sandwiching at least a part of the dielectric substrate, e.g. one layer situated in the uppermost position from amon a plurality of dielectric layers 1a forming the dielectric substrate and of two rows of via-hole groups which connect the pair of main conductor layers 8a, 8b and which are arranged and installed at intervals (c) of 1/2 or lower of a cutoff frequency in the transmission direction of a signal.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、マイクロ波やミリ
波等の高周波信号を伝達するための高周波伝送線路を有
する高周波素子収納用パッケージに関し、特に高周波伝
送線路における高周波信号の伝送特性を改善した高周波
素子収納用パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for storing a high-frequency element having a high-frequency transmission line for transmitting a high-frequency signal such as a microwave or a millimeter wave, and more particularly to an improved transmission characteristic of a high-frequency signal in the high-frequency transmission line. The present invention relates to a high-frequency element storage package.

【0002】[0002]

【従来の技術】近年に至り、マイクロ波やミリ波等の高
周波信号を利用した通信システム、例えばIDカードシ
ステム、無線LAN、車載レーダー等のシステムの開発
が盛んに行われており、これらの機器に使用される高周
波素子収納用パッケージを高性能化することが求められ
ている。
2. Description of the Related Art In recent years, communication systems utilizing high-frequency signals such as microwaves and millimeter waves, for example, systems such as ID card systems, wireless LANs, and vehicle-mounted radars have been actively developed. There is a demand for higher performance of high frequency element storage packages used in the field.

【0003】かかる従来の高周波素子収納用パッケージ
は、例えば図6に示す如く、アルミナセラミックス等か
らなる誘電体基板11上に、下面に凹部12aを設けた
キャップ12を取着させ、前記誘電体基板11の上面と
キャップ12の凹部12aとで形成される空所13(キ
ャビティ)内に高周波半導体集積回路等の高周波素子1
4を収容させるとともに、これを気密封止した構造を有
している。
In such a conventional package for accommodating a high-frequency element, as shown in FIG. 6, for example, a cap 12 having a concave portion 12a provided on a lower surface is attached to a dielectric substrate 11 made of alumina ceramic or the like. A high-frequency device 1 such as a high-frequency semiconductor integrated circuit is provided in a space 13 (cavity) formed by the upper surface of
4 is housed and hermetically sealed.

【0004】また、前記誘電体基板11には、高周波素
子14と外部の電気回路とを接続する高周波伝送線路1
8が設けられており、このような伝送線路18として
は、一般に、マイクロストリップ線路やコプレーナ線路
等が用いられている。尚、高周波伝送線路18として、
マイクロストリップ線路が採用される場合は、その導体
線路を誘電体基板11の上面に、接地導体を誘電体基板
11の内部にそれぞれ配置し、またコプレーナ線路が採
用される場合は、導体線路及び接地導体を誘電体基板1
1の上面に併設させる。
The dielectric substrate 11 has a high-frequency transmission line 1 connecting the high-frequency element 14 and an external electric circuit.
The transmission line 18 is generally a microstrip line, a coplanar line, or the like. In addition, as the high-frequency transmission line 18,
When a microstrip line is adopted, the conductor line is arranged on the upper surface of the dielectric substrate 11, and a ground conductor is arranged inside the dielectric substrate 11. When a coplanar line is adopted, the conductor line and the ground are arranged. Conductor to dielectric substrate 1
1 on the upper surface.

【0005】[0005]

【発明が解決しようとする課題】ところが、この従来の
高周波素子収納用パッケージにおいては、マイクロスト
リップ線路等の伝送線路18が形成されている誘電体基
板11の一部上面にキャップ12の一部が当接されてい
る。このため、伝送線路18はキャップ12の当接部と
それ以外のところで実効誘電率が相違することとなり、
その結果、特性インピーダンスの不整合による信号の反
射損失や共振等が誘発され、高周波信号の伝送特性が悪
くなるという欠点を有していた。
However, in this conventional package for housing a high-frequency element, a part of the cap 12 is formed on the upper surface of a part of the dielectric substrate 11 on which the transmission line 18 such as a microstrip line is formed. Has been abutted. Therefore, the transmission line 18 has a different effective permittivity from the contact portion of the cap 12 to the other portion.
As a result, reflection loss or resonance of a signal due to mismatching of characteristic impedance is induced, and transmission characteristics of a high-frequency signal are deteriorated.

【0006】そこで上述の欠点を解消するために、マイ
クロストリップ線路等の伝送線路18を形成する導体線
路の線幅や導体線路−接地導体間の距離を実効誘電率に
対応させて調整し、伝送線路18の特性インピーダンス
をその全体に亘って一定に保つことが提案されている。
Therefore, in order to solve the above-mentioned drawback, the line width of the conductor line forming the transmission line 18 such as a microstrip line and the distance between the conductor line and the ground conductor are adjusted in accordance with the effective permittivity, and the transmission is performed. It has been proposed to keep the characteristic impedance of the line 18 constant throughout it.

【0007】しかしながら、高周波素子収納用パッケー
ジを組み立てるにあたってキャップ12を誘電体基板1
1上に取着させる際、キャップ12を誘電体基板11上
の所定位置に正確に位置合わせすることは実質的に不可
能であり、数μm程度の僅かな位置ずれが生じただけで
も特性インピーダンスの不整合が発生する。このため、
高周波伝送線路18における信号の反射損失や共振等を
有効に防止することができず、満足のいく伝送特性が得
られていなかった。
However, when assembling the package for accommodating the high-frequency element, the cap 12 is attached to the dielectric substrate 1.
It is practically impossible to accurately align the cap 12 with a predetermined position on the dielectric substrate 11 when the cap 12 is mounted on the substrate 1, and even if a slight misalignment of about several μm occurs, the characteristic impedance is reduced. Inconsistency occurs. For this reason,
The reflection loss and resonance of signals in the high-frequency transmission line 18 cannot be effectively prevented, and satisfactory transmission characteristics have not been obtained.

【0008】[0008]

【課題を解決するための手段】本発明は上記欠点に鑑み
案出されたもので、本発明の高周波素子収納用パッケー
ジは、高周波素子と外部電気回路とを接続する高周波伝
送線路を設けた誘電体基板と、キャップとから成り、内
部に高周波素子を収容するための空所を有する高周波素
子収納用パッケージであって、前記高周波伝送線路は誘
電体基板の少なくとも一部を挟んで対向する一対の主導
体層と、該一対の主導体層間を電気的に接続し、信号の
伝達方向に遮断波長の1/2以下の間隔で配設された二
列のバイアホール群とで形成されていることを特徴とす
るものである。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and a package for storing a high-frequency element according to the present invention is a dielectric package having a high-frequency transmission line for connecting a high-frequency element and an external electric circuit. A high-frequency element housing package comprising a body substrate and a cap, and having a space for housing the high-frequency element therein, wherein the high-frequency transmission line is a pair of opposing members sandwiching at least a part of the dielectric substrate. It is formed of a main conductor layer and two rows of via holes that are electrically connected between the pair of main conductor layers and are arranged in the signal transmission direction at an interval of 1/2 or less of a cutoff wavelength. It is characterized by the following.

【0009】また本発明の高周波素子収納用パッケージ
は、前記高周波伝送線路の一対の主導体層間に、前記バ
イアホール群に電気的に接続される副導体層を前記主導
体層と略平行に配置させたことを特徴とするものであ
る。
In the high-frequency element housing package according to the present invention, a sub-conductor layer electrically connected to the via-hole group is disposed substantially parallel to the main conductor layer between the pair of main conductor layers of the high-frequency transmission line. It is characterized by having made it.

【0010】[0010]

【発明の実施の形態】以下、本発明を添付図面に基づい
て詳細に説明する。図1は本発明の高周波パッケージの
一形態を示し、1は誘電体基板、2はキャップであり、
誘電体基板1とキャップ2とで高周波素子4を収容する
空所3(キャビティ)が形成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of the high-frequency package of the present invention, wherein 1 is a dielectric substrate, 2 is a cap,
A cavity 3 (cavity) for accommodating the high-frequency element 4 is formed by the dielectric substrate 1 and the cap 2.

【0011】この高周波素子収納用パッケージを構成す
る誘電体基板1は、その上面中央に高周波素子4が搭載
される搭載部を有しており、該搭載部には高周波素子4
がガラス,樹脂,ロウ材等の接着剤(図示せず)を介し
て接着固定される。
The dielectric substrate 1 constituting this high-frequency element storage package has a mounting portion on which the high-frequency element 4 is mounted at the center of the upper surface thereof.
Are bonded and fixed via an adhesive (not shown) such as glass, resin, or brazing material.

【0012】前記誘電体基板1は例えばアルミナセラミ
ックスやガラスセラミックス,窒化アルミニウムセラミ
ックス等の誘電体材料から成り、例えばアルミナセラミ
ックスから成る場合、アルミナ、シリカ、マグネシア等
のセラミックス原料粉末に適当な有機溶剤、溶媒を添加
混合して泥漿状に成すとともにこれを従来周知のドクタ
ーブレード法やカレンダーロール法等を採用してシート
状となすことによって複数枚のセラミックグリーンシー
トを得、しかる後、前記セラミックグリーンシートの各
々に適当な打ち抜き加工を施すとともにこれらを上下に
積層し、高温(約1600℃)で焼成することによって
製作される。
The dielectric substrate 1 is made of a dielectric material such as alumina ceramics, glass ceramics, aluminum nitride ceramics or the like. For example, when the dielectric substrate 1 is made of alumina ceramics, an organic solvent suitable for a ceramic raw material powder such as alumina, silica or magnesia is used. A plurality of ceramic green sheets are obtained by forming a slurry by adding and mixing a solvent and forming a slurry by employing a conventionally known doctor blade method, calender roll method, or the like, and thereafter, the ceramic green sheet is formed. Are subjected to an appropriate punching process, stacked one above the other, and fired at a high temperature (about 1600 ° C.).

【0013】また前記誘電体基板1には高周波素子4と
図示しない外部電気回路とを接続するための高周波伝送
線路8が設けられている。前記高周波伝送線路8は、図
2に示すように、誘電体基板1の少なくとも一部、例え
ば誘電体基板1を形成する複数の誘電体層1aのうち最
も上に位置する1層を挟んで対向する一対の主導体層8
a,8bと、該一対の主導体層8a,8b間を電気的に
接続し、信号の伝達方向に遮断波長(λc)の1/2以
下の間隔cで配設された二列のバイアホール群(バイア
ホール:8c)とで形成されている。
The dielectric substrate 1 is provided with a high-frequency transmission line 8 for connecting the high-frequency element 4 to an external electric circuit (not shown). As shown in FIG. 2, the high-frequency transmission line 8 is opposed to at least a part of the dielectric substrate 1, for example, a topmost one of a plurality of dielectric layers 1 a forming the dielectric substrate 1. Pair of main conductor layers 8
a, 8b and the pair of main conductor layers 8a, 8b are electrically connected to each other, and two rows of via holes are arranged in the signal transmission direction at an interval c equal to or less than の of the cutoff wavelength (λc). (Via holes: 8c).

【0014】このような高周波伝送線路8は、一対の主
導体層8a,8b間に形成されている2つのバイアホー
ル群がそれぞれ信号の伝達方向に遮断波長(λc)の1
/2以下の間隔cで配列されており、信号の伝達方向に
対して垂直な方向に電気的な壁を形成していることから
電磁波を線路形成方向にのみ良好に伝播させることがで
き、一対の主導体層8a,8bと二列のバイアホール群
によって囲まれる領域をa×bの擬似的な導波管として
機能させることができる。これにより、高周波伝送線路
8がマイクロ波やミリ波等の高周波信号を伝達するのに
適したものとなる。尚、前記高周波伝送線路8は、バイ
アホール8cの配列ピッチcが遮断波長(λc)の1/
2よりも大きいと、高周波伝送線路8に電磁波を供給し
た際、隣接するバイアホール8c間より電磁波が漏れ、
高周波伝送線路8に沿って良好に伝播しない。従って、
バイアホール8cの配列ピッチcは遮断波長(λc)の
1/2以下に設定しておく必要がある。
In such a high-frequency transmission line 8, the two via-hole groups formed between the pair of main conductor layers 8a and 8b each have a cutoff wavelength (λc) of 1 in the signal transmission direction.
/ 2 are arranged at an interval c of not more than / 2, and since an electric wall is formed in a direction perpendicular to the signal transmission direction, the electromagnetic wave can be favorably propagated only in the line forming direction. The region surrounded by the main conductor layers 8a and 8b and the two rows of via holes can function as an axb pseudo waveguide. This makes the high-frequency transmission line 8 suitable for transmitting high-frequency signals such as microwaves and millimeter waves. In the high-frequency transmission line 8, the arrangement pitch c of the via holes 8c is 1/1 / the cutoff wavelength (λc).
If it is larger than 2, when electromagnetic waves are supplied to the high-frequency transmission line 8, the electromagnetic waves leak from between the adjacent via holes 8c,
It does not propagate well along the high-frequency transmission line 8. Therefore,
The arrangement pitch c of the via holes 8c needs to be set to 以下 or less of the cutoff wavelength (λc).

【0015】また前記高周波伝送線路8を構成する主導
体層8a,8b及びバイアホール8cは、誘電体基板1
がアルミナセラミックスから成る場合、タングステンや
モリブデン等の高融点金属材料により形成され、これら
は誘電体基板1を製作する際に同時に形成される。即
ち、誘電体基板1となるセラミックグリーンシートの表
面に、タングステン,モリブデン等の金属粉末を含む導
電ペーストを従来周知の厚膜印刷法等を採用することに
よって5〜25μmの厚みをもって印刷・塗布するとと
もに、セラミックグリーンシートに予め開けておいた穴
に導電ペーストをを埋め込み、セラミックグリーンシー
トと同時に焼成することによって誘電体基板1の上面及
び内部に所定パターンに形成される。このとき、一対の
主導体層8a,8b間の間隔aに対する制限を特に設け
る必要はないが、TE10のシングルモードで用いる場
合には、一対の主導体層8a,8b間の間隔をa、二列
のバイアホール群間の間隔をbとしたとき、a=b/2
又はa=2bとなるように設定しておくことが好まし
く、この場合、各バイアホール8cの大きさはφ50〜
300μm程度になしておくことが好ましい。
The main conductor layers 8a and 8b and the via holes 8c constituting the high-frequency transmission line 8 are formed on the dielectric substrate 1.
Is formed of a high melting point metal material such as tungsten or molybdenum, and these are formed simultaneously when the dielectric substrate 1 is manufactured. That is, a conductive paste containing a metal powder such as tungsten or molybdenum is printed and applied on the surface of the ceramic green sheet serving as the dielectric substrate 1 with a thickness of 5 to 25 μm by employing a conventionally known thick film printing method or the like. At the same time, a conductive paste is buried in a hole previously opened in the ceramic green sheet, and is baked simultaneously with the ceramic green sheet to form a predetermined pattern on the upper surface and inside of the dielectric substrate 1. At this time, it is not necessary to particularly limit the distance a between the pair of main conductor layers 8a and 8b. However, when the TE 10 is used in the single mode, the distance between the pair of main conductor layers 8a and 8b is a, When the interval between via-hole groups in a row is b, a = b / 2
Alternatively, it is preferable to set a so that a = 2b. In this case, the size of each via hole 8c is φ50 to
It is preferable to set the thickness to about 300 μm.

【0016】そして、上述のような高周波伝送線路8は
その一端が空所3内に配置させた高周波素子4の近傍ま
で、他端がキャップ2の取着領域の外側まで導出され、
各導出部には端子としての接続プローブ5が取着されて
いる。
The high-frequency transmission line 8 as described above has one end led out to the vicinity of the high-frequency element 4 disposed in the cavity 3 and the other end led out to the outside of the mounting region of the cap 2.
A connection probe 5 as a terminal is attached to each outlet.

【0017】前記接続プローブ5は高周波伝送線路8を
ボンディングワイヤ6を介して高周波素子4や外部電気
回路に電気的に接続する端子としての作用を為し、特
に、本形態では高周波伝送線路8の上面が磁界と平行な
H面に、側面が電界と平行なE面になっているので、接
続プローブ5の高周波伝送線路8内への導入長さを信号
波長の1/4程度となるように設定しておけば接続プロ
ーブ5を1/4波長のモノポールアンテナとして機能さ
せ、高周波伝送線路8を高周波素子4や外部電気回路に
対して良好に接続させることができる。尚、このような
疑似導波管型の高周波伝送線路8はスロットを用いてマ
イクロストリップ線路やコプレーナ線路など他の伝送線
路と接続させても良い。
The connection probe 5 functions as a terminal for electrically connecting the high-frequency transmission line 8 to the high-frequency element 4 or an external electric circuit via the bonding wire 6. Since the upper surface is an H plane parallel to the magnetic field and the side surface is an E plane parallel to the electric field, the length of the connection probe 5 introduced into the high-frequency transmission line 8 is set to be about 1 / of the signal wavelength. If set, the connection probe 5 can function as a quarter-wave monopole antenna, and the high-frequency transmission line 8 can be connected well to the high-frequency element 4 and an external electric circuit. The pseudo waveguide type high frequency transmission line 8 may be connected to another transmission line such as a microstrip line or a coplanar line using a slot.

【0018】更に、前記誘電体基板1の上部には、下面
に凹部2aを有するキャップ2がガラス,樹脂,ロウ材
等の接着剤(図示せず)を介して取着され、これによっ
て誘電体基板1とキャップ2との間に高周波素子4を収
容するための空所3を形成し、高周波素子4を気密に収
容している。
Further, a cap 2 having a concave portion 2a on the lower surface is attached to the upper portion of the dielectric substrate 1 via an adhesive (not shown) such as glass, resin, brazing material or the like. A space 3 for accommodating the high-frequency element 4 is formed between the substrate 1 and the cap 2, and the high-frequency element 4 is hermetically accommodated.

【0019】前記キャップ2は前述した誘電体基板1と
同様の誘電体材料、又は放熱性が良好な金属材料等によ
って形成されており、凹部2aの周囲を高周波伝送線路
8が形成されている誘電体基板1の上面に当接させると
ともに、該当接部をガラス,樹脂,ロウ材等の接着剤
(図示せず)を介して誘電体基板1の上面に接着固定す
ることにより誘電体基板1の上部に取着される。
The cap 2 is made of the same dielectric material as the above-described dielectric substrate 1 or a metal material having good heat dissipation. The dielectric around which the high-frequency transmission line 8 is formed around the recess 2a is formed. The dielectric substrate 1 is brought into contact with the upper surface of the dielectric substrate 1 by bonding the corresponding contact portion to the upper surface of the dielectric substrate 1 via an adhesive (not shown) such as glass, resin, or brazing material. Mounted on top.

【0020】尚、前記キャップ2は、例えばアルミナセ
ラミックスから成る場合、誘電体基板1と同様に、所定
形状に打ち抜き加工したセラミックグリーンシートを積
層し、これを高温で焼成することによって下面に凹部2
aを有した所定の形状に形成される。
When the cap 2 is made of, for example, alumina ceramics, similarly to the dielectric substrate 1, ceramic green sheets punched into a predetermined shape are laminated and fired at a high temperature to form the recesses 2 on the lower surface.
It is formed in a predetermined shape having a.

【0021】以上のような高周波素子収納用パッケージ
においては、誘電体基体1に設けられる高周波伝送線路
8が導波管と同等の機能を有しており、その周囲に配置
される部材の誘電率や厚さ等が部分的に相違していても
特性インピーダンスが変化することはない。このため、
高周波伝送線路18にキャップ2の一部が当接されて
も、該当接部の近傍等で特性インピーダンスの不整合が
発生することはなく、電気信号の反射損失や共振等の発
生を皆無として高周波信号を極めて良好に伝送させるこ
とができる。
In the above-described package for housing a high-frequency element, the high-frequency transmission line 8 provided on the dielectric substrate 1 has a function equivalent to that of the waveguide, and the dielectric constant of a member disposed therearound. The characteristic impedance does not change even if the thickness and the like are partially different. For this reason,
Even if a part of the cap 2 abuts on the high-frequency transmission line 18, no mismatch of the characteristic impedance occurs near the corresponding contact portion or the like. Signals can be transmitted very well.

【0022】しかも、この場合、高周波素子収納用パッ
ケージを組み立てるにあたり、従来例のようにキャップ
2を誘電体基板1に対して高精度に位置合わせする必要
はなく、その組み立て作業が極めて簡単になる。
Moreover, in this case, in assembling the package for housing the high-frequency element, it is not necessary to position the cap 2 with respect to the dielectric substrate 1 with high accuracy as in the conventional example, and the assembling work becomes extremely simple. .

【0023】尚、本発明は上述した形態に限定されるも
のではなく、本発明の要旨を逸脱しない範囲において種
々の変更、改良等が可能であり、例えば、図3に示すよ
うに、誘電体基板1内に形成される高周波伝送線路8を
誘電体基板1の下部領域に形成するようにしても良く、
この場合、高周波伝送線路8の一対の主導体層8a,8
bはいずれもキャップ2と接触しなくなるため、より良
好な気密封止が可能である。
The present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention. For example, as shown in FIG. The high-frequency transmission line 8 formed in the substrate 1 may be formed in a lower region of the dielectric substrate 1,
In this case, the pair of main conductor layers 8a and 8
Since b does not come into contact with the cap 2, better hermetic sealing is possible.

【0024】また、図4に示すように、外部接続用の端
子を誘電体基板1の下面に設け、これを外部の配線基板
Pに半田ボール9を介して接続させたり、或いは、図5
に示すように、高周波伝送線路8の一対の主導体層8
a,8b間に、各バイアホール8cと接続されるように
して、主導体層8a,8bと略平行な副導体層8dを形
成しても良く、この場合、高周波伝送線路8の側壁はバ
イアホール8cと副導体層8dによって細かな格子状と
なるため、電磁波の遮断効果をより有効に高めることが
できる。
As shown in FIG. 4, a terminal for external connection is provided on the lower surface of the dielectric substrate 1 and is connected to an external wiring substrate P via a solder ball 9, or as shown in FIG.
As shown in the figure, a pair of main conductor layers 8 of the high-frequency transmission line 8 are provided.
A sub-conductor layer 8d substantially parallel to the main conductor layers 8a and 8b may be formed between the sub-conductor layers 8a and 8b so as to be connected to the via holes 8c. Since the holes 8c and the sub-conductor layers 8d form a fine lattice, the effect of blocking electromagnetic waves can be more effectively enhanced.

【0025】[0025]

【発明の効果】本発明の高周波素子収納用パッケージに
よれば、誘電体基体に設けられる高周波伝送線路が導波
管と同等の機能を有しており、その周囲に配置される部
材の誘電率や厚さ等が部分的に相違していても特性イン
ピーダンスは一定に保たれる。このため、高周波伝送線
路にキャップの一部が当接されても、該当接部の近傍等
で特性インピーダンスの不整合が発生することはなく、
電気信号の反射損失や共振等の発生を皆無として高周波
信号を極めて良好に伝送させることができる。
According to the package for housing a high-frequency element of the present invention, the high-frequency transmission line provided on the dielectric substrate has a function equivalent to that of the waveguide, and the dielectric constant of the member disposed therearound. The characteristic impedance is kept constant even if the thickness and the like are partially different. For this reason, even if a part of the cap is in contact with the high-frequency transmission line, there is no occurrence of characteristic impedance mismatch in the vicinity of the corresponding contact portion, etc.
A high-frequency signal can be transmitted very satisfactorily without any occurrence of reflection loss or resonance of the electric signal.

【0026】しかも、この高周波素子収納用パッケージ
を組み立てるにあたり、従来例のようにキャップを誘電
体基板に対して高精度に位置合わせする必要はなく、そ
の組み立て作業が極めて簡単になる。
Moreover, in assembling the high-frequency element housing package, it is not necessary to align the cap with the dielectric substrate with high accuracy as in the conventional example, and the assembling work becomes extremely simple.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の高周波素子収納用パッケージの一形態
を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a high-frequency element housing package of the present invention.

【図2】図1の高周波素子収納用パッケージに用いられ
る高周波伝送線路の斜視図である。
FIG. 2 is a perspective view of a high-frequency transmission line used in the high-frequency element housing package of FIG. 1;

【図3】本発明の高周波素子収納用パッケージの変形例
を示す断面図である。
FIG. 3 is a cross-sectional view showing a modification of the high frequency element housing package of the present invention.

【図4】本発明の高周波素子収納用パッケージの変形例
を示す断面図である。
FIG. 4 is a cross-sectional view showing a modification of the high-frequency element housing package of the present invention.

【図5】本発明の他の形態の高周波素子収納用パッケー
ジに用いられる高周波伝送線路の斜視図である。
FIG. 5 is a perspective view of a high-frequency transmission line used in a high-frequency element housing package according to another embodiment of the present invention.

【図6】従来の高周波素子収納用パッケージを示す断面
図である。
FIG. 6 is a cross-sectional view showing a conventional package for storing a high-frequency element.

【符号の説明】[Explanation of symbols]

1・・・誘電体基板 2・・・キャップ 3・・・空所 4・・・高周波素子 8・・・高周波伝送線路 DESCRIPTION OF SYMBOLS 1 ... Dielectric substrate 2 ... Cap 3 ... Empty space 4 ... High frequency element 8 ... High frequency transmission line

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】高周波素子と外部電気回路とを接続する高
周波伝送線路を設けた誘電体基板と、キャップとから成
り、内部に高周波素子を収容するための空所を有する高
周波素子収納用パッケージであって、 前記高周波伝送線路は誘電体基板の少なくとも一部を挟
んで対向する一対の主導体層と、該一対の主導体層間を
電気的に接続し、信号の伝達方向に遮断波長の1/2以
下の間隔で配設された二列のバイアホール群とで形成さ
れていることを特徴とする高周波素子収納用パッケー
ジ。
A high-frequency element storage package comprising a dielectric substrate provided with a high-frequency transmission line for connecting a high-frequency element and an external electric circuit, and a cap, and having a space for accommodating the high-frequency element therein. The high-frequency transmission line electrically connects the pair of main conductor layers opposed to each other with at least a part of the dielectric substrate therebetween, and connects the pair of main conductor layers with each other in the signal transmission direction by 1 / の of the cutoff wavelength. A high frequency element storage package, comprising: two rows of via holes arranged at an interval of 2 or less.
【請求項2】前記高周波伝送線路の一対の主導体層間
に、前記バイアホール群に電気的に接続される副導体層
を前記主導体層と略平行に配置させたことを特徴とする
請求項1に記載の高周波素子収納用パッケージ。
2. The semiconductor device according to claim 1, wherein a sub-conductor layer electrically connected to said via-hole group is disposed substantially parallel to said main conductor layer between said pair of main conductor layers of said high-frequency transmission line. 2. The package for storing a high-frequency element according to claim 1.
JP34951696A 1996-12-27 1996-12-27 Package for storing high-frequency elements Expired - Lifetime JP3309056B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34951696A JP3309056B2 (en) 1996-12-27 1996-12-27 Package for storing high-frequency elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34951696A JP3309056B2 (en) 1996-12-27 1996-12-27 Package for storing high-frequency elements

Publications (2)

Publication Number Publication Date
JPH10189824A JPH10189824A (en) 1998-07-21
JP3309056B2 true JP3309056B2 (en) 2002-07-29

Family

ID=18404271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34951696A Expired - Lifetime JP3309056B2 (en) 1996-12-27 1996-12-27 Package for storing high-frequency elements

Country Status (1)

Country Link
JP (1) JP3309056B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11035882B2 (en) 2018-10-26 2021-06-15 Samsung Electronics Co., Ltd. Signal transfer structure for test equipment and automatic test apparatus for testing semiconductor devices using the same

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JP2001024100A (en) * 1999-07-12 2001-01-26 Mitsubishi Electric Corp Microwave package
JP5289214B2 (en) * 2008-07-31 2013-09-11 京セラ株式会社 High frequency module
JP5241591B2 (en) * 2009-04-24 2013-07-17 京セラ株式会社 Connection structure between high-frequency circuit and high-frequency line
JP5414364B2 (en) * 2009-05-28 2014-02-12 京セラ株式会社 High frequency substrate and high frequency module
CN109429423A (en) * 2017-08-30 2019-03-05 中兴通讯股份有限公司 Transmitting device and its method for terminal device WiFi11ad circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11035882B2 (en) 2018-10-26 2021-06-15 Samsung Electronics Co., Ltd. Signal transfer structure for test equipment and automatic test apparatus for testing semiconductor devices using the same

Also Published As

Publication number Publication date
JPH10189824A (en) 1998-07-21

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