JP3308457B2 - Electric signal supply circuit and semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electric signal supply circuit and a semiconductor memory device, and more particularly to a measure for adjusting a signal delay time.

[0002]

2. Description of the Related Art In recent years, with the increase in the scale of semiconductor devices, adjustment of the delay time of signal transmission to circuit cells has become an issue. In particular, in a large-scale semiconductor memory device, there is a problem that a malfunction occurs due to a delay time of signal transmission depending on an arrangement position of a memory cell, and a high-speed operation becomes difficult to avoid the malfunction. For example, US Pat.
In a nonvolatile memory in which a capacitor of a memory cell is made of a ferroelectric material, a voltage is applied to a cell plate electrode of the capacitor of the memory cell, as shown in US Pat. The difference in the amount of charge from the memory cell (dummy memory cell) is amplified by an amplifier and used as output data. At this time, if a delay time difference occurs in signal transmission to the plate electrodes of the main body memory cell and the reference memory cell, the difference between the charge amounts of the two is not output correctly, which may cause a malfunction.

FIG. 15 is a block circuit diagram and FIG. 16 is a diagram showing the relationship between time and signal level voltage in a conventional example in which the difference in signal transmission delay time from an electric signal generation source to each circuit cell is a problem. This will be described with reference to FIG.

[0004] In FIG. 15, the relationship between reference numerals and member names is as follows. SD is a signal source, C1 to C
5 is a circuit cell, R11 to R14 are resistors, N11 to N1
Reference numeral 5 indicates a node. In the circuit shown in FIG.
The node N11 is connected to the signal generation source SD, and four nodes N12 to N15 are sequentially connected to the node N11 in series via resistors R11 to R14. The circuit cells C1 to C5 are connected to the nodes N11 to N15, respectively. That is, the signal source S
The signal output from D passes through the resistor R11 to the circuit cell C2 without passing through the resistor to the circuit cell C1.
The circuit cell C3 is connected via resistors R11 and R12, the circuit cell C4 is connected via resistors R11, R12 and R13,
The circuit cell C5 includes resistors R11, R12, R13 and R
14, respectively.

[0005]

However, the signal supply circuit having the above configuration has the following problems.

In the electric signal supply circuit having such a configuration,
When the signal from the signal generation source SD is changed from the logic voltage “L” to the logic voltage “H”, the signal level voltage at the node N11 is changed to the node N15 as shown by a signal level voltage curve 21 in FIG.
Is as shown in a signal level voltage curve 22. That is, the time required for the node N15 to reach the level "1" is longer than the time required for the node N11 to reach the level "1". This is because each of the circuit cells C1 to C
5 including the parasitic capacitance and resistors R11 to R1
4, the signal delay time at the node N15 is larger than the signal delay time at the node N11. Such a delay time difference between each circuit cell causes a problem in circuit operation.

A signal generation source SD shown in FIG. 15 is a voltage supply circuit to a plate electrode of a memory cell, and each circuit cell C1 to C1
C5 is a main memory cell and a reference memory cell, and a non-volatile memory using a ferroelectric as a memory cell capacitor is taken as an example. As described above, when a voltage is supplied from the voltage supply circuit, the plate electrode of the main memory cell and the plate electrode of the reference memory cell have different times to reach a predetermined level due to a difference in signal transmission delay time. The potential read from each memory cell shifts from the potential read when there is no difference in the delay time of the signal to the plate electrode of each memory cell. In order to prevent such erroneous detection, it is necessary to start the sense amplifier after a sufficient time elapses until the read potential is determined, which makes high-speed operation difficult. In addition, a malfunction may occur depending on the timing of starting the sense amplifier.

The present invention has been made in view of the above, and an object of the present invention is to reduce the delay time difference of a signal to each circuit cell as much as possible when a large number of circuit cells are arranged. Therefore, an object of the present invention is to provide an electric signal supply circuit and a semiconductor memory device capable of performing a high-speed and stable operation.

[0009]

According to a first aspect of the present invention, a first electric signal supply circuit includes a plurality of circuit cells, an electric signal generation source for generating a signal to be supplied to each of the circuit cells, and an electric signal generation circuit. A wiring that is derived from a source and is connected to each of the circuit cells at a leading end, wherein the wiring is a first hierarchy derived from the electric signal generation source and a branch that is a leading end of the first hierarchy. At a point, a second layer including a center and branch lines branched on both sides thereof, and one circuit cell is connected to a branch line extending to the center of the second layer, A plurality of circuit cells are connected in parallel to each of the branch lines extending to both sides of the branch lines.
The wiring width of the first layer is the same as that of the second layer.
The resistance of the wiring from the branch point in the second hierarchy to each circuit cell is smaller than the wiring width in the first hierarchy from the electric signal generation source to the branch point in the first hierarchy. , And the resistance values in the path from the electric signal generation source to each circuit cell are set substantially equal. Thereby, the delay times of the signals supplied from the signal generation source to the first and second circuit cells become substantially equal. Therefore, high-speed operation is possible, and a stable circuit operation with less malfunction is obtained.

As a result, the delay times of the signals supplied from the signal generation source to the first and second circuit cells become substantially equal. Therefore, high-speed operation is possible, and a stable circuit operation with less malfunction is obtained.

[0011]

A second electric signal supply circuit according to the present invention includes a plurality of circuit cells, an electric signal generation source for generating an electric signal to be supplied to each of the circuit cells, and a circuit derived from the electric signal generation source. Later, a pyramid in at least three levels
And a wiring connected at a tip end to each of the circuit cells. The wiring is branched from one branch point in three directions in a final hierarchy connected to the circuit cell, The resistance value in the wiring in the first layer from the electric signal generation source to the first branch point in the two layers is changed from the second layer branched from the first layer to the last layer.
From the first branch point in the wiring including
It is larger than the resistance value of the leading part .

Thus, in the electric signal supply circuit,
Since an electric signal is transmitted from the electric signal source to a plurality of circuit cells through a pyramid-shaped wiring, a difference in impedance between the electric signal source and each circuit cell is reduced, and the electric signal is generated from the electric signal source. The delay time difference of the signal to each circuit cell is reduced. Therefore, high-speed operation is possible, and a stable circuit operation with less malfunction is obtained. Further, since the resistance value in the first hierarchy that gives a common resistance to each circuit cell in the path of the signal transmitted to each circuit cell is large, the resistance value in the second hierarchy is reduced by the delay time in each circuit cell. The effect is reduced. Therefore, the delay time difference between each circuit cell is further reduced.

[0014] Each tip of the last hierarchy leading up Symbol circuit cell is connected to the respective circuit cells through each resistor
In particular, the resistance of the resistor can be adjusted to the first value.
From the above electrical signal source to the first branch point in the hierarchy
To be larger than the resistance value in wiring leading to each resistor from the first branch point from the resistance value and the second hierarchy in the wiring that leads in the final hierarchy <br/>, the tip of the second hierarchy Since a resistor is interposed between the unit and each circuit cell,
The influence of the capacitance including the parasitic capacitance of each circuit cell is less likely to appear at the node at the tip of the second layer, and the delay time difference between the circuit cells is reduced.

A third electric signal supply circuit according to the present invention includes a plurality of circuit cells, an electric signal generating source for generating an electric signal to be supplied to the circuit cells, and a third electric signal generating circuit connected to the electric signal generating source. A first-layer wiring and a second-layer wiring connected to each of the circuit cells, wherein the first-layer wiring and the second-layer wiring have at least first and second contacts; , The plurality of circuit cells includes at least first, second, and third circuit cells, and the first layer wiring has one end. , The first and second resistors are arranged in this order, and the first layer wiring is partitioned into the first to third nodes in order from the one end by the resistors.
On the second layer wiring, first to fourth resistors are arranged in order from one end corresponding to the one end of the first layer wiring. The wiring of the second layer is divided into first to fifth nodes in order from the one end, and the first, third, and fifth nodes are connected to the first, second, and third nodes, respectively. And the first contact is formed between a first node in the first layer wiring and a second node in the second layer wiring. , The second contact is connected to the first contact.
The third node in the wiring of the layer and the fourth node in the wiring of the second layer
And the electrical signal generation source is connected to a second node in the first-layer wiring, and the second signal is connected to the second node in the second-layer wiring. The resistance value of the resistor is larger than the resistance value of the first resistor.

Thus, a difference in delay time between a circuit cell to which an electric signal is supplied via two paths and a circuit cell to which an electric signal is supplied from one path can be reduced as much as possible. .

The resistance of the first resistor in the wiring of the first layer is substantially equal to the resistance of the second resistor, and the resistance of the second resistor is equal to the resistance of the first resistor. √ of the resistance value of the resistor
By configuring so as to be twice, it is possible to substantially eliminate a difference in delay time between a circuit cell to which an electric signal is supplied via two paths and a circuit cell to which an electric signal is supplied from one path. it can.

A fourth electric signal supply circuit according to the present invention includes a plurality of circuit cells, an electric signal generating source for generating an electric signal to be supplied to the circuit cells, and a fourth electric signal generating circuit connected to the electric signal generating source. A first layer wiring and a second layer wiring connected to each of the circuit cells are provided, and the first layer wiring and the second layer wiring are connected by a plurality of contacts. In the electric signal generating circuit, the plurality of circuit cells include at least first, second, and third circuit cells, and the first layer wiring includes first to fourth resistor elements sequentially from one end. Are arranged, and the first-layer wiring is partitioned into the first to fifth nodes in order from the one end by the resistors, and the first-layer wiring is provided in the second-layer wiring. The first to fourth parts are sequentially arranged from one end corresponding to the one end of the eye wiring.
Are arranged, and the wiring of the second layer is partitioned into the first to fifth nodes in order from the one end by the respective resistors, and the first, third, and third wirings are arranged. The fifth node is connected to the first, second, and third circuit cells, respectively, and is connected between the first-layer wiring and the second-layer wiring. , The fourth node, and the fifth node are connected by first to fourth contacts, respectively, and the electric signal generation source is connected to a second node in the first layer wiring. The resistance of the first resistor in the wiring of the first layer is substantially equal to the resistance of the second resistor, and the resistance of the first resistor in the wiring of the first layer is substantially equal. And the resistance value of the third resistor in the wiring of the second layer is substantially equal to the resistance of the third resistor in the wiring of the second layer. The resistance value is approximately equal to the resistance value of the first resistor.

As a result, the difference in delay time between the circuit cell arranged at the end and the circuit cell arranged at the center can be substantially eliminated.

A first semiconductor memory device according to the present invention includes a plurality of circuit cells including at least first and second circuit cells functioning as a main memory cell and a third circuit cell functioning as a reference memory cell; are connected via the interconnections in the circuit cell, a electrical signal generating source for generating a signal to be supplied to each circuit cell, the electrical signal source - in the resistance in the wiring between the circuit cells The maximum value is the resistance value in the wiring between the electric signal generation source and the first circuit cell, and the minimum value among the resistance values in the wiring between the electric signal generation source and each circuit cell is the electric signal generation source. -The resistance value in the wiring between the second circuit cells, and the electric signal generation source-
The resistance value in the wiring between the third circuit cells is set to be a value between the maximum value and the minimum value .

Thus, in the semiconductor memory device,
The delay time difference between the reference memory cell and the main memory cell to which a signal is transmitted with the maximum and minimum delay times is made uniform, so that the delay time difference between the main memory cell and each reference memory cell in the semiconductor memory device is obtained. , The largest delay time difference is reduced. Therefore, for example, high-speed operation is possible even in a nonvolatile memory using a ferroelectric material as a memory cell capacitor, in which a signal generation source is a drive circuit of a plate electrode of a memory cell, and each circuit cell is a main body memory cell and a reference memory cell. In addition, malfunctions are less likely to occur even when the ferroelectric capacitor is deteriorated or varied, and a highly reliable semiconductor memory device is obtained.

According to the first semiconductor memory device of the present invention, there are provided a plurality of circuit cells connected to a common bit line, and a signal connected to each of the circuit cells via a wiring and supplied to each of the circuit cells. And a plurality of circuit cells, wherein the plurality of circuit cells function as a main body memory cell.
And at least a third circuit cell and a fourth circuit cell functioning as reference memory cells, and a resistance value in a wiring between the electric signal generation source and the first circuit cell. The resistance value in the wiring between the electric signal generation source and the third circuit cell is substantially the same, and the resistance value in the wiring between the electric signal generation source and the second circuit cell and the electric signal generation source resistance in wiring between the fourth circuit cells Ru approximately the same der.

The upper SL first circuit cell and the said third circuit cells are selected simultaneously, and the second circuit cell and said fourth circuit cell can be configured to be simultaneously selected.

As a result, since there is almost no delay time difference between each main memory cell and each reference memory cell, a highly reliable semiconductor memory device such as a ferroelectric memory capable of high-speed operation can be constructed. become.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an electric signal supply circuit and a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

In FIG. 1, the relationship between reference numerals and member names is as follows. SD is a signal source, C11 to C15 are circuit cells, R111 to R121 are resistors, N111 to N
Reference numeral 115 indicates a node. However, in the present embodiment and each embodiment, the resistor is generally a member for representing the resistance of the signal wiring, and in reality, there is no resistive member other than the wiring. However, it is assumed that the resistance of the signal wiring is so small as to be negligible, and also includes the case where a separate resistive member is provided.

In the circuit shown in FIG.
Is connected to a node N113 via a resistor R121,
Each of the nodes N111 to N115 has a circuit cell C
11 to C15 are connected. And the node N11
1 and the node N112, and a resistor R112 between the node N112 and the node N113.
However, a resistor R113 is provided between the node N113 and the node N114, and a resistor R114 is provided between the node N114 and the node N115. That is, the signal output from the signal generation source SD is
11, the resistor R121, R112 and R111, the circuit cell C12 via the resistor R121 and R112, the circuit cell C13 via the resistor R121, the circuit cell C14 via the resistor R121 and R113, The circuit cell C15 includes resistors R121, R113 and R11.
4 respectively. That is, in the present embodiment, the signal generation source SD disposed at the end of the circuit cells C11 to C15 is connected to the resistor R1 at the node N113 which is the center of the node row connected to each of the circuit cells C11 to C15.
21 is different from the configuration of the above-described conventional example.

FIG. 2 shows signal transmission characteristics in the electric signal supply circuit according to the present embodiment. As shown in the figure,
The signal level voltage at the node N113 when the signal from the signal generation source SD is changed from the logic voltage "L" to the logic voltage "H" becomes like a signal level voltage curve 11, and the node N111
Alternatively, the signal level voltage of N115 is as shown by a signal level voltage curve 12. This is because each of the circuit cells C11 to C1
5 including parasitic capacitances and resistors R111 to R1
14 due to the signal delay.

In this circuit configuration, the signal delay time at the node N113 is the shortest, and the signal delay time at the node N111 or the node N115 is the longest. The difference between the minimum signal delay time and the maximum signal delay time is the same as in the conventional example (FIG. 16). For example, assuming that the resistance value between each circuit cell and the capacitance including the parasitic capacitance of each circuit cell are the same, the delay time difference is 1/1 of the conventional example.
It will be about 4.

Particularly, in this embodiment, the resistor R11
By making the resistance value of each of the nodes N111 to N115 smaller than the resistance value of the resistor R121,
There is an advantage that the delay time difference between (circuit cells C11 to C15) can be reduced. In order to increase the resistance value of the resistor R121, for example, the wiring width may be reduced.

The wiring including the resistor R121 and the wiring including the resistors R111 to R114 may be arranged two-dimensionally or three-dimensionally. When arranged in a plane, there is an advantage that only one wiring layer is required, and when arranged three-dimensionally, there is an advantage that an occupied area is small.

(Second Embodiment) Next, a second embodiment will be described with reference to FIG.

In this embodiment, six circuit cells C21 to C21
C26 is connected to each of the six nodes N211 to N216, and the nodes N211 and N212 are connected via the resistor R211 to the nodes N212 and N213.
Means a node N214 and a node N via a resistor R212.
215 is connected via a resistor R213, and the node N215 and the node N216 are connected via a resistor R214. However, in the present embodiment, the node N21
3 and the node N214 are not directly connected. The node N217 is connected to the signal generation source SD via the resistor R231.
To the node N2 via the resistors R221 and R222.
12, N215 are connected respectively.

In the electric signal supply circuit according to the present embodiment,
By making the signal wiring from the signal source SD to each of the circuit cells C21 to C26 into a pyramid shape, there is an advantage that the delay time difference to each of the circuit cells C21 to C26 can be further reduced as compared with the first embodiment.

(Third Embodiment) Next, a third embodiment will be described with reference to FIG.

Each of the circuit cells C21 to C2 according to this embodiment
6, each node N211 to N216 and each resistor R211
The connection relationship with R214 is the same as the connection relationship in the second embodiment shown in FIG. However, in the present embodiment, the signal generation source SD is connected to the node N212 via the resistor R221 and to the node N215 via the resistor R222. In other words, the signal source SD is arranged at the position of the node N217 in FIG. 3, and the resistor R231 does not exist.

In the electric signal supply circuit according to the present embodiment,
As in the second embodiment, by making the signal wiring from the signal source SD to each circuit cell into a pyramid type, the effect that the delay time difference can be further reduced as compared with the first embodiment can be exhibited.

Further, since the circuit cells are arranged by directly branching the wiring from the signal generation source SD in two directions, the resistor R231 can be eliminated as compared with the circuit according to the second embodiment. Only the resistance value in the path from the signal source SD to the circuit cell can be reduced. Therefore, the maximum value of the delay time to the circuit cell farthest from the signal generation source SD becomes small, and the operation of the entire circuit can be speeded up.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG.

As shown in the figure, the electric signal supply circuit according to the present embodiment is different from the electric signal supply circuit according to the second embodiment (see FIG. 3) in addition to the nodes N211 to N211.
A resistor R01 is connected between N216 and each of the circuit cells C21 to C26.
Through R06. That is, the circuit cell C
A resistor R01 is interposed between a node N201 and a node N211 connected to the node 21 and a resistor R0 is connected between a node N202 and a node N212 connected to the circuit cell C22.
2 and a node N20 connected to the circuit cell C23.
3 and a node N213, a resistor R03 is provided between the node N204 and the node N2 connected to the circuit cell C24.
14, a resistor R04 is provided between the node N205 and the node N215 connected to the circuit cell C25, and a resistor N05 is provided between the node N215 and the node N206 and the node N216 connected to the circuit cell C26. A resistor R06 is interposed between them. The connection relationship between each of the nodes N211 to N216 and the signal generation source SD and the arrangement state of the resistors R211 to R231 are as described in the second embodiment for the circuit shown in FIG.

In the electric signal supply circuit according to the present embodiment,
As in the first and second embodiments, the effect that the delay time difference can be reduced can be exhibited by making the signal wiring from the signal generation source SD to each circuit cell a pyramid type.

Further, in the fourth embodiment, each of the nodes N211 to N21 which are pyramid-shaped wiring ends is used.
Since the circuit cells C21 to C26 are connected to the circuit cells C21 to C26 through the resistors R01 to R06, the influence of the capacitance including the parasitic capacitance of each of the circuit cells C21 to C26 is less likely to appear at the nodes N211 to N216. As a result, the effect that the delay time can be further reduced can be exhibited.

(Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIGS. FIG. 6 is a block circuit diagram schematically showing a circuit configuration of the ferroelectric memory device according to the present embodiment. As shown in the figure, the circuit according to the present embodiment differs from the circuit cell C11 to C15 in the semiconductor integrated circuit according to the first embodiment shown in FIG. It has the same configuration as that replaced by RC1. Then, the circuit cell C11,
C12, C14, and C15 are main circuit cells.

FIG. 7 is an electric circuit diagram showing a configuration of a ferroelectric memory device which is a specific example of the semiconductor integrated circuit shown in FIG. However, FIG. 7 shows only a part of one column of the memory cell array in the ferroelectric memory device. In the figure, the relationship between reference numerals and member names is as follows. WL0 to WL7 are word lines, RWL
0 and RWL1 are reference word lines, BL and XBL are a pair of bit lines for respectively supplying a non-inverted bit line signal and an inverted bit line signal, and CP0 to CP3 and RCP.
0 is a cell plate electrode, CPD is a cell plate signal supply source, SA is a sense amplifier, CC0 to CC7 are main body memory cell capacitors formed of a ferroelectric, and CR0 and CR1.
Denotes a reference memory cell capacitor formed of a ferroelectric, and Qn0 to Qn7, QnR0, and QnR1 denote N-channel transistors, respectively. However, in FIG. 7, a memory cell composed of a set of two memory capacitors and two N-channel transistors is also arranged in another column, and each cell plate electrode CP, RCP extends along a row in the drawing, and Each memory cell arranged in a row of the cell array is connected.

As shown in the figure, the ferroelectric memory device according to the present embodiment is configured as follows. Each bit line BL, XBL is connected to the sense amplifier SA. One electrode of each of the main body memory cell capacitors CC0 to CC7 is connected to an N-channel type MOS transistor Qn.
0 to Qn7 to the bit line BL or XBL.
The gate of n7 is connected to word lines WL0 to WL7, respectively. Also, the main body memory cell capacitor CC0
And the other electrode of CC1 is a common cell plate electrode CP
0, and the main memory cell capacitors CC2 and CC3
Is the common cell plate electrode CP1,
The other electrodes of the main body memory cell capacitors CC4 and CC5 form a common cell plate electrode CP2, and the other electrodes of the main body memory cell capacitors CC6 and CC7 form a common cell plate electrode CP3. Similarly, one electrode of each of the reference memory cell capacitors CR0 and CR1 is connected to an N-channel MOS transistor QnR.
0, QnR1 to the bit line BL or XBL.
The gate of QnR1 is connected to word lines RWL0, RWL1. The other electrodes of the reference memory cell capacitors CR0 and CR1 are a common cell plate electrode RCP0. In addition, cell plate electrode C
P0 and CP1 are connected via a resistor R14, cell plate electrodes CP1 and RCP0 are connected via a resistor R13, cell plate electrodes RCP0 and CP2 are connected via a resistor R12, and cell plate electrodes CP2 and CP3 are connected via a resistor R12. Resistor R11
, And the cell plate electrode CP3 is connected to a cell plate signal supply source CPD. That is, the reference memory cell capacitor CR
The cell plate electrodes RCPO for 0 and CR1 are arranged at the center of the other cell plate electrodes CP0 to CP3.

Each member arranged in the ferroelectric memory device shown in FIG. 7 corresponds to each element in the semiconductor integrated circuit shown in FIG. 6 as follows. Each cell plate electrode CP3
CP2, RCP1, CP1, and CP0 are nodes N in FIG.
111, N112, N113, N114, and N115, respectively. A memory cell composed of main body memory cell capacitors CC0 and CC1 and N-channel transistors Qn0 and Qn1 connected to the cell plate electrode CP0, and each memory cell (not shown) arranged in this row are the main circuit shown in FIG. Corresponds to cell C15. Similarly,
Each memory cell connected to the cell plate CP1 corresponds to the main circuit cell C14 in FIG. Further, each reference memory cell connected to the cell plate electrode RCP0 corresponds to the reference circuit cell RC1 in FIG. Similarly, the memory cells connected to the cell plates CP2 and CP3 respectively correspond to the main circuit cells C12 and C11 in FIG.

In this embodiment, as shown in FIG. 7, the reference memory cell capacitors CR0 and CR1 are arranged at the center of the main body memory cell capacitors CCO to CC7. The difference between the delay times of the signals supplied from the cell plate signal supply source CPD to the two cell plate electrodes becomes smaller. Therefore, the dependence of the amount of charge read from the main body memory cell capacitor and the reference memory cell capacitor to the bit line BL or XBL does not depend on the arrangement of the memory cells. As a result, a stable operation and a high-speed operation can be achieved, and a highly reliable ferroelectric memory device that is less likely to malfunction even when the ferroelectric capacitor is deteriorated or varied can be provided.

FIG. 8 is a diagram showing the change over time of the signal level at each node of the circuit shown in FIG. In the figure, a signal level curve 13 indicates the signal level of the node N111, a signal level curve 14 indicates the signal level of the node N115, and a signal level curve 15 indicates the signal level of the node N113. That is, the signal level curve 15 of the reference circuit cell RC1 is a curve passing between the signal level curves 13 and 14 of the maximum delay of the main circuit cell, and the difference between the delay times of the reference circuit cell and the main circuit cell is smaller than that of the conventional configuration. Smaller.

(Sixth Embodiment) Next, a sixth embodiment will be described with reference to FIG.

As shown in FIG. 9, the circuit configuration of the ferroelectric memory device according to the present embodiment includes six circuit cells C1 in the electric signal supply circuit according to the first embodiment shown in FIG.
Instead of one circuit cell C12 of 1 to C16,
This is one in which reference circuit cells RC1 constituting reference memory cells are arranged. Then, the signal generation circuit SD, each of the nodes N111 to N115 and each of the resistors R11
1 to R114 and R121 are as described with reference to FIG. 1 in the first embodiment.

In the present embodiment, the signal generation source SD is, for example, a cell plate signal supply source. In the electric signal supply circuit having this configuration, the node N111 or N115 has the maximum delay time from the signal of the signal generation source SD, and the node N113 has the minimum delay time from the signal of the signal generation source SD. The node N112 or N114 has an intermediate delay time. Then, a reference circuit cell RC1 forming a reference memory cell from the signal generation source SD
The delay time of the signals up to the respective main body circuit cells C11, C13, C1 constituting the main body memory cells from the signal generation source SD
The values and the like of the resistors R111 to R121 are set so as to be intermediate values between the maximum delay time and the minimum delay time of the signals up to C4 and C15.

In the present embodiment, the ferroelectric memory device having such a memory cell array structure allows the main memory cell constituting the main memory cell to have a fifth delay time difference from the signal generation source SD. The delay time of the signal from the signal source SD to the circuit cell RC1 forming the reference memory cell is smaller than that of the embodiment, and the circuit cells C11, C13, C14, C15 forming the main memory cell from the signal source SD are reduced. Since the intermediate delay time is set to an intermediate value between the maximum delay time and the minimum delay time of the signals up to this point, a ferroelectric memory device with a stable operation and a high-speed operation can be obtained.

(Seventh Embodiment) Next, a seventh embodiment will be described with reference to FIG.

As shown in FIG. 10, the circuit configuration of the ferroelectric memory device according to the present embodiment has six circuit cells C21 to C26 in the circuit according to the second embodiment shown in FIG.
Of the reference circuit cell R constituting the reference memory cell in place of the two circuit cells C25 and C26 of FIG.
C1 and RC2 are arranged. Signal source SD,
Nodes N211 to N217 and resistors R211 to R211
214, R221 and R222 are in the second
This is as described with reference to FIG.

The delay time from the signal source SD to each of the reference circuit cells RC1 and RC2 is set to be different from each other, and when one of the circuit cells C21 to C24 constituting the main memory cell operates. , The reference circuit cell having the delay time closest to the delay time of the signal from the signal generation source SD to the circuit cell can be selected.

In the present embodiment, a ferroelectric memory device having a configuration as shown in FIG. 10 is used. An advantage is obtained that the delay time difference to the circuit cell can be reduced as compared with the sixth embodiment.

In addition, reference circuit cells RC1, R
C2 is provided at a plurality of locations, and any one of the plurality of reference circuit cells can be selected according to the location where the selection of the circuit cell constituting the main body memory cell is performed, that is, the delay time. And the reference circuit cell constituting the reference memory cell, the delay time difference of the signal supplied from the signal generation source SD can be reduced, and especially the signal wiring from the signal generation source SD has a large memory capacity. In a ferroelectric memory device having a long length, stable operation and high-speed operation can be performed.

(Eighth Embodiment) Next, an eighth embodiment will be described with reference to FIGS.

As shown in the drawing, the electric signal supply circuit according to the present embodiment comprises a signal generation source SD and a signal generation source S.
Wiring W310 derived from D via a resistor R310
A first-layer wiring connected to the wiring W310;
It includes seven circuit cells C31 to C37 and a second-layer wiring connected to each circuit cell. Two resistors R311 and R312 are interposed in the first layer wiring, and six resistors R321 to R32 are provided in the second layer wiring.
6 are interposed. In this embodiment, the nodes are displayed separately for the first-layer wiring and the second-layer wiring. In the first layer wiring, each of the resistors R311 and R31
The node 312 is partitioned into three nodes N311 to N313. In the second layer wiring, each of the circuit cells C31 to C3 is set by the resistors R321 to R326.
7 are directly divided into seven nodes N321 to N327. Here, a feature of the present embodiment is that first to third contacts CT311 to CT313 are provided between the first layer wiring and the second layer wiring. In other words, the node N311 in the first-layer wiring and the node N322 in the second-layer wiring are connected to the node N31 in the first-layer wiring by the first contact CT311.
2 and the node N324 in the second layer wiring are connected to the node 3 in the first layer wiring by the second contact CT312.
13 and a node N326 in the wiring of the second layer are connected to each other by a third contact CT313. In other words, the resistor R311 and the resistor R311,
R312 are arranged in series, and a resistor R3
21 to R326 are arranged in series, and a signal is transmitted from a plurality of nodes partitioned by the resistors R311 and R312 of the first layer wiring to a plurality of nodes of the second layer wiring via a plurality of contacts. It is configured to supply.

In the electric signal supply circuit according to the present embodiment,
By connecting the wiring of the first layer in which the resistors R311 and R312 are arranged and the wiring of the second layer in which the resistors R321 to R326 are arranged at a plurality of points, each circuit cell except the circuit cells at both ends is connected. Since a signal is supplied via a plurality of contacts, that is, via a plurality of paths, each circuit cell C3
The signal delay time difference between 1 to C37 can be reduced,
Since the distance from the signal source SD to the farthest circuit cell is shortened, the maximum delay time, that is, the delay time of the system can be significantly reduced.

In this embodiment, a plurality of contacts CT311 are provided between the first-layer wiring and the second-layer wiring.
To CT 313 are formed, and the wiring length between the end of the wiring of the second layer and the first contact CT 311 closest to the end is between the first contact CT 311 and the second contact CT 312. It is configured to be about half the wiring length. In other words, all of the nodes N321, N322, N323,
Of the N324, N325, N326, and N327, even-numbered nodes N322, N324, and N326 are connected so as to be connected to the first-layer wiring. That is, the number of nodes of the second layer wiring is odd (2m + 1) (m is a natural number,
In the present embodiment, when m = 3), the number of contacts with the first-layer wiring is m. Further, in the present embodiment, since the wiring width is uniform, the resistance value of the resistor R321 between the end of the second-layer wiring and the first contact CT311 closest to that end is equal to the first contact. CT
The resistances of the resistors R322 and R323 (the resistances of which are equal to each other) disposed between the contact 311 and the second contact CT312 are configured to be approximately half the respective resistances. That is, each of the resistors 321, 322, 323, 3
24, 325 and 326 have equal resistance values. In other words, when the width of the signal wiring, that is, the cross-sectional area is the same, the intervals between the circuit cells are equal. Therefore, the layout is simplified, and the structure is practically advantageous in advancing the manufacturing process.

Next, FIG. 12 is a circuit diagram of a memory cell array of a ferroelectric memory device to which the circuit configuration of FIG. 11 is applied. In the present embodiment, unlike the example shown in FIG. 7, only the main body memory cells are displayed and the reference memory cells are not displayed, but the reference memory cells are arranged at other positions in this column. Although only one column is shown in the figure, it goes without saying that there are many other columns.

In the figure, the relationship between reference numerals and member names is as follows. WL0 to WL13 are word lines, BL,
XBL is a pair of bit lines for supplying a non-inverted bit line signal and an inverted bit line signal, respectively, CP0 to CP6.
Is a cell plate electrode, CPD is a cell plate signal supply source as a signal generation source, SA is a sense amplifier, CC0 to C
C13 denotes a main body memory cell capacitor formed of a ferroelectric, and Qn0 to Qn13 denote N-channel transistors. However, in FIG. 12, a memory cell including a set of two memory capacitors and two N-channel transistors is arranged in another column, and each cell plate electrode CP extends along a row in the figure, and Each memory cell arranged in a row is connected.

As shown in the figure, the ferroelectric memory device according to the present embodiment is configured as follows. Each bit line BL, XBL is connected to the sense amplifier SA. One electrodes of the main body memory cell capacitors CC0 to CC13 are respectively connected to N-channel transistors Qn0 to Qn0.
It is connected to the bit line BL or XBL via Qn13, and the gates of the N-channel transistors Qn0 to Qn13 are connected to word lines WL0 to WL13, respectively. The other electrodes of the pair of main body memory cell capacitors CC0 and CC1, CC2 and CC3 are common cell plate electrodes CP0, CP1,. The cell plate electrodes CP0 and CP1 are connected via a resistor R326, the cell plate electrodes CP1 and CP2 are connected via a resistor R325, and the cell plate electrodes CP2 and CP3 are connected via a resistor R324. CP3 and CP4 are connected via a resistor R323, and the cell plate electrodes CP4 and CP5 are connected via a resistor R322.
The cell plate electrodes CP5 and CP6 are connected to each other via a resistor R321. Then, every other cell plate electrodes CP5, CP
3, contacts CT311 to CT313 are formed on CP1.

In the ferroelectric memory device shown in FIG. 12, each memory cell arranged in each row connected to each cell plate electrode CP0 to CP6 is a circuit cell C3 in FIG.
1 to C37.

In the ferroelectric memory device according to the present embodiment, the delay time difference between the main body memory cells in the memory cell array can be reduced as much as possible by the configuration shown in FIGS.

(Ninth Embodiment) Next, a ninth embodiment will be described with reference to FIG.

As shown in the figure, the electric signal supply circuit according to the present embodiment includes a signal generation source SD and a signal generation source S.
Wiring W410 derived from D via a resistor R410
A first-layer wiring connected to the wiring W410;
A large number of circuit cells including three circuit cells C41 to C43 and a second-layer wiring connected between the circuit cells are provided. Further, two resistors R4 are provided in the first layer wiring.
11 and R412 are interposed, and four resistors R421 to R424 are interposed in the wiring of the second layer. The first layer wiring is divided into three nodes N411 to N413 by the resistors R411 and R412. In the second-layer wiring, each resistor R42
1 to R424, five nodes N421 to N425
Is divided into Here, the feature of the present embodiment is that the node N411 in the first layer wiring and the node N422 in the second layer wiring are connected to the first contact CT411.
As a result, the node N413 in the first layer wiring and the node N424 in the second layer wiring are connected to the second contact CT4.
12 are connected to each other. However, the center node N412 in the wiring of the first layer is
No contact is formed with the node N423 in the wiring of the layer.

Further, in the present embodiment, the resistance values r22 and r23 of the two resistors R422 and R423 arranged on the path connected to the circuit cell C42 which receives the supply of charge (signal) from two directions, The relationship between the resistance value r21 of the resistor R421 disposed on the path connected to the circuit cell C41 that receives the supply of electric charges only from the following equation is given by the following equation (1): r21: r22 (= r23) = 1: √2 (1) It is set as follows. Note that the resistance value of the resistor R424 disposed on the path connected to the circuit cell C43 disposed on the other end and the resistances R422 and R423 disposed on the path connected to the central circuit cell C42. A similar relationship is established between the resistance value and the resistance value. However, the resistance values of the resistor R411 and the resistor R412 are equal. By setting as described above, each circuit cell C41, C42
To the delay time can be equalized. This will be described. Assuming that the capacitance of each of the circuit cells C41 and C42 is the same CA1, the condition that the delay time of the signal from the first layer wiring to both circuit cells represented by the following equation (2) is equal, that is, r21 × α · r21 · CA = (r22 / 2) · r22 · CA (2) The above equation (1) is derived.

In the present embodiment, by setting as described above, a configuration with a small delay time difference can be obtained as a whole. Further, similarly to the eighth embodiment, since the distance from the signal generation source SD to the farthest circuit cell is reduced, the maximum delay time, that is, the delay between the systems can be significantly reduced. . However, the resistor R42
If the resistance value of No. 2 is larger than the resistance value of the resistor R421, the effect of minimizing the delay time difference between the circuit cells C41 and C42 can be obtained.

Although not shown, it goes without saying that the configuration of this embodiment can be applied to the structure of the memory cell array of the ferroelectric memory device as shown in FIG.

When a plurality of contacts are provided between the first-layer wiring and the second-layer wiring, the method of arranging the contacts is not limited to the method of this embodiment. .

(Tenth Embodiment) Next, a tenth embodiment will be described with reference to FIG.

As shown in the figure, the electric signal supply circuit according to the present embodiment includes a signal generation source SD and a signal generation source S.
Wiring W510 derived from D via a resistor R510
A first layer wiring connected to the wiring W510;
A large number of circuit cells including three circuit cells C51 to C53 and a second-layer wiring connected between the circuit cells are provided. The first layer wiring has four resistors R5.
11 to R514 are interposed, and four resistors R521 to R524 are interposed in the wiring of the second layer. In this embodiment, the nodes are displayed separately for the first-layer wiring and the second-layer wiring. The first layer wiring is divided into five nodes N511 to N515 by the resistors R511 to R514. Further, in the wiring of the second layer, each of the resistors R521 to R524 is partitioned into five nodes N521 to N525. Here, the feature of this embodiment is that the first to fourth contacts C are provided between the first layer wiring and the second layer wiring.
The point is that T511 to CT514 are provided. That is, the node N511 in the first layer wiring and the node N521 in the second layer wiring are connected to the first contact CT51.
1, the node N512 in the first layer wiring and the node N522 in the second layer wiring are connected to the second contact CT.
According to 512, the node N514 in the wiring of the first layer and the node N524 in the wiring of the second layer are connected to the node N515 in the wiring of the first layer by the third contact CT513.
And a node N525 in the wiring of the second layer are connected to each other by a fourth contact CT514.
However, no contact is formed between the central node N513 in the first-layer wiring and the node N523 in the second-layer wiring. That is, in the structure of the electric signal supply circuit according to the present embodiment, in addition to the structure in the ninth embodiment, contacts are formed at both ends of the second-layer wiring via the resistor. Things.

In this embodiment, since the circuit cells C51 (and C53) arranged at the end and the circuit cell C52 arranged at the center receive the supply of electric charges from two directions, the resistors R511 and R521 are combined. Resistance value and resistor R512,
By setting the combined resistance value of R522 to the same value, the delay time to both circuit cells is set to be equal. However, the resistance values of the resistor R512 and the resistor R513 are equal.

Therefore, according to the present embodiment as well, a configuration with a small delay time difference can be obtained as a whole.
In particular, the configuration of the present embodiment has an advantage that the resistance value of each resistor can be easily adjusted as compared with the ninth embodiment. Further, similarly to the eighth embodiment, since the distance from the signal generation source SD to the farthest circuit cell is reduced, the maximum delay time, that is, the delay between the systems can be significantly reduced. .

Although not shown, it goes without saying that the configuration of the present embodiment can be applied to the structure of the memory cell array of the ferroelectric memory device as shown in FIG.

When a plurality of contacts are provided between the first-layer wiring and the second-layer wiring, the method of arranging the contacts is not limited to the method of this embodiment. .

[0080]

According to the electric signal generating circuit of the present invention, the wiring connected to the plurality of circuit cells is divided into a plurality of layers,
Since the resistance of the path from the electric signal generation circuit to each circuit cell can be made equal, the delay time of the signal supplied from the signal generation source to each circuit cell can be made substantially equal, thus increasing the circuit operation speed. Stabilization can be achieved.

According to the semiconductor memory device of the present invention, the resistance value in the wiring between the electric signal generation source and the reference memory cell is set to the maximum value and the minimum value of the resistance value in the wiring between the electric signal generation source and each main body memory cell. Value, the maximum value of the delay time difference between the main memory cell and each reference memory cell in the semiconductor memory device can be reduced, and thus the operation speed of the semiconductor memory device can be increased. And reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating a schematic configuration of an electric signal supply circuit according to a first embodiment.

FIG. 2 is a characteristic diagram illustrating a relationship between time and a signal level voltage of the electric signal supply circuit according to the first embodiment.

FIG. 3 is a block circuit diagram illustrating a schematic configuration of an electric signal supply circuit according to a second embodiment.

FIG. 4 is a block circuit diagram illustrating a schematic configuration of an electric signal supply circuit according to a third embodiment.

FIG. 5 is a block circuit diagram illustrating a schematic configuration of an electric signal supply circuit according to a fourth embodiment.

FIG. 6 is a block circuit diagram illustrating a schematic configuration of a ferroelectric memory device according to a fifth embodiment.

FIG. 7 is an electric circuit diagram of a ferroelectric memory device according to a fifth embodiment.

FIG. 8 is a characteristic diagram illustrating a relationship between a time and a signal level voltage of an electric signal supply circuit according to a fifth embodiment.

FIG. 9 is a block circuit diagram illustrating a schematic configuration of a ferroelectric memory device according to a sixth embodiment.

FIG. 10 is a block circuit diagram illustrating a schematic configuration of a ferroelectric memory device according to a seventh embodiment.

FIG. 11 is a block circuit diagram illustrating a schematic configuration of a ferroelectric memory device according to an eighth embodiment.

FIG. 12 is an electric circuit diagram of a ferroelectric memory device according to an eighth embodiment.

FIG. 13 is a block circuit diagram illustrating a schematic configuration of a ferroelectric memory device according to a ninth embodiment.

FIG. 14 is a block circuit diagram illustrating a schematic configuration of a ferroelectric memory device according to a tenth embodiment.

FIG. 15 is a block circuit diagram showing a schematic configuration of a conventional electric signal supply circuit.

FIG. 16 is a characteristic diagram showing a relationship between time and a signal level voltage of a conventional electric signal supply circuit.

[Explanation of symbols]

 SD signal source C circuit cell RC reference circuit cell R resistance N node WL word curve RWL reference word line BL bit line XBL bit line CP cell plate electrode RCP cell plate electrode CPD cell plate signal source SA sense amplifier C body memory cell capacitor CR Reference memory cell capacitor Qn N-channel MOS transistor QnR N-channel MOS transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/413 G11C 11/401

Claims (10)

(57) [Claims] 1. A plurality of circuit cells, an electric signal generating source for generating a signal to be supplied to each of the circuit cells, and a wiring derived from the electric signal generating source and connected at a tip end to each of the circuit cells. Wherein the wiring comprises a first layer derived from the electric signal generation source, and a second branch comprising a branch branching at a center and both sides at a branch point serving as a tip of the first layer. One circuit cell is connected to a branch line extending to the center of the second hierarchy, and a plurality of circuit cells are connected to each branch line extending to both sides of the second hierarchy. The wiring width in the first layer of the wiring is
The wiring width from the branch point in the second hierarchy to each circuit cell is smaller than the wiring width in the second hierarchy from the electric signal generation source in the first hierarchy to the branch point. An electric signal supply circuit, wherein the resistance is set to be smaller than the resistance of the wiring leading to the circuit cell, and the resistance value in the path from the electric signal generation source to each circuit cell is set substantially evenly. 2. A plurality of circuit cells, an electric signal generating source for generating an electric signal to be supplied to each of the circuit cells, and a pyramid-shaped at least three levels after being derived from the electric signal generating source. A wiring that is branched and connected to each of the circuit cells at a tip portion, wherein the wiring is 1 in a final hierarchy connected to the circuit cell.
Branching in three directions from one branch point, and the resistance value in the wiring in the first layer from the electric signal generation source to the first branch point out of the at least three layers is branched from the first layer From the second level to the last level
Each circuit cell from the first branch point in the wiring including the layers
An electric signal supply circuit characterized in that the electric signal supply circuit has a resistance value that is larger than a resistance value of a part that reaches the point. 3. The electric signal generating circuit according to claim 2 , wherein each end of the last layer connected to the circuit cell is connected to each of the circuit cells via a resistor. Electric signal generation circuit. 4. The electric signal generation circuit according to claim 3, wherein the resistance value of the resistor is a resistance value in a wiring from the electric signal generation source in the first hierarchy to a first branch point and the resistance value of the resistance value in the wiring. An electric signal supply circuit, wherein a resistance value is larger than a resistance value in a wiring from the first branch point to each resistor in the second to last layers. 5. A plurality of circuit cells, an electric signal generating source for generating an electric signal to be supplied to the circuit cells, a first layer wiring connected to the electric signal generating source, and each of the circuits A second layer wiring connected to the cell, wherein the first layer wiring and the second layer wiring are at least the first layer wiring.
And an electrical signal generation circuit connected by a plurality of contacts including a second contact, wherein the plurality of circuit cells are at least first, second and third
The first layer wiring includes first and second circuit cells in order from one end.
Are arranged, and the wiring of the first layer is partitioned into the first to third nodes in order from the one end by the resistors, and the wiring of the second layer is The first to fourth resistors are arranged in order from one end corresponding to the one end of the first-layer wiring, and the second-layer wiring is connected to the one of the first resistors by the respective resistors. The first to fifth nodes are partitioned in order from the end, and the first, third, and fifth nodes are connected to the first, second, and third circuit cells, respectively. The first contact is the first contact in the first layer wiring.
And the second contact is formed between the second node and the second node in the second layer wiring, and the second contact is formed in the third layer in the first layer wiring.
And an electric signal generation source is connected to a second node in the first-layer wiring, and a fourth node in the second-layer wiring. In the wiring of the second layer, the resistance value of the second resistor is larger than the resistance value of the first resistor. 6. The electric signal generating circuit according to claim 5 , wherein a resistance value of the first resistor in the wiring of the first layer and a second resistance value of the first resistor are set to be equal to each other.
The resistance value of the second resistor is approximately equal to the resistance value of the second resistor, and the resistance value of the second resistor is √2 times the resistance value of the first resistor. 7. A plurality of circuit cells, an electric signal generating source for generating an electric signal to be supplied to the circuit cells, a first layer wiring connected to the electric signal generating source, and each of the circuits An electric signal generating circuit, comprising: a second-layer wiring connected to a cell, wherein the first-layer wiring and the second-layer wiring are connected by a plurality of contacts; The cells are at least first, second and third
The first layer wiring includes first to fourth resistors arranged in this order from one end, and the first layer wiring is connected to the one end by the respective resistors. From the first end to the fifth end, and the second-layer wiring is connected to the first to fourth nodes in order from one end corresponding to the one end of the first-layer wiring. Are arranged, and the wiring of the second layer is partitioned into the first to fifth nodes in order from the one end by the respective resistors, and the first, third, and third wirings are arranged. The fifth node is connected to the first, second, and third circuit cells, respectively. Between the first-layer wiring and the second-layer wiring,
The first, second, fourth, and fifth nodes are connected to each other by first to fourth contacts, respectively, and the electric signal generation source is connected to a first layer in the first layer wiring. 2 and the resistance value of the first resistor in the wiring of the first layer and the second resistor.
The resistance value of the first resistor in the wiring of the first layer is substantially equal to the resistance value of the third resistor in the wiring of the second layer. An electrical signal generation circuit, wherein the resistance value of the second resistor is substantially equal to the resistance value of the first resistor in the wiring of the second layer. 8. A plurality of circuit cells including at least first and second circuit cells functioning as a main body memory cell and a third circuit cell functioning as a reference memory cell; An electric signal generation source for generating a signal to be supplied to each of the circuit cells, wherein a maximum value of resistance values in wiring between the electric signal generation source and each of the circuit cells is the electric signal generation source. A resistance value in the wiring between the first circuit cells, wherein the minimum value of the resistance values in the wiring between the electric signal generation source and each circuit cell is between the electric signal generation source and the second circuit cell. A resistance value in the wiring, wherein the resistance value in the wiring between the electric signal generation source and the third circuit cell is set to be a value between the maximum value and the minimum value. A semiconductor memory device characterized by the above-mentioned. 9. A plurality of circuit cells connected to a common bit line, and an electric signal generation source connected to each of the circuit cells via a wiring and generating a signal to be supplied to each of the circuit cells. Wherein the plurality of circuit cells include at least a first circuit cell and a second circuit cell functioning as a main body memory cell, and a third circuit cell and a fourth circuit cell functioning as a reference memory cell; The resistance value in the wiring between the electric signal generation source and the first circuit cell is substantially the same as the resistance value in the wiring between the electric signal generation source and the third circuit cell. Wherein the resistance value in the wiring between the circuit cells is substantially equal to the resistance value in the wiring between the electric signal generation source and the fourth circuit cell. 10. The semiconductor memory device according to claim 9 , wherein said first circuit cell and said third circuit cell are selected simultaneously, and said second circuit cell and said fourth circuit cell are simultaneously selected. A semiconductor memory device configured to be selected.