JP2003085976A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce cross talk between bit lines and between bit lines and upper layer wirings or lower layer wirings, in a semiconductor integrated circuit comprising a SRAM. SOLUTION: A semiconductor integrated circuit is provided with a plurality of memory cells having at least a first port and a second port respectively, bit lines of a first group intersecting mutually at a first position between memory cells of each column, bit lines of a second group intersecting mutually at a second position between memory cells of each column, first word lines for selecting one memory cell in a first port of memory cells of each column, second word lines for selecting one memory cell in a second port of memory cells of each column, a write-in circuit writing data in a memory cell selected by a first word line, and a read-out circuit reading out differentially data stored in a memory cell selected by the second word line.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention generally relates to a static random access memory (S) having a plurality of ports.
The present invention relates to a semiconductor integrated circuit including RAM) cells.

[0002]

2. Description of the Related Art The structure of a conventional semiconductor integrated circuit having a 2-port SRAM cell will be described with reference to FIG. FIG. 3 shows four memory cells 1 to 4 out of a plurality of memory cells included in this semiconductor integrated circuit. Each memory cell has a pair of bit lines BL1a and BL1a bar, and , BL1b and BL1b bar. Information corresponding to 1 bit can be stored in one memory cell, and the stored information can be stored in a pair of bit lines BL1a and BL1a bar or B.
Sense amplifier SA1a via L1b and BL1b bar
Alternatively, it can be read by SA1b.

In the semiconductor integrated circuit shown in FIG. 3, peripheral circuits are configured so that data cannot be simultaneously read / written to / from memory cells having the same address. Meanwhile, the bit lines BL1a and BL1a
It is possible to write data to the memory cell 1 via the bar and read data from the memory cell 2 via the bit lines BL1b and BL1b bar at the same time. However, the bit lines BL1a and BL1a
The write voltage applied to the bar may propagate as crosstalk to the bit lines BL1b and BL1b bar due to capacitive coupling between the bit lines, and the data may not be correctly read from the memory cell 2.

That is, between a plurality of memory cells connected to two pairs of bit lines, when data is written / read at two ports at the same time, crosstalk occurs between the bit lines. There was a problem that malfunction occurred.

In order to prevent such a malfunction at the time of simultaneous writing / reading, as shown in FIG. 4, a pair of bit lines BL1b and BL1b bar are crossed with each other. Here, the inversion of data caused by intersecting the paired bit lines BL1b and BL1b bar is avoided by changing the wiring to the memory cell 2 and the memory cell 4.

By making the bit line a cross structure, the stray capacitance between the bit line BL1a and the bit line BL1b becomes equal to the stray capacitance between the bit line BL1a and the bit line BL1b bar. The same applies to the bit line BL1a bar. This allows
Even if data is written using the bit lines BL1a and BL1a bar, the bit lines BL1b and BL1b
Crosstalk to the bar can be canceled at the input stage of the sense amplifier SA1b.

Here, Japanese Patent Application Publication (JP-A) No. Hei 8
-273350 discloses a plurality of bit line pairs arranged in parallel, memory cells for storing information charges respectively connected to the plurality of bit line pairs, and a predetermined number of bits of the plurality of bit lines. A bit line that corresponds to a line pair in common, is arranged in parallel with the bit line pair, and includes a column signal line for selectively activating the corresponding bit line pair, and each bit line pair forms a pair. There is described a semiconductor memory device in which three-dimensionally intersecting at arbitrary positions so that the arrangement positions of the two are switched.
In this semiconductor memory device, each bit line of the bit line pair is crossed with each other to avoid an unbalanced stray capacitance between the bit lines of the bit line pair.

Further, in Japanese Patent Application Laid-Open No. 5-109287, one of a pair of bit lines forming a first bit line pair forms a pair of adjacent second bit line pairs. In a semiconductor memory device having a bit line layout pattern arranged between the bit lines, a pair of bit lines forming a second bit line pair is arranged between the pair of bit lines. The semiconductor memory device is described in which the bit lines of the bit line pair are three-dimensionally crossed with each other without being connected. In this semiconductor memory device,
Coupling noise to the memory cell is reduced by disposing one bit line of the bit line pair between a pair of bit lines forming a bit line pair adjacent to the bit line pair and by making the bit line cross structure. ing.

However, in a semiconductor integrated circuit having a multi-layer wiring structure, another wiring may be formed above or below the layer in which the bit line is formed. In such a case, the bit line is formed. There is a problem that crosstalk occurs between the wiring and the upper or lower layer wiring, and a malfunction occurs when reading data.

In order to prevent such crosstalk between wirings having a multilayer structure, as shown in FIG.
It is conceivable that the pair of bit lines BL1a and BL1a bar intersect with each other and the pair of bit lines BL1b and BL1b bar intersect with each other to have a double cross structure. As a result, crosstalk between the bit line and the upper layer wiring can be canceled.

However, in the double cross structure, the bit line BL1a and the bit line BL1b are always adjacent to each other, and the bit line BL1a bar and the bit line BL1b bar are always adjacent to each other. Therefore,
Since crosstalk occurs between two pairs of bit lines forming two ports, this does not solve the problem.

[0012]

Therefore, in view of the above points, the present invention reduces crosstalk between bit lines in a semiconductor integrated circuit including an SRAM cell, and further reduces the bit lines and the upper or lower layer wiring. It is intended to prevent malfunction in reading stored data by reducing crosstalk between the two.

[0013]

In order to solve the above problems, a semiconductor integrated circuit according to a first aspect of the present invention is a plurality of memory cells arranged in a matrix, each of which is at least a first memory cell. A plurality of memory cells having a first port and a second port, and a first set of bit lines connected to the first ports of the memory cells of each column, the first set of bit lines between the memory cells of each column. A first set of bit lines intersecting each other at a position and a second set of bit lines connected to a second port of the memory cells in each column, the second position between the memory cells in each column. Of the second set of bit lines intersecting each other at, the first word line for selecting one of the first ports of the memory cells in each column, and the second port of the memory cells in each column. A second word for selecting one of the And a write circuit for writing data to the memory cell selected by the first word line and connected to the first port of the memory cell of each column via the first set of bit lines, and the second set of bits. A read circuit connected to the second port of the memory cell in each column via a line and differentially reading the data stored in the memory cell selected by the second word line.

Here, the first position exists between the (2N) th memory cell and the (2N + 1) th memory cell in each column (N = 1, 2, ...), The second position may be located between the (2N-1) th memory cell and the (2N) th memory cell in each column.

Alternatively, the first position exists between the (2N-1) th memory cell and the (2N) th memory cell in each column (N = 1, 2, ...). , The second position may be between the (2N) th memory cell and the (2N + 1) th memory cell in each column.

In the above, the first set of bit lines includes a first bit line and a second bit line, and a second bit line
The set of bit lines includes a third bit line and a fourth bit line, the length of the section in which the first bit line is adjacent to the third bit line and the first bit line is the fourth bit. The length of the section adjacent to the line is substantially equal, and the length of the section of the second bit line adjacent to the third bit line and the fourth bit line are equal to the fourth bit line.
It is desirable to make the lengths of the sections adjacent to the bit lines of (3) substantially equal to each other.

According to the semiconductor integrated circuit of the present invention configured as described above, it is possible to balance the coupling capacitance between the bit lines and the coupling capacitance between the wirings of the multilayer structure. Therefore, by reducing the crosstalk between bit lines, and further by reducing the crosstalk between the bit line and the upper or lower layer wiring,
It is possible to prevent malfunctions in reading stored data.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a part of a semiconductor integrated circuit according to an embodiment of the present invention. This semiconductor integrated circuit includes a memory cell array composed of a plurality of SRAM cells arranged in a matrix. FIG. 1 shows four memory cells 1 to 4 in any one column. Each memory cell has a pair of first
A pair of bit lines BL1a and BL1a bar and a second
It is connected to the pair of bit lines BL1b and BL1b bar. Further, this semiconductor integrated circuit has memory cells 1 to 4
And a sense amplifier SA1a and SA1b for reading data from the memory cells 1 to 4 in two systems. One memory cell can store one bit of information,
The stored information is stored in the first set of bit lines BL1a and B1.
L1a bar or the second set of bit lines BL1b and B
Sense amplifier SA1a or SA1 via L1b bar
It can be read by b.

In the semiconductor integrated circuit shown in FIG. 1, peripheral circuits are configured so that data cannot be simultaneously read / written to / from memory cells having the same address. Meanwhile, the bit lines BL1a and BL1a
It is possible to write data to the memory cell 1 via the bar and read data from the memory cell 2 via the bit lines BL1b and BL1b bar at the same time.

FIG. 2 shows a circuit diagram of a memory cell included in the semiconductor integrated circuit of FIG. As shown in FIG. 2, this memory cell has inverting circuits INV1 and INV2 and N
It includes channel MOS transistors QN11 to QN14. The inverting circuit INV1 has an input connected to the first store node N1 and an output connected to the second store node N2. The input of the inverting circuit INV2 is connected to the second store node N2, and the output is connected to the first store node N1.

The source-drain path of the transistor QN11 is composed of the first store node N1 and the bit line BL1.
It is connected to a. The source-drain path of the transistor QN12 is connected between the second store node N2 and the bit line BL1a bar. The gates of the transistors QN11 and QN12 are connected to the word line WL1a.

The source-drain path of the transistor QN13 has a first store node N1 and a bit line BL1.
It is connected with b. The source-drain path of the transistor QN14 is connected between the second store node N2 and the bit line BL1b bar. The gates of the transistors QN13 and QN14 are connected to the word line WL1b.

In this memory cell, transistors QN11 and QN12 form a first port (write / read port), and transistors QN13 and QN14
It constitutes a second port (read-only port).

The operation of writing data to the memory cell will be described with reference to FIG. In writing data, a high level signal is supplied to the word line WL1a, a high level signal is supplied to the bit line BL1a, and a low level signal is supplied to the bit line BL1a bar. . Word line W
By supplying a high level signal to L1a,
The transistors QN11 and QN12 are turned on. As a result, the store node N1 has the bit line BL1a.
The same high level as above, and the store node N2 has the same low level as above the bit line BL1a bar.
The inversion circuits INV1 and INV2 maintain this state, whereby 1-bit data is stored in the memory cell.

Next, the operation of reading data from the memory cell will be described. When data is read through the write / read port, a high level signal is supplied to the word line WL1a and the transistors QN11 and QN11
N12 is turned on. As a result, the bit line B
L1a becomes the same level as the store node N1, and the bit line BL1a bar becomes the same level as the store node N2. Bit line BL1a using a sense amplifier
And the BL1a bar level are differentially detected to write / write the 1-bit data stored in the memory cell.
Read through the read port.

On the other hand, when data is read using the read-only port, a high level signal is supplied to the word line WL1b and the transistors QN13 and QN14 are supplied.
Turns on. As a result, the bit line BL1b
Becomes equal to the level of the store node N1 and the bit line BL1b bar becomes equal to the level of the store node N2. Bit lines BL1b and BL using sense amplifiers
By differentially detecting the level of 1b bar, 1-bit data stored in the memory cell is read out through the read-only port.

As described above, the word line WL1a is used to select the memory cell to be written / read, and the word line WL1b is used to select the memory cell to be read. By using two systems of word lines WL1a and WL1b connected to two types of ports, writing by the word line WL1a and reading by the word line WL1b are performed asynchronously,
Alternatively, the reading by the word line WL1a and the reading by the word line WL1b can be performed at different timings.

Referring again to FIG. 1, memory cells 1-4.
A first set of bit lines BL1a and BL1a connected to
The bars are crossed with each other between the memory cells 2 and 3, between the memory cells 4 and 5 (not shown), to form a cross structure. Further, the second set of bit lines BL1b and BL1b bar connected to the memory cells 1 to 4 are mutually connected between the memory cell 1 and the memory cell 2, between the memory cell 3 and the memory cell 4 ,. A cross structure is formed so as to intersect. That is, the first set of bit lines BL
The position where 1a and the BL1a bar intersect exists between the (2N) th memory cell and the (2N + 1) th memory cell in each column (N = 1, 2, ...), and the second position. The position where the pair of bit lines BL1b and BL1b bar intersect is present between the (2N-1) th memory cell and the (2N) th memory cell in each column.

Alternatively, in the bit lines of the first set and the bit lines of the second set, the intersecting positions may be reversed,
The intersecting interval may be changed. However, the length of the section where the bit line BL1a is adjacent to the bit line BL1b is substantially equal to the length of the section where the bit line BL1a is adjacent to the bit line BL1b bar, and the bit line BL1a bar is the bit line. BL1b
It is preferable that the length of a section adjacent to the bit line BL1a and the length of a section adjacent to the bit line BL1b bar are substantially equal to each other.

With the double cross structure, the coupling capacitance between the bit line BL1a and the bit line BL1b and the coupling capacitance between the bit line BL1a and the bit line BL1b bar are balanced.
Also, the bit line BL1a bar and the bit line BL1
The coupling capacitance between the bit line b and the bit line BL1a bar is balanced with the coupling capacitance between the bit line BL1a bar and the bit line BL1b bar. Further, the coupling capacitance between the bit line BL1a and the upper layer (or lower layer) wiring and the coupling capacitance between the bit line BL1a bar and the upper layer (or lower layer) wiring are balanced. Further, the coupling capacitance between the bit line BL1b and the upper layer (or lower layer) wiring and the coupling capacitance between the bit line BL1b bar and the upper layer (or lower layer) wiring are balanced.

Therefore, the crosstalks from the bit lines of each set to the upper or lower wirings cancel each other out. Also,
Considering the crosstalk from the upper or lower layer wiring to each set of bitlines and the crosstalk from one set of bitlines to the other set of bitlines, the crosstalk in bitline BL1a and bitline B
The crosstalk in the L1a bar is canceled by the sense amplifier SA1a which performs the differential amplification operation, and the crosstalk in the bit line BL1b and the bit line BL1b.
The crosstalk in the 1b bar is canceled at the input stage of the sense amplifier SA1b that performs a differential amplification operation.

[0032]

As described above, according to the present invention, the SR
In a semiconductor integrated circuit including an AM cell, crosstalk between bit lines is reduced, and further crosstalk between the bit lines and an upper layer or lower layer wiring is reduced, so that a malfunction in reading stored data is prevented. Can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram showing a partial configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a layout diagram showing a configuration of an SRAM cell included in a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a conventional semiconductor integrated circuit.

FIG. 4 is a diagram showing another example of a conventional semiconductor integrated circuit.

FIG. 5 is a diagram showing still another example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 to 4 memory cell 10 write circuit SA1a, SA1b sense amplifier BL1a, BL1a bar, BL1b, BL1b bar bit line WL1a, WL1b word line INV1 to INV2 inversion circuit QN11 to QN14 N channel transistor

Claims (4)

[Claims] 1. A plurality of memory cells arranged in a matrix, each memory cell having at least a first port and a second port, and a first memory cell of each column. A first set of bit lines connected to the ports, the first set of bit lines crossing each other at a first position between the memory cells of each column, and a second port of the memory cells of each column A second set of bit lines connected to each other and crossing each other at a second position between the memory cells in each column, and a first port of the memory cells in each column. A first word line for selecting one of the second ports of the second ports of the memory cells in each column, and a first set of bit lines Through the first port of memory cells in each column And a write circuit for writing data to the memory cell selected by the first word line and a second port of the memory cell in each column via the second set of bit lines, A semiconductor integrated circuit, comprising: a read circuit that differentially reads data stored in a memory cell selected by two word lines. 2. The first position is the second (2) in each row.
Exists between the (N) th memory cell and the (2N + 1) th memory cell (N = 1, 2, ...), and the second position is the (2N−1) th memory cell in each column. 2. The semiconductor integrated circuit according to claim 1, which is present between the memory cell and the (2N) th memory cell. 3. The first position is the second (2) in each row.
Exists between the (N-1) th memory cell and the (2N) th memory cell (N = 1, 2, ...), and the second position is the (2N) th memory cell in each column. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is present between the memory cell and the (2N + 1) th memory cell. 4. The first set of bit lines includes a first bit line and a second bit line, and the second set of bit lines is a third bit line and a fourth bit line.
And a length of a section in which the first bit line is adjacent to the third bit line and a length of a section in which the first bit line is adjacent to the fourth bit line. And the length of a section in which the second bit line is adjacent to the third bit line and the length of a section in which the second bit line is adjacent to the fourth bit line. 4. The semiconductor integrated circuit according to claim 1, wherein and are substantially equal to each other.