TW201448174A - Semiconductor device - Google Patents

Abstract

To make it possible to position part (n-type section (AAN)) of an assist amplifier inside a sense amplifier region (SAA). A semiconductor equipped with: first and second memory cell regions (MATA) aligned in the Y-direction; a sense amplifier region (SAA) including a plurality of sense amplifiers and formed between the first and second memory cell regions (MATA); a first wiring layer; first and second bit lines (BL0T, BL0B) extending in the Y-direction and containing a first wiring section formed as the first wiring layer in at least the sense amplifier region (SAA); and a first pad electrode extending in the X-direction and formed as the first wiring layer between the first wiring section of the first bit line (BL0T) and the first wiring section of the second bit line (BL0B).

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an auxiliary amplifier is connected to a local IO line pair.

A semiconductor device such as a DRAM (Dynamic Random Access Memory) is configured by having a plurality of bit line pairs. Each element pair is extended from the memory cell region to the sense amplifier region, and is connected to a plurality of memory cells in the memory cell region, and on the other hand, in the sense amplifier In the area, it is connected to the local IO line via a switch of each bit line. In the sense amplifier region, in addition to the column switches, a sense amplifier that amplifies a small potential difference occurring at a bit line pair, and a potential of a bit line that will constitute two bit line pairs are also provided. Equalize equalizers, etc. The sense amplifier and the equalizer are set at each bit line pair.

The local IO line pair is connected to the read/write amplifier via the main IO line pair. In the prior art semiconductor device, the amplifier located between the memory cell and the read/write amplifier has only a sense amplifier. Therefore, in order for the read data read from the memory cell to reach the read/write amplifier, it is necessary to have a certain degree of driving capability at the sense amplifier. However, with the increase in capacity and miniaturization of the semiconductor device, the interval between the bit lines and the area of the sense amplifier region are also reduced. Therefore, in recent years, it has become impossible to make the sense amplifier wide by the channel width. Large crystals are used to form. As a result, it has become difficult to allow the read data to reach the read/write amplifier only by the capability of the sense amplifier. Therefore, in recent years, there has been an increase in the potential for appearing at the local IO line pair. The case of the auxiliary amplifier is utilized. An example of such an auxiliary amplifier is disclosed in Patent Document 1.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2011-90750

Heretofore, the auxiliary amplifier has been disposed at the intersection of the sub-character region and the sense amplifier region as disclosed in Patent Document 1. However, since there is not enough margin in the intersection area, it is necessary to move the auxiliary amplifier from the intersection area to another place even if it can only move a part.

Here, the layer structure of the semiconductor device will be described. A semiconductor device having a diffusion layer/gate stacked in this order from the bottom The structure of the wiring layer, the tungsten layer, the first aluminum layer, the second aluminum layer, and the third aluminum layer. At the diffusion layer/gate wiring layer, a source/drain or gate electrode of a transistor constituting a sense amplifier or the like is disposed, and at the tungsten layer, a bit line pair is disposed, in the second The aluminum layer is provided with a local IO line pair, and at the third aluminum layer, a main IO line pair is disposed. Between the adjacent two layers, an interlayer insulating layer is provided, whereby the layers are insulated from each other. The connection between the layers is achieved by a contact portion including a via electrode penetrating the interlayer insulating layer.

If the setting area of the auxiliary amplifier is described later, at the diffusion layer/gate wiring layer of the sense amplifier region, since it is possible to obtain a slender space in the direction of the word line, it is conceivable if possible. It is desirable to move at least a portion of the auxiliary amplifier to this space. However, it is assumed that even if the auxiliary amplifier is disposed in this space, it is difficult to set the contact portion through the tungsten layer which is tightly inserted with the bit line, and therefore, in reality, it is to be sensed so far. It is considered difficult to set up an auxiliary amplifier in the amplifier area. Hereinafter, three points will be described as a reason for the specificity.

The first reason is that since it is necessary to provide through-hole electrodes constituting the contact portions at each layer, it is necessary to provide a cross-sectional area larger than that of the via-hole electrodes at each layer through which the contact portions pass. The area of the pad electrode is the reason. In other words, in order to provide the above-described general contact portion, it is necessary to secure a region in which the cross-sectional area of the via electrode is ensured in the tungsten layer, and it is necessary to secure a wider region for the pad electrode. It is more difficult to set up the contact through the tungsten layer.

The second reason is that the shape of the wiring in the tungsten layer having a very fine structure is important for the regularity in order to prevent the unevenness of the exposure of the photolithography process performed at the time of formation. For specific description, at the sense amplifier region, four pairs of local IO line pairs are arranged, and the plurality of bit line pairs are sequentially connected to the four from the end. The local IO line is opposite. Therefore, the circuit configuration in the sense amplifier region is repeated every four bit line pairs. Therefore, the shape of the wiring in the tungsten layer is also set to be the rule for every 4-bit line pair. Repetitive structure of sex. As long as the repetitive structure is maintained, the shim electrode which can be provided in the tungsten layer is limited to the size of the space of the 4-bit line pair in the direction of the word line. This also makes it more difficult to set up the contact through the tungsten layer.

The third reason is that the auxiliary amplifier has a small allowable amount of potential drop due to wiring impedance. If the potential drop due to the wiring impedance is large, the rate of change of the potential of the corresponding wiring is slow, and the operating speed of the semiconductor device is slow. Therefore, it is necessary to reduce the wiring impedance as much as possible. However, in order to reduce the wiring impedance, it is necessary to use a contact portion having a large sectional area. Therefore, it is more difficult to provide a contact portion through the tungsten layer.

Therefore, there is a need to overcome such difficulties and to be able to provide at least a portion of the auxiliary amplifier within the sense amplifier region.

A semiconductor device according to one aspect of the present invention, characterized by comprising: first and second memory cell regions arranged side by side in a first direction; and first and second memory cells formed in the first and second memory cells Between the regions, including a plurality of sense amplifier regions of the sense amplifier; and a first wiring layer; and extending in the first direction and including at least the first wiring layer at the sense amplifier region The first and second bit lines of the first wiring portion to be formed; and the first wiring portion of the first bit line and the first wiring portion of the second bit line as the first A first pad electrode extending in a second direction intersecting the first direction by the wiring layer.

A semiconductor device according to another aspect of the present invention, characterized by comprising: first and second memory cell regions arranged side by side in a first direction; and first and second memory cells formed in the first and second memory cells a sensing amplifier region including a plurality of sense amplifiers; and a semiconductor substrate including a first diffusion layer; and a first wiring layer formed over the semiconductor substrate; and a semiconductor substrate formed on the semiconductor substrate And an interlayer insulating film between the first wiring layer; and a first wiring portion extending toward the first direction and including at least a first wiring portion formed as the first wiring layer in the sense amplifier region; a second bit line; and a first pad electrode formed as the first wiring layer between the first wiring portion of the first bit line and the first wiring portion of the second bit line And the first and second via electrodes that respectively penetrate the interlayer insulating film and connect the first diffusion layer and the first pad electrode, and the first pad electrode includes the first and the second 1 and the first and second contact portions through which the second via electrodes are in contact with each other, wherein the first and second contact portions are electrically connected to each other and are arranged side by side in a second direction crossing the first direction Configuration.

According to the present invention, since the pad electrode extends in the second direction, that is, in a direction intersecting the direction in which the bit line extends, the wiring impedance through the first wiring layer can be formed. The small contact portion is such that at least a portion of the auxiliary amplifier can be provided in the sense amplifier region.

1‧‧‧Semiconductor device

AAA‧‧‧Auxiliary amplifier area

AAN‧‧‧n-type auxiliary amplifier

AANPD, SANPD‧‧‧ power components

AAP‧‧‧p-type of auxiliary amplifier

AL1‧‧‧1st aluminum layer

AL2‧‧‧2nd aluminum layer

AL3‧‧‧3rd aluminum layer

AMP‧‧Amplifier area

ARRAY‧‧‧ memory array

BL‧‧‧ bit line

BL0~BL3‧‧‧ bit line pair

BL0T~BL3T, BL0B~BL3B‧‧‧ bit line

CELL‧‧‧ memory cell

CROSSA‧‧‧Intersection

DL, D1~D8, D10, D11‧‧‧ diffusion layer

EQB, EQB ₀ ~ EQB ₃ , EQL‧‧‧ equalizer

G1~G5, G10‧‧‧ gate electrode

GL‧‧‧ gate wiring layer

IL1~IL5‧‧‧ interlayer insulation

LIO, LIO0T~LIO3T, LIO0B~LIO3B‧‧‧Local IO line

LIO0~LIO3‧‧‧Local IO line pair

MIO, MIO0T~MIO3T, MIO0B~MIO3B‧‧‧ main IO line

MIO0~MIO3‧‧‧Main IO line pair

LMS‧‧‧Transmission switch

MATA‧‧‧ memory cell area

P1~P3, P1 ₁ ~P1 ₈ , P2 ₁ ~P2 ₈ , P3 ₁ ~P3 ₈ , P4‧‧‧sap electrode

R_BUS‧‧‧Reading and writing bus

SAA‧‧‧Sense Amplifier Area

SAN, SAN ₀ ~ SAN ₃ ‧‧‧n-type of sense amplifier

SAP, SAP ₀ ~SAP ₃ ‧‧‧p-type of sense amplifier

SS‧‧‧Substrate

SWDA‧‧‧Sub Character Drive Area

T1~T6‧‧‧O crystal

TH0~TH3‧‧‧Through Hole Electrode

TL‧‧‧Tungsten layer

WL‧‧‧ character line

XDEC‧‧‧Down decoder area

YDEC‧‧‧ column decoder area

YS, YS _0T ~ YS _3T , YS _0B ~ YS _3B ‧‧‧ column switch

Fig. 1 is a plan view showing a semiconductor device 1 according to a preferred embodiment of the present invention.

FIG. 2 is an enlarged view of a region A shown in FIG. 1.

FIG. 3 is a block diagram showing the circuit configuration in the sense amplifier area SAA and the cross area CROSSA shown in FIG. 2.

[Fig. 4] A circuit diagram showing a more specific circuit configuration for a part of the circuit shown in Fig. 3.

Fig. 5 is a schematic view showing the layer constitution of the semiconductor device 1 shown in Fig. 1.

[Fig. 6] A diagram showing an example of the diffusion layer DL and the gate wiring layer GL shown in Fig. 5.

[Fig. 7] A diagram showing an example of the tungsten layer TL shown in Fig. 5.

[Fig. 8] A diagram showing an example of the first aluminum layer AL1 and the via electrode TH1 shown in Fig. 5.

[Fig. 9] A diagram showing an example of the second aluminum layer AL2 and the via electrode TH2 shown in Fig. 5.

[Fig. 10] A diagram showing an example of the third aluminum layer AL3 and the via electrode TH3 shown in Fig. 5.

[Fig. 11] For the portions of the bit line pairs BL0 to BL3 related to the four shown in Fig. 3, and for the diffusion layers arranged in the diffusion layer DL and disposed in the gate wiring layer GL The interconnection relationship of each gate electrode is shown in the figure.

Fig. 12 is a view showing a configuration of a circuit corresponding to Fig. 11.

FIG. 13 is a view showing the connection between the wirings of the upper layers and the diffusion layers D1 to D8 and the gate electrodes G1 to G5 arranged in the auxiliary amplifier region AAA shown in FIG.

[Fig. 14] A view showing an enlarged view of a region B (a portion of the tungsten layer TL which is connected to the pad electrodes P1 ₄ to P3 ₄ ) shown in Fig. 13 .

[Fig. 15] In the circuit diagram shown in Fig. 4 (the portion connected to the power supply element AANPD, the n-type portion AAN of the auxiliary amplifier, and the transfer switch LMS), the wiring impedance of the via electrode portion is additionally shown in the figure. .

Fig. 16 (a) is a diagram in which the diffusion layers D1, D3, and D7 and the gate electrodes G1 and G4 and the tungsten layer TL located directly above the portions are superimposed. (b) is for a quantity with a 4-bit pair In the semiconductor device (comparative example) of the tungsten layer TL having a reverse structure, the diffusion layer and the gate electrode and the tungsten layer TL are superimposed and depicted. (c) is a view showing a modification of a portion of the tungsten layer TL which is located directly above the diffusion layers D1, D3, and D7 and the gate electrodes G1 and G4.

[FIG. 17] is a case where the local IO line pair LIO0 is connected to the bit line pair BL0 after the read operation is performed by causing the column control signal YSW shown in FIG. 4 to be HIGH level. The simulation results of the local potential IO line pair LIO0 and the individual potential difference between the main IO line pair MIO0 are shown.

FIG. 18 is a diagram in which the diffusion layers D10 and D11 of the power supply element SANPD and the gate electrode G10 and the tungsten layer TL located directly above the position are superimposed.

[Fig. 19] In the circuit diagram shown in Fig. 4 (portion related to the power supply element SANPD), the wiring impedance of the via electrode portion is additionally shown in the figure.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

Fig. 1 is a plan view showing a semiconductor device 1 according to the present embodiment. As shown in the figure, the semiconductor device 1 is configured such that the address side peripheral region and the DQ side are disposed at both ends of the Y direction (bit line direction). The surrounding area, in the area between these, has a complex memory of the plural memory cells The memory array ARRAY is configured in a matrix.

In the peripheral area of the address side, a terminal for receiving various signals such as a command signal or an address signal from an external controller, and a circuit for generating a necessary internal signal based on the received signal are disposed. On the other hand, in the peripheral region of the DQ side, an input/output circuit and an input/output terminal for inputting and outputting data signals are disposed.

An amplifier region AMP for providing a read/write amplifier (not shown) is disposed between the adjacent memory arrays ARRAY in the Y direction. The read/write amplifier is connected to a bit line (not shown) in the memory array ARRAY by the main IO line MIO, and is input to the peripheral area of the DQ side by the read/write bus R_BUS. The output circuit is connected.

Between the amplifier area AMP and each of the corresponding two memory arrays ARRAY, a column decoder area YDEC for setting a column decoder (not shown) is provided. The column decoder is provided with a function for controlling the connection of the bit line and the main IO line MIO in response to the internal signal described above.

A row decoder region XDEC for providing a row decoder (not shown) is disposed between the adjacent memory arrays ARRAY in the X direction. The row decoder is connected to a word line (not shown) in the memory array ARRAY and has a function of controlling the active state of the word line in response to the internal signal described above.

Fig. 2 is an enlarged view of a region A shown in Fig. 1. As shown in the figure, the memory array ARRAY is equipped with The memory cell regions MATA having a plurality of complex memory cells are arranged in a matrix form.

Between the memory cell regions MATA adjacent to each other in the Y direction, a sense amplifier region SAA for providing a plurality of sense amplifiers (not shown) is disposed. The sense amplifier is connected to the memory cell in the memory cell region MATA via the bit line BL, and has a function of amplifying the potential of the bit line BL. In addition, in the sense amplifier area SAA, a part of the local IO line LIO and the auxiliary amplifier (a portion formed by an n-channel type transistor) is also provided, but the details are I will explain later.

A sub-character driver area SWDA for providing a sub-word driver (not shown) is disposed between the memory cell regions MATA adjacent to each other in the X direction. The sub-character driver is provided at each word line and has a function of controlling the active state of the word line in response to control from the above-described row decoder.

The intersection between the sense amplifier area SAA side by side in the X direction and the side character drive area SWDA side by side in the Y direction is the intersection area CROSSA. In the crossover region CROSSA, another portion of the auxiliary amplifier (a portion constituted by a p-channel type transistor) or the like is disposed.

Referring to Fig. 1 and Fig. 2, the functions of the respective configurations described above will be briefly described by taking a reading operation as an example. First, if an action command and a row address are input from a controller not shown, the row decoder in the row decoder region XDEC and the subword in the sub-character driver region SWDA are used. The meta-driver, the character line system corresponding to the input row address is activated. At this point of time, at each bit line BL, there is a potential corresponding to the memory content of the memory cell corresponding to the word line. The sense amplifier functions to amplify the potential appearing at the bit line BL as such.

Then, if a read command and a column address are input from the controller, the column decoder in the column decoder area YDEC connects the bit line BL represented by the column address with the local IO line LIO, and The local IO line LIO is connected to the main IO line MIO. The auxiliary amplifier functions to amplify the potential appearing at the local IO line LIO by this connection, whereby the potential of the bit line BL is reflected at the main IO line MIO. In this manner, the potential appearing at the main IO line MIO is amplified by the read/write amplifier in the amplifier area AMP, and then supplied to the read/write bus R_BUS via the DQ side peripheral area. The input and output circuits and the input and output terminals are output to the outside.

Next, the circuit configuration in the sense amplifier area SAA and the cross area CROSSA will be described in detail.

FIG. 3 is a block diagram showing the circuit configuration in the sense amplifier area SAA and the cross area CROSSA. Further, Fig. 4 is a circuit diagram showing a more specific circuit configuration for a part of the circuit shown in Fig. 3. Further, in the semiconductor device 1, the main IO line, the local IO line, and the bit line are transmitted in a manner of transmitting signals in two groups, that is, two in a complementary relationship. In the following way, the line number is similar to the "main IO line pair", and the word "right" is added at the end of the word. In addition, when it is necessary to distinguish between one of the "right" and the other, "T" and "B" are added to the end of each component symbol for distinction.

First, as shown in FIG. 3, in one sense amplifier area SAA, a plurality of bit line pairs are formed. However, in FIG. 3, only the bit line pairs BL0 to BL3 (the first to fourth bit line pairs) of four of them are displayed. Further, in one of the sense amplifier regions SAA, four bit pairs of main IO lines, MIO0 to MIO3, and four local IO lines, LIO0 to LIO3, are arranged corresponding to the plurality of bit line pairs. (1st to 4th partial IO pair). If the specific relationship is specified for the corresponding relationship, the local IO line pair LIO0 and the main IO line pair MIO0 correspond to the bit line pair BL0. For example, if the read operation is taken as an example, the bit line pair BL0 appears. The potential is output as read data to the read/write amplifier described above via the corresponding local IO line pair LIO0 and the main IO line pair MIO0. The same is true for the bit line pair BL1~BL3.

The bit lines BL0T to BL3T, as shown in FIG. 3, generally extend from the memory cell region MATA located at one side of the Y direction of the sense amplifier region SAA, and cover the sense amplifier region SAA. Settings. On the other hand, the bit lines BL0B to BL3B are from the memory cell region MATA located at the other side in the Y direction of the sense amplifier region SAA, and cover the sense amplifier region SAA. Make an extension setting. At each of the bit lines BL0T to BL3T and BL0B to BL3B, as shown in FIG. 3, a memory cell CELL composed of a plasmonic crystal and a cell capacitor is connected. Each of the cell crystals is connected to the word line WL.

The circuit disposed in the sense amplifier area SAA is as follows. First, at each bit line pair, the sense amplifier and equalizer EQB are configured. The sense amplifier is composed of a portion (p-type portion) SAP composed of a p-channel type transistor and a portion (n-type portion) SAN formed by an n-channel type transistor. Similarly, the auxiliary amplifier is composed of a portion (p-type portion) AAP composed of a p-channel type transistor and a portion (n-type portion) AAN composed of an n-channel type transistor. In the sense amplifier area SAA, the n-type portion AAN among the portions is disposed at each local IO line pair. Further, a column switch YS is disposed between each of the bit lines and the corresponding local IO line, and a transfer switch LMS is disposed between each of the local IO lines and the corresponding main IO line.

Within the crossover region CROSSA, at each local IO line pair, a p-type AAP and an equalizer EQL in the auxiliary amplifier are arranged.

Referring to Fig. 4, the specific configuration of each of the above circuits will be described. Hereinafter, the configuration of the bit line pair BL0 will be described with reference to the description of FIG. 4, but the configuration of the bit line pair BL1 to BL3 is also the same.

The n-type SAN of the sense amplifier is made by It is composed of two n-channel MOS transistors that are fork-coupled. One of the drain electrodes and the gate electrode are connected to the bit line BL0B and the bit line BL0T, respectively. On the other hand, the other one of the drain and the gate electrode are connected to the bit line BL0T and the bit line BL0B, respectively. At a source of each of the two n-channel MOS transistors, a constant voltage V2 equal to the ground potential VSS is supplied from a voltage generating circuit (not shown) via the power supply element SANPD (not shown). .

The power supply element SANPD is generally constituted by an n-channel type MOS transistor T6 as shown in FIG. 4, and is disposed in the sense amplifier area SAA. At the gate electrode G10 of the transistor T6, a control signal SIG_5 which is one of the above internal signals is supplied. Further, a diffusion layer D10 which is supplied with a constant voltage V_2 and a drain is formed in the diffusion layer D11 constituting the source of the transistor T6, and is commonly connected to two of the n-type portions SAN constituting the sense amplifier. The respective sources of the n-channel MOS transistors.

The p-type portion SAP of the sense amplifier is constituted by two p-channel MOS transistors that are cross-coupled. One of the drain electrodes and the gate electrode are connected to the bit line BL0B and the bit line BL0T, respectively. On the other hand, the other one of the drain and the gate electrode are connected to the bit line BL0T and the bit line BL0B, respectively. The respective voltage sources of the two p-channel MOS transistors are supplied with a constant voltage V_1 from a voltage generating circuit (not shown). The constant voltage V_1 is the power supply voltage VDD supplied from the outside. The smaller voltage, more specifically, the power supply voltage VARY which is the operating voltage of the memory cell array is used as the constant voltage V_1. Further, although not shown, a power supply element similar to the above-described power supply element SANPD is provided in the supply path of the constant voltage V_1, and the gate electrode of the power supply element is also supplied with The above internal signal. This power supply component is different from the power supply component SANPD and is disposed in the crossover area CROSSA.

The equalizer EQB is an n-channel type MOS transistor in which one of the source/drain electrodes is connected to the bit line BL0B and the other is connected to the bit line BL0T, and is connected in series to the bit line. Two n-channel MOS transistors between BL0B and bit line BL0T are formed. At a connection point of the latter two n-channel MOS transistors, a constant voltage VBLP is supplied from a voltage generating circuit (not shown). The constant voltage VBLP is equal to one half of the constant voltage V_1 (= (V_1 - V_2)/2). Further, at each of the gate electrodes of the three n-channel MOS transistors constituting the equalizer EQB, the control signal SIG_1 which is one of the internal signals described above is commonly supplied.

The column switch YS is constructed by an n-channel type MOS transistor connected between the corresponding bit line and the corresponding local IO line. At the gate electrode of the n-channel type MOS transistor, the column control signal YSW is supplied from the above-described column decoder.

The n-type portion AAN of the auxiliary amplifier is constituted by two n-channel type MOS transistors T1 and T2 which are cross-coupled. The diffusion layer D1 constituting the drain of the transistor T1 is directly connected to the local IO line LIO0B, and is also connected to the main IO line MIO0B via the n-channel type MOS transistor T4. The gate electrode G1 of the transistor T1 is connected to the local IO line LIO0T. The diffusion layer D2 constituting the drain of the transistor T2 is directly connected to the local IO line LIO0T, and is also connected to the main IO line MIO0T via the n-channel type MOS transistor T5. The gate electrode G2 of the transistor T2 is connected to the local IO line LIO0B. The diffusion layers D3 and D4 constituting the respective source of the transistors T1 and T2 are connected to each other by the node n shown in the figure.

The node n is connected to the power supply wiring to which the ground potential VSS is supplied via the power supply element AANPD. The power supply element AANPD is generally constituted by an n-channel type MOS transistor T3 as shown in FIG. The diffusion layer D5 constituting the drain of the transistor T3 is connected to the node n, and the diffusion layer D6 constituting the source is connected to the power supply wiring to which the ground potential VSS is supplied. At the gate electrode G3 of the transistor T3, a control signal SIG_4 which is one of the above internal signals is supplied.

The transistors T4 and T5 constitute a transfer switch LMS, respectively. One of the source/drain of the transistor T4 is formed by a diffusion layer D1 common to the transistor T1. Further, the other diffusion layer D7 constituting the source/drain of the transistor T4 is connected to the main IO line MIO0B. Similarly, one of the source/drain of the transistor T5 is formed by the diffusion layer D2 common to the transistor T2. Also, constitute electricity The other diffusion layer D8 of the source/drain of the crystal T5 is connected to the main IO line MIO0T. At the gate electrodes G4 and G5 of the transistors T4 and T5, the control signal S1G_3 is supplied in common from the above-described decoder.

The p-type AAP of the auxiliary amplifier is connected to the local IO line pair LIO0 instead of the bit line pair BL0, and is supplied with a constant voltage V_3 instead of the constant voltage V_1, and is provided with a sense amplifier. The p-type AAP has the same configuration. However, the constant voltage V_3 is a voltage equal to the constant voltage V_1. Further, the equalizer EQL is connected to the local IO line pair LIO0 instead of the bit line pair BL0, and is supplied with the control signal SIG_2 instead of the control signal SIG_1, and has the same configuration as the equalizer EQB. . The control signal SIG_2 is also the same as the control signal SIG_1 and the like, and is one of the above internal signals.

The operation of the above configuration will be described by taking a reading operation as an example. In the following description, the case where the data is read from the memory cell corresponding to the bit line pair BL0 shown in FIG. 4 will be described as an example, but for the bit line corresponding to the other bits. The same is true for the case where the data is read from the memory cells.

First, in the initial state, the control signals SIG_1 and SIG_2 are all at the HIGH level, and the control signals SIG_3 to SIG_5 and the column control signal YSW are both LOW levels. Since the control signals SIG_1 and SIG_2 are at the HIGH level, the respective electro-ecological systems in the equalizers EQB and EQL are in an ON state, and therefore, the bit lines are The potentials of BL0B, BL0T, and local IO lines LIO0B and LIO0B are equal to the constant voltage VBLP (precharge state). Further, since the control signal SIG_3 and the column control signal YSW are at the LOW level, the main IO line pair MIO0, the local IO line pair LIO0, and the bit line pair BL0 are in a state of being separated from each other. Further, since the control signals SIG_4 and SIG_5 are at the LOW level, the supply voltages of the n-type portion SAN of the sense amplifier and the n-type portion AAN of the auxiliary amplifier are blocked, and these systems are set to The state of no action. Similarly, in the p-type portion SAP of the sense amplifier and the p-type portion AAP of the auxiliary amplifier, the supply of the operating voltage is blocked, and the operation is not performed.

If an operation command and a row address are input to the controller (not shown), the control signal SIG_1 is set to the LOW level, and the equalizer EQB stops operating. Next, the word line WL corresponding to the input row address is activated by the sub-character driver (not shown) in the sub-word driver area SWDA. Thereby, in the potential difference between the bit line pair BL0, the information memorized in the memory cell corresponding to the activated word line WL is reflected. Further, next, the control signal SIG_5 is set to the HIGH level, and the n-type portion SAN of the sense amplifier starts operating. The p-type portion SAP of the sense amplifier is also activated in the same manner. Thereby, the potential difference between the bit line pair BL0 is expanded to a constant voltage V_1. In other words, the potential of one of the bit lines BL0T and BL0B is constant voltage V_1, and the other potential is constant voltage V_2 (= ground potential VSS).

Next, if a read command and a column address are input from the controller, the control signal SIG_2 is set to the LOW level, so that the equalizer EQL stops operating. Next, the column control signal YSW corresponding to the bit line pair BL0 is set to the HIGH level. Therefore, the bit line pair BL0 and the local IO line pair LIO0 are connected. Thereby, in the potential difference between the local IO line pair LIO0, the potential difference of the bit line pair BL0 is reflected. Next, the control signal SIG_4 is set to the HIGH level, and the n-type AAN of the auxiliary amplifier starts operating. The p-type AAP of the auxiliary amplifier is also activated in the same manner. Thereby, the potential difference between the local IO line pair LIO0 is expanded to a constant voltage V_3. In other words, the potential of one of the local IO lines LIO0T and LIO0B is the constant voltage V_3, and the other potential is the ground potential VSS.

Thereafter, the control signal SIG_3 is set to the HIGH level, so the local IO line pair LIO0 and the main IO line pair MIO0 are connected. Thereby, the potential difference between the bit line pair BL0 is also reflected in the potential difference between the main IO line pair MIO0. Thereafter, as described above, the read data is output to the outside via the read/write amplifier, the read/write bus R_BUS, the input/output circuits in the peripheral area of the DQ side, and the input/output terminals.

Next, the physical configuration of the sense amplifier area SAA will be described in detail.

First, the layer configuration of the semiconductor device 1 will be described. FIG. 5 is a schematic view showing a layer configuration of the semiconductor device 1. As shown in the figure, the semiconductor device 1 is provided with a laminated structure in which a diffusion layer DL and a gate wiring layer GL are formed on the surface of the substrate SS, and On the upper side, the tungsten layer TL (first wiring layer), the first aluminum layer AL1, the second aluminum layer AL2 (second wiring layer), and the third aluminum layer AL3 are sequentially laminated from the side close to the surface of the substrate SS. Each layer is insulated from each other by interlayer insulating layers IL1 to IL4. Further, the upper surface of the third aluminum layer AL3 of the uppermost layer is covered by the interlayer insulating layer IL5 for protection. A thin gate insulating film GI is formed between the gate wiring layer GL and the surface of the substrate SS.

The diffusion layer DL, the gate wiring layer GL, and the tungsten layer TL are connected to each other only at a necessary place by passing through the via electrode TH0 of the interlayer insulating layer IL1. Similarly, the tungsten layer TL and the first aluminum layer AL1 are connected to each other only at a necessary place by passing through the via electrode TH1 of the interlayer insulating layer IL2. Further, the first aluminum layer AL1 and the second aluminum layer AL2 are connected to each other only at a necessary place by passing through the via electrode TH2 of the interlayer insulating layer IL3. Further, the second aluminum layer AL2 and the third aluminum layer AL3 are connected to each other only at a necessary place by passing through the via electrode TH3 of the interlayer insulating layer IL4.

6 to 10 are diagrams showing a part of the sense amplifier area SAA (portion of the intersection area CROSSA at the one end side of the X direction), and an example of the above layers is shown. Specifically, FIG. 6 shows the diffusion layer DL and the gate wiring layer GL, FIG. 7 shows the tungsten layer TL, and FIG. 8 shows the first aluminum layer AL1 and the via electrode TH1. Figure 9, is For the second aluminum layer AL2 and the via electrode TH2, FIG. 10 shows the third aluminum layer AL3 and the via electrode TH3.

As shown in FIG. 6, generally, a plurality of diffusion layers and gate electrodes which are elongated in the X direction are disposed at a central portion of the sense amplifier region SAA in the Y direction, and are formed by the above. The power supply elements SANPD, AANPD, the n-type portion AAN of the auxiliary amplifier, and the transfer switch LMS shown in FIG. Hereinafter, a region in which such a configuration is arranged is generally referred to as an auxiliary amplifier region AAA (third region) as shown in FIG.

The bit line pair is disposed at the tungsten layer TL shown in FIG. The wirings shown in FIG. 7 are specifically equivalent to those of the wiring, which will be described in detail later, but for the tungsten layer TL and other wiring layers shown in FIG. 7 (the first aluminum) Comparing the layers AL1 to the third aluminum layer AL3), it can be understood that the wiring layer of the tungsten layer TL is extremely fine compared to the wiring of the other wiring layers. For this reason, as described above, in order to prevent the unevenness of the exposure of the light lithography which is performed at the time of formation, the regularity of the wiring is important in the tungsten layer TL compared to the other wiring layers. In the semiconductor device 1, the arrangement of the bit lines is matched to the number 4 of the local IO line pairs, and the reverse structure of the 4-bit line pair and the 4-bit line pair is basically configured. Therefore, to ensure the regularity of the wiring.

However, the details will be described later, but in the vicinity of the auxiliary amplifier region AAA, the structure of the tungsten layer TL is a reverse structure of every 8-bit line pair and 8-bit line pair. This is because, like Figure 7 Generally shown in the tungsten layer TL at a position above the auxiliary amplifier region AAA, a pad electrode for connecting the diffusion layer in the auxiliary amplifier region AAA and the wiring of the gate electrode and the upper layer is disposed. The reason of P1~P3. The pad electrodes P1 to P3 are arranged by a repeating structure of every 8-bit line pair and 8-bit line pair. Therefore, in the vicinity of the pad electrodes P1 to P3, the above-mentioned repeated structure of each of the 4-bit line pair and the 4-bit line pair collapses, and as a whole, it is an 8-bit line pair and an 8-bit line pair. Repeated construction. Although it is a repeating structure for every 8-bit pair and 8-bit pair, since it is still a repetitive structure, the regularity of wiring is still ensured.

As shown in FIG. 9, in general, the local IO line pair LIO0~LIO3 is disposed at the second aluminum layer AL2. Further, the wirings of the supply control signals SIG3 and SIG4 shown in FIG. 4 and the node n shown in FIG. 4 are also disposed at the second aluminum layer AL2. Further, as shown in FIG. 10, the main IO line pair MIO0 to MIO3 and the power supply line to which the ground potential VSS is supplied are disposed in the third aluminum layer AL3. Such wiring is connected to the power supply element AANPD in the auxiliary amplifier area AAA, the n-type portion AAN of the auxiliary amplifier, and the transfer switch LMS. Therefore, in the semiconductor device 1, it is necessary to perform this connection by the connection portion penetrating the tungsten layer TL. Although the detailed description is omitted, the same is true for the power supply element SANPD. The pad electrodes P1 to P3 described above are provided to achieve such connections.

Hereinafter, first, first for the sense amplifier area SAA The configuration of the circuit disposed at a region other than the auxiliary amplifier region AAA will be described in detail, and then the configuration of the circuit associated with the auxiliary amplifier region AAA will be described in detail.

FIG. 11 is for a portion related to the bit line pairs BL0 to BL3 of the four shown in FIG. 3, and for each of the diffusion layers disposed in the diffusion layer DL and disposed in the gate wiring layer GL. The interconnection relationship of each of the gate electrodes is shown in the figure. Further, Fig. 12 is a view showing the configuration of the circuit corresponding to Fig. 11. In addition, in the following description, the character _{0 is} attached to the end of the component symbol as in the configuration corresponding to, for example, the bit line pair BL0, and is at the end corresponding to the component symbol at the end corresponding to, for example, the bit line BL0T. The additional text _{0T is} generally used to clearly mark the corresponding bit line pair or bit line at the end of the component symbol.

As shown in FIG. 11 and FIG. 12, generally, the circuits connected to the bit line pair BL0 to BL3 are from one end side of the Y direction, and the column switches YS _0T to YS _3T and the p type of the sense amplifier. SAP ₁ , SAP ₃ , equalizer EQB ₁ , EQB ₃ , sense amplifier n-type SAN ₁ , SAN ₃ , sense amplifier n-type SAN ₀ , SAN ₂ , equalizer EQB ₀ , EQB ₂ , sense The order of the p-type portions SAP ₀ and SAP ₂ and the column switches YS _0B to YS _3B of the amplifier is arranged side by side. The auxiliary amplifier area AAA is secured between the n-type portions SAN ₁ , SAN _{3 of the} sense amplifier and the n-type portions SAN ₀ , SAN _{2 of the} sense amplifier. Here, the column switches YS _0T to YS _3T , the p-type portions SAP ₁ and SAP _{3 of the} sense amplifier, the equalizers EQB ₁ and EQB ₃ , and the n-type portions SAN ₁ and SAN ₃ of the sense amplifier are arranged. It is the first region of the sense amplifier region of the present invention. Similarly, the column switches YS _0T ~ YS _3T , the p-type portions SAP ₁ , SAP _{3 of the} sense amplifier, the equalizers EQB ₁ , EQB ₃ , the n-type portions of the sense amplifiers SAN ₁ , SAN ₃ , It is the third region of the sense amplifier region of the present invention.

The electrical connections of the above components are as shown in Fig. 12. The details of the respective circuits shown in FIG. 12 are as described with reference to FIG. 3 and FIG. 4, and thus the description thereof will be omitted. In FIG. 11, the wirings disposed at the tungsten layer TL among the wirings that realize this connection are shown as solid lines, and are disposed on other wiring layers (the first aluminum layer AL1 to the third aluminum). The wiring at layer AL3) is shown by a broken line. As can be understood from this, generally, only four of the bit lines BL1B, BL0T, BL3B, and BL2T are formed by the tungsten layer TL and the region directly above the auxiliary amplifier region AAA. Therefore, when the pad electrodes P1 to P3 described above are provided in the tungsten layer TL, it is necessary to avoid the bit lines BL1B, BL0T, BL3B, and BL2T.

Hereinafter, the connection between the diffusion layer in the auxiliary amplifier region AAA and the gate electrodes and the wirings including the layers above the pad electrodes P1 to P3 in the tungsten layer TL will be specifically described. In the following description, first, attention is paid to the power supply element AANPD, the n-type portion AAN of the auxiliary amplifier, and the transfer switch LMS. Hereinafter, the power supply element SANPD will be described.

Fig. 13 is a view showing the connection between the wirings of the upper layers and the diffusion electrodes D1 to D8 and the gate electrodes G1 to G5 arranged in the auxiliary amplifier region AAA. In addition, the diffusion layer D1 to D8 and the gate electrodes G1 to G5 are the diffusion layers and the gate electrodes constituting the power supply element AANPD, the n-type portion AAN of the auxiliary amplifier, and the transfer switch LMS, as described with reference to FIG.

As shown in FIG. 13, generally, eight pad electrodes P1 to P3 (first to third pad electrodes) are disposed above the diffusion layers D1 to D8 and the gate electrodes G1 to G5. In the following description, the numbering is added by subscripting the symbol at the symbol of the element as generally shown in Fig. 13, and the distinction is made for this. The number is from the left side of the drawing, and is set to 1~8 in order.

Further, Fig. 14 is an enlarged view showing a region B (a portion of the tungsten layer TL which is connected to the pad electrodes P1 ₄ to P3 ₄ ) shown in Fig. 13 . As shown in the figure, in the region where the pad electrodes P1 ₄ to P3 _{4 are} disposed (the region above the auxiliary amplifier region AAA shown in FIG. 6 and the like), there are two bits each. The lines BL1B, BL0T, BL3B, and BL2T and the pad electrodes P1 ₄ to P3 ₄ are disposed between the lines BL1B, BL0T, BL3B, and BL2T. More specifically, in the region where the pad electrodes P1 ₄ to P3 ₄ are disposed, the bit lines BL1B, BL0T, BL3B, BL2T, BL1B, BL0T, BL3B, and the bit lines are sequentially arranged from the left side of the drawing. BL2T, the pad electrodes P1 ₄ to P3 ₄ are disposed between the bit line BL1B of the second strip from the left side of the drawing and the bit line BL0T of the second strip from the left side of the drawing. . With the arrangement of the pad electrodes P1 ₄ to P3 ₄ , the bit lines are arranged in a meandering manner so as to avoid the pad electrodes P1 ₄ to P3 ₄ . Further, in the figure, although only the region B is shown, as in the above, the tungsten layer TL is a structure in which every octet line pair and octet line pair are reversed, and other regions are The same configuration as that shown in Fig. 14 is also provided.

Returning to Fig. 13, the diffusion layer D1 is connected to the two pad electrodes P1 ₁ and P1 ₂ . The pad electrodes P1 ₁ and P1 ₂ are via the first aluminum layer AL1 and the second aluminum layer AL2, and are connected to the local IO line LIO0B at the third aluminum layer AL3 (the first partial IO line One of the partial IO lines) is connected. Although not shown, the local IO line LIO0B is further connected to the local IO line LIO0B (FIG. 9) of the second aluminum layer AL2 via the via electrode TH3 (FIG. 5). Thereby, the diffusion layer D1 is connected to the local IO line LIO0B of the second aluminum layer AL2.

The diffusion layer D2 is connected to the two pad electrodes P1 ₄ and P1 ₅ . The pad electrodes P1 ₄ and P1 ₅ are via the first aluminum layer AL1 and the second aluminum layer AL2, and are connected to the local IO line LIO0T at the third aluminum layer AL3 (the first partial IO line The other part of the IO line) is connected. Although not shown, the local IO line LIO0T is further connected to the local IO line LIO0T (FIG. 9) of the second aluminum layer AL2 via the via electrode TH3 (FIG. 5). Thereby, the diffusion layer D2 is connected to the local IO line LIO0T of the second aluminum layer AL2.

The diffusion layer D3 is connected to the two pad electrodes P2 ₁ and P2 ₂ , and the pad electrodes P2 ₁ and P2 ₂ are disposed on the second aluminum layer via the first aluminum layer AL1. The node n (the first intermediate wiring) at AL2 is connected. Further, the diffusion layer D4 is connected to the two pad electrodes P2 ₄ and P2 ₅ , and the pad electrodes P2 ₄ and P2 _{5 are} also provided via the first aluminum layer AL1. 2 The node n at the aluminum layer AL2 is connected. Further, diffusion layers D5, as the train is connected to the electrode pad P1 _7, this electrode pad P1 _7, also based ALl through the first aluminum layer, is provided at the node AL2 n of the second aluminum layer for the connection. Therefore, the diffusion layers D3 to D5 are connected to each other via the node n.

The diffusion layer D6 is connected to the two pad electrodes P2 ₇ and P3 ₇ . The pad electrodes P2 ₇ and P3 ₇ are connected to the power supply wiring to which the ground potential VSS is supplied, which is provided in the third aluminum layer AL3 via the first aluminum layer AL1 and the second aluminum layer AL2. Thereby, the ground potential VSS is supplied to the diffusion layer D6.

The diffusion layer D7 is connected to the two pad electrodes P3 ₁ and P3 ₂ . The pad electrodes P3 ₁ and P3 ₂ are connected to the main IO line MIO0B (the first main IO line) provided in the third aluminum layer AL3 via the first aluminum layer AL1 and the second aluminum layer AL2. One of the main IO lines) is connected. Thereby, the diffusion layer D7 is connected to the main IO line MIO0B of the third aluminum layer AL3.

The diffusion layer D8 is connected to the two pad electrodes P3 ₄ and P3 ₅ . The pad electrodes P3 ₄ and P3 ₅ are connected to the main IO line MIO0T (the first main IO line) provided in the third aluminum layer AL3 via the first aluminum layer AL1 and the second aluminum layer AL2. The main IO line of the other side is connected. Thereby, the diffusion layer D8 is connected to the main IO line MIO0T of the third aluminum layer AL3.

The gate electrode G1 is connected to the pad electrode P2 ₃ . The pad electrode P2 ₃ is connected to the local IO line LIO0T provided at the third aluminum layer AL3 via the first aluminum layer AL1 and the second aluminum layer AL2. This local IO line LIO0T is the same as the one to which the diffusion layer D2 is connected. Further, the gate electrode G1 and the diffusion layer D2 are also connected to each other by wiring in the second aluminum layer AL2.

The gate electrode G2 is connected to the pad electrode P1 ₃ . The pad electrode P1 ₃ is connected to the local IO line LIO0B provided at the third aluminum layer AL3 via the first aluminum layer AL1 and the second aluminum layer AL2. This local IO line LIO0B is the same as the one to which the diffusion layer D1 is connected. Further, the gate electrode G2 and the diffusion layer D1 are also connected to each other by wiring in the second aluminum layer AL2.

Gate electrode G3, and the system is connected to the pad electrode for P2 _8. The pad electrode P2 _{8 is} connected to the transmission wiring (first signal wiring) of the control signal SIG_4 provided in the second aluminum layer AL2 via the first aluminum layer AL1. Thereby, the control signal SIG_4 is supplied to the gate electrode G3.

The gate electrode G4 and the gate electrode G5 are connected to each other in the gate wiring layer GL. Also, some of this connecting portion, the connecting lines are as electrode pad P3 _3, this electrode pad P3 _3, line 1 via the first aluminum layer ALl, and is provided with SIG_3 control signal at the second aluminum layer AL2 of the The transmission wiring (the second signal wiring) is connected. Thereby, the control signal SIG_3 is commonly supplied to the gate electrodes G4 and G5.

With the above general wiring structure, the circuit configuration shown in FIG. 4 is realized in connection with the power supply element AANPD, the n-type portion AAN of the auxiliary amplifier, and the transfer switch LMS.

Figure 15 is an explanatory view showing the wiring impedance of the via electrode portion in addition to the circuit diagram shown in Fig. 4 (the portion connected to the power supply element AANPD, the n-type portion AAN of the auxiliary amplifier, and the transfer switch LMS). Figure. However, since the wiring impedance of the via electrode associated with the control signal hardly affects the operating speed of the semiconductor device, in this figure, only the wiring impedance of the other portion is shown.

In general, the portion of the wiring that is formed by the via electrode has a high wiring impedance as compared with the planar portion. The wiring impedance of the via electrode is larger as the cross-sectional area of the via electrode (the total cross-sectional area of the plurality of via electrodes is used in a place where a plurality of via electrodes are used) Therefore, from the viewpoint of increasing the operating speed of the semiconductor device, it is desirable to increase the cross-sectional area as much as possible. However, it is difficult for the through-hole electrode TH0 (FIG. 5) in which the tungsten layer TL in which the wiring is densely popped and the diffusion place DL/gate wiring layer GL to be connected to each other is limited. The cross-sectional area thereof is increased, and therefore, as in the above-described general case, in the prior art semiconductor device, it is considered difficult to set the auxiliary amplifier in the sense amplifier area SAA. In the semiconductor device according to the present embodiment, the tungsten layer TL is formed to have a repeating structure for every octet line pair and every octet line pair, and the pad electrode is extended toward the lower diffusion layer. The direction is extended, whereby the cross-sectional area of the via electrode TH0 between the pad electrode and the diffusion layer of the lower layer can be increased. As a result, as in the above, the SAA is realized in the sense amplifier region. Inside The target of the n-type portion AAN or the like of the auxiliary amplifier is set. The details will be described below.

Fig. 16 (a) shows the diffusion layer D1 (first diffusion layer), D3 (second diffusion layer), D7 (third diffusion layer), and gate electrodes G1, G4 at positions directly above The tungsten layer TL is shown in an overlapping pattern. Here, for example, the bit line BL1B of FIG. 16(a) corresponds to the first wiring portion of the first bit line of the present invention, and the bit line BL0T corresponds to the second bit line of the present invention. The first wiring portion and the spacer wirings P1 to P3 correspond to the first to third spacer electrodes. On the other hand, FIG. 16(b) is a semiconductor device (comparative example) having a tungsten layer TL having a repeating structure of a 4-bit line pair, and the diffusion layer and the diffusion layer are the same as in FIG. 16(a). The gate electrode and the tungsten layer TL are shown in an overlapping manner. In FIG. 16(b), it is assumed that the n-type portion AAN of the auxiliary amplifier is disposed in the sense amplifier region SAA similarly to the semiconductor device 1 of the present embodiment, and is the same as FIG. 16(a). The diffusion layers D1, D3, and D7 and the gate electrodes G1 and G4 are shown. Although the detailed description is omitted, when the tungsten layer TL is a reverse structure of a 4-bit line pair, the pad electrode P4 at the tungsten layer TL can be arranged as shown in FIG. 16(b). Generally shown to be a shape that is elongated in the Y direction.

As shown in FIG. 16(a), in the semiconductor device 1 according to the present embodiment, any of the diffusion layers D1, D3, and D7 can be in the configuration of an 8-bit pair. The via electrode TH0 is disposed in two places. In general, the diffusion layers D1, D3, and D7 are Each of the four via electrodes TH0 is connected to the corresponding pad electrode. On the other hand, in the comparative example shown in FIG. 16(b), the number of via electrodes TH0 that can be arranged in the structure of the 8-bit line pair is in the diffusion layers D1, D3, and D7. It becomes one each. As a whole, the diffusion layers D1, D3, and D7 are connected to the corresponding pad electrodes via only the two via electrodes TH0. Further, as shown in Fig. 16(b) and Fig. 16(a), it is understood that the cross-sectional area of one of the via electrodes TH0 for the diffusion layers D3 and D7 is compared with that of Fig. 16 (a). The example is also getting smaller. From the above, it is apparent that the diffusion layers D1, D3, and D7 in the semiconductor device 1 according to the embodiment of the present invention can be said to be the wiring impedance of the via electrode portion as compared with the comparative example. The wiring impedance shown in Fig. 15 is lowered. Although not shown, this matter is also the same for the other diffusion layers D2, D4 to D6, and D8.

Figure 17 is a partial IO after the local IO line pair LIO0 is connected to the bit line pair BL0 by causing the column control signal YSW (Fig. 4) to be HIGH level during the read operation. The simulation results of the pair of LIO0 and the individual potential difference between the main IO line and MIO0 are shown. In the figure, the vertical axis is set to time t, the horizontal axis is set to voltage [mV], and the time point at which the column control signal YSW is at the HIGH level is taken as the origin of the horizontal axis. Further, in the figure, an example of the semiconductor device 1 shown in Fig. 16 (a) and the semiconductor device shown in Fig. 16 (b) are shown.

In general, as the speed of action for reading operations One of the evaluation indexes is the time from when the column control signal YSVV changes to the HIGH level until the potential difference between the main IO line pairs reaches 150 mV. Therefore, if the measurement is performed for the time in the simulation result of FIG. 17, it is 1.96 ns in the example caused by the semiconductor device 1 shown in FIG. 16(a), whereas In the example of the semiconductor device shown in Fig. 16 (b), it is 2.92 ns. This department represents the former performing the action faster than 0.96 ns compared to the latter. As described above, in the semiconductor device 1 of the present embodiment, the operating speed is faster than that of the comparative example, and it is presumed that the wiring impedance of the via electrode TH0 is made in comparison with the comparative example. Reduce the effect of the matter.

Further, in the semiconductor device 1, the pad electrodes P1 to P3 are arranged in a region corresponding to the 8-bit line pair, but the pads are connected to the diffusion layers D1, D3, and D7. For the sheet electrodes P1 to P3, it is also conceivable to arrange the pad electrodes P1 to P3 in a region corresponding to the 16-bit line pair as in the modification shown in FIG. 16(c). In this way, it is possible to set the area of each of the pad electrodes P1 to P3 to be larger. However, on the other hand, when there is an upper limit in the cross-sectional area of each of the via electrodes TH0, or when there is a limitation in the arrangement interval of the via electrodes TH0, since there is also a picture The general phase shown in Fig. 16(c) causes a decrease in the number of via electrodes TH0 connected to the respective diffusion layers as compared with the example of Fig. 16(a), and therefore it is necessary to pay attention. Further, since the via electrode TH0 is disposed only at the central portion of each of the diffusion layers, the diffusion layer is formed. At the end, the distance between it and the via electrode TH0 is vacant to a considerable extent. In this case, since the impedance (parasitic diffusion layer impedance) in the diffusion layer is increased, the circuit characteristics are deteriorated. Further, since the pad electrodes P1 to P3 of the gate electrode portion are arranged in a region corresponding to the 8-bit line pair as in the example of FIG. 16(a), it is largely Destroy the regularity of the tungsten layer TL. Therefore, the modification shown in Fig. 16(c) is preferable, and it is only used when the matter is considered in consideration of these matters and the best result can be obtained comprehensively.

Next, the power supply element SANPD will be described. 18 is a view showing the diffusion layers D10 and D11 (the ninth and tenth diffusion layers) of the power supply element SANPD and the gate electrode G10 (the sixth gate electrode) (refer to FIG. 4) and the position directly above. The tungsten layer TL is superimposed as shown in Fig. 16(a). Further, Fig. 19 is an additional view showing the wiring impedance of the via electrode portion in the circuit diagram shown in Fig. 4 (portion related to the power supply element SANPD). However, in the figure, the same wiring as that of Fig. 15 is shown only for the wiring impedance of the portion other than the via electrode of the control signal.

As shown in FIG. 18, in the semiconductor device 1 according to the present embodiment, the diffusion layer D10 is the same as the above-described diffusion layers D1, D3, and D7, and can be in an 8-bit line pair. In the configuration, two through-hole electrodes TH0 are arranged. Further, in the diffusion layer D11, four via electrodes TH0 can be arranged in the structure of the 8-bit line pair. In all, the diffusion layer D10 is via six through-hole electrodes The TH0 and the diffusion layer D11 are connected to the corresponding pad electrodes via the twelve via electrodes TH0. In this way, the diffusion layers D10 and D11 are connected to the pad electrode via the plurality of via electrodes TH0. When the tungsten layer TL is set to have a repeating structure of a 4-bit line pair, the system does not It may be achieved (refer to Figure 16(b)). Therefore, the power supply element SANPD is also the same as the n-type AAN of the auxiliary amplifier and the like, and can be said to be formed by the reverse structure of the tungsten layer TL by the amount of the 4-bit line pair. The wiring resistance of the via electrode portion (the wiring impedance shown in Fig. 19) is lowered.

As described above, according to the semiconductor device 1 of the present embodiment, since the pad electrodes P1 to P3 are arranged at every 8-bit line pair, the area can be set to be Exceeding the limit caused by the repeated construction of each 4-bit pair and 4-bit pair. Therefore, since the contact portion having a small wiring resistance through the tungsten layer TL can be formed, the n-type portion AAN in which the auxiliary amplifier can be provided in the sense amplifier region SAA is used.

Further, since the tungsten layer TL is a structure in which the octet line pair and the octet line are reversed each other, it is possible to prevent the unevenness of the exposure of the light lithography when the tungsten layer TL is formed.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the spirit and scope of the invention. These are also included in the scope of the present invention.

For example, in the above embodiment, the series is cited in 1 The case where four local IO line pairs are arranged in the sense amplifier area SAA is described as an example, but the present invention is configured as a local IO line pair in one sense amplifier area SAA. If the quantity is not 4, it can be applied. For the specific description, when the number of local IO line pairs associated with one of the sense amplifier regions SAA is n, the bit line pair is constructed in a reverse structure of n pairs and n pairs. Basically, it is disposed at the tungsten layer TL. In this case, the spacer electrodes P1 to P3 are arranged by the number of bit line pairs exceeding n, which is formed by the reverse structure of the tungsten layer TL by the amount of each n-bit line pair. In this case, it is possible to reduce the wiring impedance of the via electrode portion. Further, from the viewpoint of ensuring the regularity of the tungsten layer TL, the pad electrodes P1 to P3 are preferably arranged in a bit line pair every n × m (m is an integer of 2 or more). It is more desirable to configure it every 2n bit line pairs.

Further, in the above-described embodiment, the three pad electrodes P1 to P3 are disposed every octet line pair. However, the number of the pad electrodes to be placed is not limited to three. It is ideal to increase or decrease in response to the need.

AAN‧‧‧n-type auxiliary amplifier

AANPD, SANPD‧‧‧ power components

AAP‧‧‧P-section of auxiliary amplifier

BL0T, BL0B‧‧‧ bit line

CROSSA‧‧‧Intersection

D1~D8, D10, D11‧‧‧ diffusion layer

EQB, EQL‧‧‧ equalizer

G1~G5, G10‧‧‧ gate electrode

LIO0T, LIO0B‧‧‧Local IO line

MIO0T, MIO0B‧‧‧ main IO line

LMS‧‧‧Transmission switch

MATA‧‧‧ memory cell area

SAA‧‧‧Sense Amplifier Area

SAN‧‧‧n sense amplifier

The p-type of the SAP‧‧ sense amplifier

SWDA‧‧‧Sub Character Drive Area

T1~T6‧‧‧O crystal

SIG_1~SIG_5‧‧‧Control signal

V_1~V_3‧‧‧ constant voltage

VBLP‧‧ ‧ constant voltage

YS‧‧‧ column switch

YSW‧‧‧ control signal

Claims (20)

A semiconductor device comprising: first and second memory cell regions arranged side by side in a first direction; and formed between the first and second memory cell regions, and including plural numbers a sense amplifier region of the sense amplifier; and a first wiring layer; and a first wiring portion extending in the first direction and including at least the first wiring portion formed as the first wiring layer in the sense amplifier region And the first and second bit lines; and the first wiring portion of the first bit line and the first wiring portion of the second bit line are formed as the first wiring layer and oriented The first pad electrode extending in the second direction in which the first direction intersects. The semiconductor device according to the first aspect of the invention, further comprising: a semiconductor substrate including a first diffusion layer extending in the second direction; and the semiconductor substrate and the first wiring An interlayer insulating film between the layers: and first and second via electrodes respectively formed in the interlayer insulating film and connected to the first pad electrode and the first diffusion layer. A semiconductor device according to claim 2, wherein The first pad electrode includes first and second connection regions that are connected to the first and second via electrodes, and the first and second connection portions are in the second Configure side by side in the direction. The semiconductor device according to claim 1, further comprising: between the first wiring portion of the first bit line and the first wiring portion of the second bit line; The second pad electrode that is formed as the first wiring layer and extends in the second direction, the first pad electrode and the second pad electrode are arranged side by side in the first direction. The semiconductor device according to claim 4, further comprising: a semiconductor substrate including first and second diffusion layers which are arranged side by side in the first direction and extend in the second direction; And an interlayer insulating film formed between the semiconductor substrate and the first wiring layer; and a first and a first insulating layer formed in the interlayer insulating film and connected to the first pad electrode and the first diffusion layer a second via electrode; and third and fourth via electrodes respectively formed in the interlayer insulating film and connected to the second pad electrode and the second diffusion layer. a semiconductor device as recited in claim 5, The first pad electrode includes first and second connection portions that are connected to the first and second via electrodes, and the second pad electrode includes the first And the third and fourth connection portions that are connected to the fourth via electrode, wherein the first and second connection portions of the first pad electrode are arranged side by side in the second direction, and the first The third and fourth connection portions of the two spacer electrodes are arranged side by side in the second direction. The semiconductor device according to the first aspect of the invention, further comprising: a semiconductor substrate; and an interlayer insulating film formed between the semiconductor substrate and the first wiring layer; and a transistor a source and a drain which are respectively formed at the semiconductor substrate and extend toward the second direction, and a channel region sandwiched between the source and the drain, and are disposed in the channel region The upper gate electrode is formed as the first wiring layer between the first wiring portion of the first bit line and the first wiring portion of the second bit line, and faces the second direction a second pad electrode extending; and one of the source and the drain of the first pad electrode and the transistor, respectively, formed in the interlayer insulating film The first and second via electrodes to be connected; and the first and second drain electrodes are formed in the interlayer insulating film and are connected to the other of the second pad electrode and the source of the transistor and the drain 3 and the fourth via electrode. The semiconductor device according to claim 7, wherein the first pad electrode includes first and second connection portions that are connected to the first and second via electrodes, and the The second pad electrode includes third and fourth connection portions that are connected to the third and fourth via electrodes, and the first and second connection portions of the first pad electrode are The third and fourth connection portions of the second pad electrode are arranged side by side in the second direction in the second direction. The semiconductor device according to claim 7, wherein the plurality of sense amplifiers include a plurality of first sense amplifiers and a plurality of second sense amplifiers, and the sense amplifier region includes The first to third regions arranged side by side in the first direction and having the third region position between the first region and the second region are disposed in the first region The plurality of first sense amplifiers are arranged with the second plurality of senses in the second region. The amplifier is provided with the aforementioned transistor at the third region. The semiconductor device according to claim 9, wherein the first bit line is connected to one of the plurality of first sense amplifiers, and the second bit line is connected to One of the plurality of second sense amplifiers is connected. The semiconductor device according to any one of claims 7 to 10, further comprising: a third bit line complementary to the first bit line; and the first bit line formed in the first a second wiring layer above the wiring layer; and first and second partial IO lines which are formed as the second wiring layer in the sense amplifier region and extend in the second direction, and An auxiliary amplifier circuit configured to amplify a potential difference between 1 and a second local IO line, wherein the first and third bit lines are respectively connected to the first and second local IO lines, and the transistor It forms part of the aforementioned auxiliary amplifier. The semiconductor device according to any one of claims 1 to 9, wherein the first memory cell region includes a plurality of first memory cells, and the second memory cell region includes a plurality of second memory cells, wherein the first bit line extends to the first memory cell region And connected to a plurality of the plurality of first memory cells, wherein the second bit line extends to the second memory cell region and is opposite to the plurality of second memory cells A plurality of connections are made. The semiconductor device according to claim 4, further comprising: between the first wiring portion of the first bit line and the first wiring portion of the second bit line; The third pad electrode which is formed as the first wiring layer and extends in the second direction, and the first, second, and third pad electrodes are arranged side by side in the first direction. The semiconductor device according to claim 13, further comprising: a semiconductor substrate including first and third diffusion layers which are arranged in parallel in the first direction and extend in the second direction; And an interlayer insulating film formed between the semiconductor substrate and the first wiring layer; and a first and a first insulating layer formed in the interlayer insulating film and connected to the first pad electrode and the first diffusion layer a second via electrode; and are respectively formed in the foregoing interlayer insulating film and the second spacer a third and a fourth via electrode to which the electrode and the second diffusion layer are connected; and fifth and third portions respectively formed in the interlayer insulating film and connected to the third pad electrode and the third diffusion layer 6 through hole electrodes. The semiconductor device according to claim 14, wherein the first pad electrode includes first and second connection portions that are connected to the first and second via electrodes, and the The second pad electrode includes third and fourth connection portions that are connected to the third and fourth via electrodes, and the third pad electrode includes the fifth and fourth 6 through-hole electrodes correspondingly connected to the fifth and sixth connection portions, wherein the first and second connection portions of the first spacer electrode are arranged side by side in the second direction, and the second spacer The third and fourth connection portions of the electrode are arranged side by side in the second direction, and the fifth and sixth connection portions of the third pad electrode are arranged side by side in the second direction. . A semiconductor device comprising: first and second memory cell regions arranged side by side in a first direction; and formed between the first and second memory cell regions, and including plural numbers a sense amplifier region of the sense amplifier; and including a second direction extending in a direction intersecting the first direction a semiconductor substrate of the first diffusion layer; and a first wiring layer formed over the semiconductor substrate; and an interlayer insulating film formed between the semiconductor substrate and the first wiring layer; and facing the first direction a first and a second bit line extending and including at least a first wiring portion formed as the first wiring layer in the sense amplifier region; and the first wiring portion in the first bit line a first pad electrode formed as the first wiring layer between the first wiring portion of the second bit line; and a first diffusion layer and the first pad respectively penetrating through the interlayer insulating film The first electrode and the second via electrode are connected to each other, and the first pad electrode includes first and second contact portions that are in contact with the first and second via electrodes, respectively, and the first and second contact portions The contact portions are electrically connected to each other and arranged side by side in the second direction. The semiconductor device according to claim 16, wherein the semiconductor substrate further includes a second diffusion layer extending in the second direction, and the semiconductor device further includes: a second pad electrode formed as the first wiring layer between the first wiring portion of the 1-bit line and the first wiring portion of the second bit line; and The third and fourth via electrodes that respectively penetrate the interlayer insulating film and connect the second diffusion layer and the second pad electrode, and the first diffusion layer and the second diffusion layer are in the first direction The first pad electrode and the second pad electrode are arranged side by side in the first direction, and the second pad electrode includes the third and fourth via electrodes, respectively. The third and fourth contact portions that are in contact with each other are electrically connected to each other and arranged side by side in the second direction intersecting the first direction. The semiconductor device according to claim 17, wherein the semiconductor substrate further includes a channel region formed between the first diffusion layer and the second diffusion layer, and the semiconductor device is further provided. Further, the present invention includes a gate electrode including a gate electrode formed above the channel region, and the first diffusion layer and the second diffusion layer serving as a source and a drain. The semiconductor device according to claim 18, further comprising: a third bit line complementary to the first bit line; and a second bit formed above the first wiring layer a wiring layer and first and second partial IO lines which are formed as the second wiring layer in the sense amplifier region and extend in the second direction, and the first and second partial IO lines Potential difference between In the auxiliary amplifier circuit configured in a large manner, the first and third bit lines are connected to the first and second partial IO lines, respectively, and the transistor constitutes one of the auxiliary amplifiers. The semiconductor device according to any one of claims 16 to 19, wherein the first memory cell region includes a plurality of first memory cells, and the second memory cell region includes a plurality of second memory cells, wherein the first bit line extends to the first memory cell region, and is connected to a plurality of the plurality of first memory cells, and the second bit The line extends all the way to the second memory cell region and is connected to a plurality of the plurality of second memory cells.