KR100366731B1 - Semiconductor input circuit - Google Patents

Abstract

Provided are a semiconductor input circuit in which a plurality of input circuits are provided with input resistors to reduce the propagation delay of the input signal between the input terminal and the input circuit and respond at a high speed.

At the time of reset, the signal CAS / is "H", and the contacts 44-1 and 44-2 and the metal wirings 45-1 and 45-2 become "H". The output signals S51-1 and S51-2 of 1) are " L ".

In operation, the CAS / transitions to "L", and the contacts 44-1 and 44-2 and the metal wirings 45-1 and 45-2 transition to "L", so that the output signals S51-1, S51-2) transitions to "H".

When the reset is again performed, the CAS / transitions to "H", and the tone tact 44-1 and 44-2 and the metal wirings 45-1 and 45-2 transition to "H". -1, S51-2) transitions to "L".

Description

Semiconductor input circuit

The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM), a static random access memory (hereinafter referred to as a static random access momory (SRAM)) and a read-only memory ( Read-only momory, hereinafter referred to as ROM), and particularly an input circuit therein.

2 is a block diagram showing an example of a configuration of a DRAM which is one of the conventional semiconductor integrated circuit devices.

This DRAM has a row address buffer 1. The row address buffer 1 is a circuit which generates a row address output signal corresponding to the row address input signal. The row address buffer 1 is connected to the row decoder 2. The row decoder 2 is a circuit for decoding the output signal of the row address buffer 1 and outputting a decode signal for selecting a row address. This row decoder 2 is connected to a word driver 3. The word driver 3 is a circuit for selectively driving the word line WL based on the decode signal. The memory cell array 4 is connected to the word driver 3. In the memory cell array 4, memory cells are connected at intersections of a plurality of word lines WL and bit lines BL, and the memory cells are arranged in a matrix form.

On the other hand, this DRAM has a thermal address buffer 5. The column address buffer 5 is a circuit for outputting a column address output signal corresponding to the column address input signal.

This column address buffer 5 is connected to the column decoder 6. The column recorder 6 is a circuit for decoding the column address input signal and outputting a decode signal for selecting the bit line BL. The column decoder 6 is connected to the sense amplifier 7. The sense amplifier 7 is a circuit for amplifying the output of the memory cell array 4. The sense amplifier 7 is connected to the input / output selector 8. The input / output selector 8 is a circuit for determining the writing or reading of data.

In this DRAM, an input buffer 9 is provided. The input buffer 9 is a circuit which inputs the write data Din and is provided to the input selector 8. The output buffer 10 is also connected to the input / output selector 8. The output buffer 10 is a circuit which inputs the output of the sense amplifier 7 through the input / output selector 8, and outputs the read data Dout.

The timing generating circuit 11 generates a control signal for controlling the timing of each part based on the inverted row address strobe signal (hereinafter referred to as RAS /) or the inverted column address strobe signal (hereinafter referred to as CAS /). It is an output circuit. The refresh control clock generation circuit 12 is a circuit that generates a clock signal for refreshing a memory cell based on the output signal of the timing generation circuit 11. The internal address counter 13 is a circuit which counts the output signal of the refresh control clock generation circuit 12 and inputs it to the row address buffer 1. The two-input AND gate 14 is a circuit which outputs the logical product of the output signal of the timing generating circuit 11 and CAS /. The timing generating circuit 15 is a circuit for outputting a control signal for controlling timing based on the output signal of the AND gate 14 to the write clock generating circuit 16. The write clock generation circuit 16 is based on the output signal of the timing generation circuit 15 when the inversion write enable signal WE / is input. This circuit generates a write clock signal.

Next, the address selection (1), the write operation (2), and the read operation (3) of this DRAM will be described.

(1) address selection

The RAS / transitions from the high level (hereinafter referred to as "H") to the low level (hereinafter referred to as "L") so that the row address buffer 1 receives the row address input signal. Next, the row address buffer 1 is activated based on the row address input signal, converts the row address input signal of the TTL level to the MOS level, and generates a pair of complementary row address output signals. The row address output signal is input to the row decoder 2 to perform address selection. Next, based on the selected address, the word line WL is activated via the word driver 3 to finish the selection of the row address.

Similarly, CAS / transitions from "H" to "L", and the column address buffer 5 opens to receive the dress input signal. Then, the open buffer 5 is activated based on the column address input signal, converts the TTL level column address input signal to the MOS level, and generates a pair of complementary column address output signals. The column decoder 6 is inputted to the column address as an output signal, and address selection is performed. Next, the bit line BL is activated based on the selected address, and the selection of the column address is finished.

(2) recording operation

When the word line WL is activated, the memory cells connected to the word line WL are connected to one of the pair of bit lines. Next, the write data Din is input via the input buffer 9 and transferred to the pair of data lines. Next, only a pair of bit lines selected by the column decoder 6 are connected to the data lines, and the recording data Din is transferred. Again, write data Din is transferred to the memory cell connected to the weed line WL via the pair of bit lines.

(3) read operation

When the word line WL is activated, memory cells connected to the word line WL are connected to one of the pair of bit lines. Next, the small potential difference between the pair of bit lines is amplified by the sense amplifier 7. Next, the data amplified by the sense amplifier 7 is transmitted to the pair of day lines DL. At this time, of the plurality of pairs of bit lines, only one pair of bit lines selected by the column decoder 6 is connected to the data line DL. Next, data on the data line DL is inputted to the output buffer 10 via the input / output selector 8, and outputs read data Dout.

FIG. 3 is a circuit diagram showing an example of a configuration of a semiconductor input circuit which is an input of the timing generating circuit 11 in FIG.

This semiconductor input circuit has a pad 21 for inputting an inverted column address strobe signal CAS /. The pad 21 is connected to the input resistor 23 through the metal wire 22. The input resistor 23 is a resistor for dropping the overvoltage input from the pad 21. The input resistor 23 is formed of a material such as polysilicon during diffusion or in the vicinity of the pad 21, and has a resistance value of several hundred Ω to several KΩ. The input resistor 23 is connected to the input circuit 30-1 via the contact 24 and the metal wiring 25-1, and is connected to the input circuit 30-1 through the contact 24 and the metal wiring 25-1. 30-1) and the input circuit 30-2 via the contact 24 and the metal wiring 25-2. The input circuits 30-1 and 30-2 are constituted by inverters 31-1 and 31-2, respectively, and receive a signal from the pad 21 and transmit it to a circuit not shown later.

In addition, the wiring resistance 25-1a exists in the metal wiring 25-1, and the parasitic capacitance 25-1b exists between ground. Similarly, the wiring resistance 25-2a exists in the metal wiring 25-2, and the parasitic capacitance 25-2b exists between ground. The wiring resistors 25-1a and 25-2a have resistance values of several Ω to several tens of Ω, and are significantly lower than those of the input resistance 23. Parasitic doses 25-1b and 25-2b) are dose values of about 1PE.

4 is a time chart for explaining the operation of FIG. 3, in which time is plotted on the horizontal axis and voltage on the vertical axis. Referring to this figure, the operation of FIG. 3 will be described.

When reset, the CAS / is in the "H" state, and the contacts 24 and the metal wires 25-1 and 25-2 are in the "H" state, so that the outputs of the inverters 31-1 and 31-2 are output. The signals S31-1 and S31-2 are in the "L" state.

During operation, the CAS / transitions to the " L " state, and the contacts 24 and the metal wirings 25-1 and 25-2 transition to the " L " state, so that the output signals S31-1 and S31-2. ) Transitions to the "H" state.

When the reset is performed again, the CAS / transitions to the " H " state, and the contacts 24 and the metal wirings 25-1 and 25-2 transition to the " H " state, so that the output signals S31-1 and S31. -2) transitions to the "L" state.

If the resistance value of the input resistor 23 is 1 kΩ and the parasitic capacitances 25-1b. 25-2b are 1 pF, respectively, the time constant τ becomes 2 ns. The response delay T (= 3τ) when transmitting the input signal to 30-2) is 6 ns.

In addition, since the wiring resistances 25-1a and 25-2a are locally lower than those of the input resistance 23, the influence of the response delay T is ignored.

However, the semiconductor input circuit of FIG. 3 used in conventional DRAM has the following problems.

(1) In a semiconductor input circuit requiring high speed response, the response delay is large. For example, the response delay T (= 6 ns) cannot be ignored because the read time from CAS / is required to have a high speed of 10 ns to l 5 ns.

(2) If the resistance value of the input resistor 23 is halved, the response delay T is also halved, but the resistance to overvoltage such as static electricity is weakened, and the reliability is lowered.

(3) In order to reduce the parasitic capacitances 25-1b and 25-2b, when the inverters 31-1 and 31-2 are laid out near the input resistance 23, the response delay T decreases but the input is reduced. Since many elements are formed in the vicinity of the resistor 23, the pattern layout is difficult in practice.

SUMMARY OF THE INVENTION The present invention solves the problem that the above-described prior art has a large response delay, and does not impair the resistance to overvoltage, and is a high-speed response semiconductor having a low response delay without being restricted in the pattern layout. It is to provide an input circuit.

In the first aspect of the present invention, in order to solve the above problems, a semiconductor input circuit comprising a pad for inputting an input signal and a plurality of input circuits for receiving a signal from the pad, the transistor being formed on a semiconductor substrate, And devising such means.

That is, in the semiconductor input circuit, a contact formed on the semiconductor substrate and connected to the pad, and one end connected to the contact, formed of a resistive material on the semiconductor substrate or in a diffusion layer inside the semiconductor substrate. And a plurality of resistors respectively dropping the overvoltage input from the pad, a plurality of resistors respectively dropping the overvoltage input from the pad, and the other end of the plurality of resistors through the wiring material, respectively. Branch connections are made to the plurality of input circuits.

In the second invention, the plurality of resistors of the first invention are formed of the same or different materials.

In the third invention, the plurality of resistors of the first invention are formed in a laminated structure through an insulating layer.

In the fourth invention, in the first, second, or third invention, a write control signal and a read control signal of a semiconductor memory are input as the input signal, and the plurality of input circuits are write control configured of MOS transistors. It consists of an input circuit and a readout control input circuit.

According to the first invention, since the semiconductor input circuit is constituted as described above, an input signal is input from the pad, and the input signal is input to the plurality of input circuits respectively through the plurality of resistors. The plurality of resistors lower the overvoltage input from the pad.

According to the second aspect of the invention, since the plurality of resistors are formed of the same material, it operates so that the voltage drop rate is the same. In addition, when a plurality of resistors are formed of different materials, the short circuit can be prevented even when different patterns or resistors are present in the vicinity.

According to the third aspect of the present invention, since a plurality of resistors are formed in a laminated structure through an insulating layer, the short circuit can be prevented even when other patterns or resistors are in the vicinity, thereby reducing the pattern layout area without being restricted by the pattern layout. do.

According to the fourth invention, since the plurality of input circuits are composed of MOS transistors, they operate at low current consumption.

(Example)

First embodiment

FIG. 1 is a circuit diagram of a semiconductor input circuit provided in a DRAM which is one of the semiconductor integrated circuit devices shown in the first embodiment of the present invention. 5 is a diagram showing the pattern layout of FIG.

This semiconductor input circuit is a circuit provided in the timing generating circuit 11 inside the DRAM shown in FIG.

This semiconductor input circuit has a pad 41 for inputting CAS /. The pad 41 is formed in a square shape, such as aluminum, and is connected to the input resistor 43-1 via the metal wire 42 and the contact 42-1, and is connected to the input resistor 43-1 through the metal wire 42 and the contact 42-2. It is connected to 43-2. The input resistors 43-1 and 43-2 drop the overvoltage input from the pad 41. The input resistance 43-1 is formed in the form of a rectangle of a resistance material such as polysilicon in the vicinity of the pad 41, and has a resistance value of several hundred Ω to several kΩ. The input resistance 43-2 is formed in a rectangular shape as a diffusion layer inside the substrate 40 in the vicinity of the pad 41 and has a resistance value of several hundred Ω to several kΩ. The input resistor 43-1 is connected to the input circuit 50-1 via the contact 44-1 and the metal wiring 45-1. The input resistor 43-2 is connected to the input circuit 50-2 via the contact 44-2 and the metal wiring 45-2. The input circuits 50-1 and 50-2 are composed of inverters 51-1 and 51-2, respectively, and are circuits which receive a signal from the pad 41 and transmit it to a circuit (not shown) at a later stage. .

In addition, the wiring resistance 45-1a exists in the metal wiring 45-1, and the parasitic capacitance 45-1b exists between ground. Similarly, the wiring resistance 45-2a exists in the metal wiring 45-2, and the parasitic capacitance 45-2b exists between ground. The wiring resistors 45-1a and 45-2a have a resistance value of several ohms to several tens of ohms, and are significantly compared with the input resistances 43-1 and 43-2. Parasitic doses 45-1b and 45-2b are dose values of about 1 pF. The resistor 46 formed of polysilicon or the like is a resistor belonging to another circuit.

6 is a time chart for explaining the operation of FIG. 1, in which time is plotted on the horizontal axis and voltage on the vertical axis. Referring to this figure, the operation of FIG. 1 will be described.

At reset, the CAS / is in the " H " state and the inverters 51-1 and 51- are in the " H " state of the contacts 44-1 and 44-2 and the metal wires 45-1 and 45-2. The output signals S51-1 and S51-2 of 2) are in the "L" state. In operation, the CAS / transitions to the " L " state, and the contacts 44-1 and 44-2 and the metal wires 45-1 and 45-2 transition to the " L " state, so that the output signal S51 -1, S51-2) transitions to the "H" state. When the reset is performed again, the CAS / transitions to the "H" state, and the contacts 44-1 and 44-2 and the metal wirings 45-1 and 45-2 transition to the "H" state. (S51-1, S51-2) transition to the "L" state. When the resistance values of the input resistors 43-1 and 43-2 are 1 kΩ and the parasitic capacitances 45-1b and 45-2b are 1 pF, respectively, the time constant τ becomes 1 ns, so the input from the pad 41 is input. The response delay T (= 3τ) at the time of transmitting the input signal to the circuits 50-1 and 50-2 is 3 ns, which is halved compared with the response delay t (= 6 ns) of the conventional semiconductor input circuit of FIG. . In addition, since the wiring resistances 45-1a and 45-2a were significantly lower than the input resistances 43-1 and 43-2, the influence on the response delay T was ignored.

As described above, in the present embodiment, since the input resistors 43-1 and 43-2 are provided on the input side of the input circuits 50-1 and 50-2, respectively, the resistance to overvoltage is not compromised. Fast response is possible with half the response delay of the technology. In addition, since the input resistor 43-2 is formed as a diffusion layer inside the substrate 40, the short can be prevented even when the resistor 46 is in the vicinity, so that the pattern layout area can be reduced without being restricted by the pattern layout. have.

Second embodiment

FIG. 7 is a pattern layout diagram of a semiconductor input circuit according to a second embodiment of the present invention, and FIG. 8 is an enlarged cross-sectional view of the A-ATJS of FIG. 7, with elements shown in FIGS. 1 and 5 showing the first embodiment. Common elements are given common signs.

In this semiconductor input circuit, the metal 0 wiring 42 from contact 42-1 to contact 42-2 is shorter than the pattern layout of the first embodiment shown in FIG. 5, and the input resistance 43-1 is on the first layer. It is formed in a rectangular shape of polysilicon, and the input resistance 43-2 is formed in a ruled shape of polysilicon on the second layer, and has a laminated structure through the insulating layer 43.

In this embodiment, since the circuit configuration is the same as in the case of the first embodiment, the operation is also the same. In the present embodiment, similarly to the first embodiment, it is possible to respond quickly at high speed without compromising resistance to overvoltage. Moreover, since at least a part of the input resistance 43-1 and the input resistance 43-2 has a laminated structure through the insulating layer 43 as compared with the first embodiment, the pattern layout area can be further reduced.

Third embodiment

9 is a cross-sectional view of a semiconductor input circuit showing a third embodiment of the present invention. This cross section is a cross section corresponding to FIG. 8 of 2nd Embodiment.

This semiconductor input circuit differs from the eighth embodiment in the second embodiment in that the input resistor 43-2 is formed as a diffusion layer inside the substrate 40.

Also in this embodiment, since the circuit configuration is the same as in the case of the first embodiment, the operation is the same. As described above, in the present embodiment, as in the first embodiment, it is possible to respond quickly at high speed without compromising resistance to overvoltage. Furthermore, compared with the first embodiment, since the input resistance 43-2 is formed as a diffusion layer inside the substrate 40, the short can be prevented even when another pattern is in the vicinity, without being restricted by the pattern layout. The pattern layout area can be further reduced.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of such modifications include the following.

(a) The semiconductor input circuit of the above embodiment may be applied to the input portion of the RAS / of the timing generation circuit 11 in FIG.

(b) The overall configuration of the DRAM of FIG. 2 may be another circuit configuration.

(c) The semiconductor input circuit of FIG. 1 may have other circuit configurations such as a gate circuit and a buffer.

(d) The two input circuits 50-1 and 50-2 may be three or more.

(e) The present invention can be applied to other semiconductor integrated circuit devices such as SRAM and ROM.

As described in detail above, according to the first aspect of the invention, since a plurality of input resistors are provided on the input side of the plurality of input circuits for the problem that the response delay is large, the prior art without compromising resistance to overvoltage. The semiconductor input circuit responds with high speed with half response delay. Moreover, since any one input resistor is formed as a diffusion layer inside the substrate and a plurality of input resistors are formed in a stacked structure, short can be prevented even when other patterns or resistors are in the vicinity, thereby limiting the pattern layout. The pattern layout area can be reduced without receiving.

According to the second invention, since the plurality of resistors are made of the same material, the voltage drop rate can be made the same. In addition, when the plurality of resistors are formed of different materials, the short can be prevented even when different patterns or resistors are in the vicinity.

According to the third aspect of the present invention, since a plurality of resistors are formed in a laminated structure through an insulating layer, the short can be prevented even when other patterns or resistors are in the vicinity, thereby reducing the pattern layout area without being restricted by the pattern layout. can do.

According to the fourth invention, since the plurality of input circuits are composed of MOS transistors, it is possible to operate with a low current consumption.

1 is a circuit diagram of a semiconductor input circuit according to a first embodiment of the present invention;

2 is a block diagram of a conventional DRAM,

3 is a circuit diagram showing a conventional semiconductor input circuit inside the timing generation circuit in FIG.

4 is a time chart of the conventional semiconductor input circuit of FIG.

5 is a view showing a pattern layout of FIG.

6 is a time chart of the semiconductor input circuit of FIG.

7 is a view showing a pattern layout of a second embodiment of the present invention;

8 is an enlarged cross-sectional view along the line A-A of FIG.

9 is a cross-sectional view corresponding to FIG. 8 showing a third embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

40: substrate 41: pad

42: metal wiring 42-1, 42-2: contact

43-1, 43-2: Pressure resistance 50-1, 50-2: Input circuit

51-1, 51-2: Inverter

Claims (4)

A pad for inputting an input signal, A plurality of input circuits composed of transistors and receiving a signal from the pad, In a semiconductor input circuit formed on a semiconductor substrate, A contact formed on the semiconductor substrate and connected to the pad; A plurality of resistors are formed on the semiconductor substrate with one end connected to the contact or formed in the diffusion layer inside the semiconductor substrate, each of which lowers the overvoltage input from the pad, And the other ends of the plurality of resistors are branched to the plurality of input circuits, respectively, through a wiring material. The method of claim 1, And the plurality of resistors are formed of the same or different materials. The method of claim 1, And the plurality of resistors have a laminated structure through an insulating layer. The method according to claim 1, 2 or 3, And the input signal is a write control signal and a read control signal of a semiconductor memory, and the plurality of input circuits are a write control input circuit and a read control input circuit composed of MOS transistors.