JPS63237291A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a storage device to which a dummy cell system can be applied, by allowing a pair of bit lines to cross, providing a dummy cell and a word line on the bit line, and connecting a selected word line to a bit line side forming a pair with a bit line of a selected memory cell, in accordance with a position, by a dummy word line decoding means. CONSTITUTION:A pair of bit lines are divided into four equal parts in the lengthwise direction, the pair for crossing at an equally divided point CP2 and a bit line end CP4, and the pair for crossing at equally divided points CP1, CP3 are placed alternately, and two pieces each of dummy word lines are placed by placing the point CP4 between. Blocks (a)-(d) correspond to the respective low addresses, and DWL0 to WL1, DWL1 to WL0' in the area (a), and DWL2 to WL1, DWL3 to WL1' in the area (b), and DWL1 to WL2, DWL0 to WL2' in the area (c), and DWL3 to WL3, DWL2 to WL3' in the area (d) are selected through a decoding means. According to this constitution, a dummy cell system for conforming to a place containing an intersection, as well can be realized, and a storage device having high reliability is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device, and particularly to prevention of signal read errors.

[Conventional technology]

Figure 4 is a diagram of a conventional dynamic semiconductor memory device.
The structure of 491 pairs is shown. Bin) l pair BL, BL has a plurality of memory cells (Cs) and word line signals (WLo, WL, WL,
...) is connected to the transfer gate TG. In addition, each bit line has a dummy cell (DC, , DC,) for generating a reference level, and a dummy word line (DwLo, DWLI) connecting this and the bit line.
) is connected, the word line and dummy word line rise again, and a signal voltage difference appears on the bit line pair, then a sense amplifier (S
A) is connected. Further, the bit line pair selected according to the column address is connected to the data input/output line pair (I10.
Transfer gates QI, Q connected to I10)
+, and the column decoder 1 output is input to this gate.

Next, consider the signal voltages that appear on each bit line pair when reading signals.

As shown in FIG. 5, each bit line is connected to the ground voltage (fixed potential) via the cell plate or substrate at
, C2 with respect to the paired bit lines and C3 with respect to the bit lines of the adjacent bit line pair.

Bit line length! , the memory cell capacity is Cs.

The memory cell has “H” level: Cs Vcc (Vcc write) L
``Level: Q (OV writing) It is assumed that a charge with a capacitance of CS Vcc (Cs) is stored in the dummy cell.

If the precharge level of the bit line is vcc, for example, a memory cell connected to the bit line BLI is selected,
When a dummy cell is connected to the bit line, the potential of the bit line B I, +, B I, + is as follows: (When reading "L") ... (1) (When reading H) ・...(2) However, Δ■IILO+ Δ
vIILI+ΔVIILI+ΔVILZ are potential changes of the bit lines indicated by subscripts.

From equations (1) to (3), considering that the bit lines BL, , and B completion have the same precharge level, equation (1) - (
2) From the calculations (1)-(3), the voltage difference between the bit line pair is as follows.

VILI vyrr ”'Δv!lLI −Δvgc
＋＋□・(ΔVILO−ΔV++Lz)l×α...(4) "+" is when reading 'H', '-' is when reading "L" The first term on the right side of equation (4) is the original read voltage The second term of the difference is a noise component via the coupling capacitance from the bit lines BLO and BL2 of the adjacent bit line pair.

By the way, as the integration of memories progresses and the bit line pitch decreases, the bit line pair capacitance fflC3 increases, and the second term in equation (4) increases. Therefore, this causes a problem in that the read voltage is significantly impaired, the read margin is reduced, and the soft error rate is worsened, eventually leading to malfunction.

The following example is a device devised by the present inventors that solves the problems of the above devices, and completely eliminates the drop in read voltage amplitude due to noise between adjacent bit line pairs due to bit line capacitance. This shows a semiconductor memory device that can be set to zero.

In the semiconductor memory device according to this example, by providing an intersection at one or more locations on a bit line pair, each of the paired bit lines receives exactly the same capacitive coupling noise from an adjacent bit line pair, and read This is to eliminate the drop in voltage difference.

Next, a semiconductor memory device according to an improved example of this conventional technique will be explained with reference to FIG.

In this improved example, each bit line pair is
(BL,, Hyakuryoτ, BL2. BL+,
) is divided into four equal parts a, b, c, and d, and at these equal dividing points CP, ・cp, ,cp,
They intersect as shown below.

■ BLo, 100Tτ intersects at cp, ■ BL,,B
L, intersects at CP r and cpz, ■'BLt, BL2 intersects at CP z, ■'BL3.
100T intersects at CP and cp, i.e., bit line pair BL, counting from 100 lines, the odd bit line pair intersects at CP2, and the even bit line pair intersects at CPl and CP3. It intersects. As a result, the capacitive coupling noise that each bit line pair receives from the adjacent bit line pair is as follows when considered in the same way as in the conventional example described above.

(2) The capacitive coupling noise ΔVBLI' and ΔV penalty T' that the bit vABLI and the 100 bits receive from the adjacent bit line pair are as follows, and they are completely equal.

(2) The capacitive coupling noises Δ■ILZ' and Vroad' that the bit lines BL2 and BL2 receive from the adjacent bit line pair are as follows, and both are completely equal.

Similarly, for all bit line pairs, the capacitive coupling noise received by each pair of bit lines from the adjacent bit line pair is exactly the same. Note that the bit line pair BLO, B at the end of the memory array is also classified as follows: section C section d section a section, and both are completely equal.

In this way, in this improved example, the capacitive coupling noise received by each of the paired bit lines from the adjacent bit line pair when reading signals is completely equal, so there is no drop in the read voltage difference due to this noise. can,
Expansion of read margin 2 An improvement in the soft error rate can be achieved.

FIG. 7 shows a second improved example of the prior art. The difference between this improved example and the improved example shown in FIG. 6 is that the odd-numbered bi-nod line pair (B
Lo, BLo, BL2, 几,...
), a crossing is added at the bit line end CP4. Intersection cp, , cp2. provided in this improvement.
CP, it is impossible to lay them out completely symmetrically with respect to the bi/nodal line pair. 6th
In the case of the improved example shown in the figure, even-numbered bit line pairs (BL, , B
L Tomi, BL3. Regarding B mouth...), each
Since there are two intersections, a balanced layout is possible for the entire bit line pair. For example, if the bit line is the A1 layer and the wiring layer that can intersect with it is a polySt layer, the cp, BL is Al, and the BL is polySi.

In the CP, the BL may be made of poly-Si and the B process τ may be set to /1, thereby making it possible to avoid unbalance of the stray capacitance of the bit line pair. The improvement shown in FIG. 7 has the same purpose as this, and adds a dummy crossing CP a to balance the odd-numbered bit line pairs, thereby balancing the capacitance for all bit line pairs. It is possible to achieve this state.

In addition, in the above improvement example, the bit line pair is divided into 4 sections and crossed at appropriate places, but the same effect can be obtained even if the number of sections is 8 sections, 12 sections, or an integral multiple thereof. play. FIG. 8 shows an example of 8 sections, which is a shape in which the shape in FIG. 7 is repeated twice, and it is clear that the same effect as the example in FIG. 7 can be obtained.

Next, we will discuss the problems with such conventional improved examples.

As in the improved example above, when the bit line pair includes an intersection,
Consider the case where the dummy cell method is applied.

FIG. 9 shows a configuration diagram when a conventional dummy cell method is applied to the device shown in FIG. 7. In this figure, the word line (W
Lo, WLo', WLt,, WLt'
.

The ○ mark at the intersection between the bit line and the dummy word line (DWLo, DWL+) indicates that a memory cell is placed, and the ○ mark at the intersection between the dummy word line (DWLo, DWL+) and the bit line indicates that a dummy cell is placed. indicates that it is placed.

As shown in the figure, the memory cell arrangement is such that, for example, a memory cell selected by a word line WL is selected by a bit line BL.
o, BL+, BLz, BL3, ...
・The word line WL0 adjacent to the word line WLo
The memory cell selected by
3 ■ Completed, ■ Completed 7. They are arranged alternately, such as being connected to π, τ, and so on. The same applies to dummy cell placement, for example, dummy word 'fM D W
The dummy cell selected by Lo is the bit line BL
o, BL+, BLz, BL3. The dummy cells connected to .
It is connected to...

Considering that it is necessary to connect the dummy cell to the bit line on the opposite side to the bit line to which the memory cell is connected (the bit line on the reference side), in the case of Fig. 9, ■ the word in block a line, WLo, WLo'
If WLo is selected, DWL is selected, and if WL0' is selected, DWLO is selected.

■ When the word lines WL, , WL,' in block b are selected, there are only half of the total bit line pairs that are always incompatible no matter which of D W Lo and D W L + is selected. do.

■If the word lines WLz and WLz' in block C are selected,■If WLt is selected in the same way, select DWLo, and if WL,' is selected, select DWL. .

(2) If the word line WL:+, WL,' in block d is selected, the situation similar to (2) will occur.

As described above, the conventional dummy cell method cannot be used when such a bit line pair includes an intersection.

[Problem that the invention seeks to solve]

Conventional semiconductor memory devices are configured as described above, so if a bit line pair includes an intersection, there will be a bit line pair in which the dummy cell is not connected to the reference side bit line in the normal dummy cell method, and the method will not be compatible with that method. The problem was that it didn't.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory device to which the dummy cell method can be applied even when a bit line pair includes an intersection.

[Means for solving problems]

In the semiconductor memory device according to the present invention, a pair of bit lines intersect at one or more locations, a dummy cell and a dummy word line are provided on the bit line, and one of the dummy word lines
A dummy word line decoding means is provided for selecting the word line according to the position of the selected word line so that the book is connected to the bit line side that is paired with the bit line to which the selected memory cell is connected.

[Effect]

In this invention, one of the plurality of dummy word lines
The dummy cell method can be applied even when the bit line pair includes an intersection by using the dummy word line decoding means that selects the word line to be connected to the bit line side that is paired with the bit line to which the selected memory cell is connected.

〔Example〕

Examples of this invention will be described below.

FIG. 1 shows a semiconductor memory device according to a first embodiment of the present invention. In this embodiment, the structure of the dummy cell is different from the conventional one shown in FIG. Dummy word line D
W L o = D W L s is decoded by the position of the selected word line, and one of the four lines becomes selected. Dummy cells are arranged on each dummy word line as shown, and these dummy words 'frrAD
Two WL0 to DWL3 are arranged on both sides of the intersection CP4. Also, each block a w d has the row address RA, RA, (i≠j), so that block a: RA, = RA4 = 0 block b: R
A, ÷O, RA, = 1 block c: RA, = 1. R
AJ=0 block d: RA,=RA,=1, and word lines WL, , WL. '.

WLI, WL,',... are row addresses R
By Ak(k#i, ≠j), WLo, WLI, WLz, WLi,...:
RAk = 0WLo', WL+', WLz', WL
z′, ・”: It is assumed that it is decoded as RAM=1.

In this embodiment, the dummy words FL7iDWLo to DWL3 may be selected as follows depending on the selected word line.

■In block a If WL is selected: DWLO What if WL,’ is selected? DWL.

■If WL in block b is selected: DWLz If WL, ' is selected: DWL3 ■If WL in block C is selected: DWL.

If wt, z' is selected: DWLO ■ block d
If WL, inside is selected: DWL3 If WL,' is selected: Dwt,z These are the row addresses RA3. RAj.

This means that the selected dummy word line is selected as follows for the value of RA.

An example of realizing such an operation is shown in FIG. This results in
By decoding according to the table above, the dummy word line drive transistor T. -T3 becomes "H" level, and with the rise of the dummy word line rise signal φ, the corresponding dummy word line rises and becomes a selected state.

As described above, according to this embodiment, by additionally arranging dummy cells and dummy word lines, which are exactly the same as in the conventional dummy cell method, by 17 nodes (corresponding to 2 dummy word lines) and sandwiching the intersection CP4, A dummy cell system that can be easily applied to a bit line system that includes crossings can be realized.

In addition, in the above explanation, the word lines w L o , W
L o ' is shown as a representative word line in block a, and this is exactly the same for other word lines in block a, and the same is true for other blocks.

Further, the arrangement position of the dummy word line is not limited to the position in the above embodiment, but may be on both sides of another intersection.

Further, in the above embodiment, the case where the present invention is applied to the conventional device shown in FIG. 7 was shown, but the present invention is applied to the conventional device shown in FIG.

It can be similarly applied to other devices such as those shown in FIG.

FIG. 3 shows a semiconductor memory device according to a second embodiment of the invention. In this case, dummy word line DWL2. DWLf
For f, dummy cells are arranged continuously for every two bit lines that intersect with each other, and one dummy cell is placed for each bit line pair. By changing the dummy cell arrangement for some of the dummy word lines in this way, the dummy word '' is placed on one side of the intersection! 4
1ADWL.

~Even if four DWL3s are arranged together, a dummy cell system can be realized without any problem. In addition, in this case as well, the dummy word line D
WL to DWL3 may be decoded using exactly the same method as in FIG. 2.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, one of the plurality of dummy word lines is connected to the bit line side forming a pair with the bit line to which the selected memory cell is connected. Since the dummy word line decoding means for selecting is provided, a dummy cell system suitable even when the bit line pair includes an intersection can be realized, and there is an effect that high reliability can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing dummy word line decoding according to the present invention, and FIG. 3 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the present invention. 4 is a block diagram showing a semiconductor memory device; FIG. 4 is a block diagram of a conventional semiconductor memory device; FIG. 5 is a diagram for explaining the memory cell capacity of a conventional semiconductor memory device; FIGS. FIG. 8 is a block diagram of a conventional semiconductor memory device having bit line pair crossings, and FIG. 9 is a block diagram of a case where a dummy cell method is applied to a conventional semiconductor memory device having bit line pair crossings. BLo, BLo, Bl, +, BL+, ・・
・・・・Bit line, WLo, WL,...
...Word line, DWLo. DWLI,... dummy word line, C,...
Memory cell, SA...Sense amplifier, CPl, CPU
, CF2...intersection, C20...bit line end, a
,b. c, d...block. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) It has a memory cell array consisting of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells located at the intersections of these, and the two bit lines form a pair and the voltage difference between the bit line pair is In a semiconductor memory device configured to be input to one sense amplifier for detection, each bit line pair has an intersection at one or more locations, and each bit line has a reference potential for reading the memory cell potential. dummy potential generation means for generating
and a plurality of dummy word lines for selecting and connecting the dummy potential generating means to one of the bit line pairs, one of the plurality of dummy word lines being connected to a selected memory cell. 1. A semiconductor memory device comprising dummy word line decoding means that selects a dummy word line according to the position of a selected word line so that the dummy word line is connected to a bit line that is paired with a bit line to which the dummy word line is connected. (2) When each bit line pair is divided into four equal parts in the length direction, the three equal dividing points and bit line ends are CP_1, CP_2, CP_
3. When CP_4, the above bit line pair is equally divided point CP
Lines having intersections at _2 and bit line end CP_4 and lines having intersections at equal dividing points CP_1 and CP_3 are alternately arranged, and the plurality of dummy word lines are four.
Two of these lines are the above equally divided points and bit line end CP_1.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is arranged with one of CP_4 in between. (3) There are four dummy word lines, two of which are connected to every other bit line of the bit lines, and the other two are connected to every other bit line of the bit lines. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to two alternately adjacent bit lines.