JP3239130B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
For semiconductor memory devices, especially for signal read error prevention
Is what you do. [0002] 2. Description of the Related Art FIG. 4 shows a conventional dynamic semiconductor memory.
2 shows the structure of a bit line pair of the device. Bit line pair BL, BL
The bar includes a plurality of memory cells (Cs) and memory cells.
The word line signal (W) is connected to the gate for connecting the bit line.
L₀, WL₁……) receives the transfer gate TG
Connected. In addition, each bit line has a reference level.
Dummy cell for generation (DC₀, DC₁) And this
Dummy word line (DWL) connecting bit lines₁, DWL
₁) Is connected, and the word line and dummy word line
Ascending, after a signal voltage difference appears on the bit line pair,
A sense amplifier (S) for sense-amplifying the bit line potential
A) is connected. Also, according to the column address
The selected bit line pair is connected to the data input / output line pair (I / O, I
/ O bar) transfer gate Q₁, Q₁Ba
This gate receives the output of column decoder 1
Is done. Next, at the time of signal reading, each bit line pair
Consider the signal voltage appearing at Each bit line is shown in FIG.
As described above, the grounding
With respect to the position (fixed potential)₁For paired bit lines
C_Two, C with respect to the bit line of the adjacent bit line pair._ThreeWhat
It has a capacity that is Bit line length is l, memory cell
Let Cs be the storage capacity. In the memory cell, “H” level: CsV_CC(V_CCwriting) “L” level: 0 (0 V write) The dummy cell has 1 / 2CsV_CC(1/2 of the capacity of Cs
V_CCWrite).
You. The precharge level of a bit line is set to V_CCToss
Then, for example, the bit line BL₁Memory cell connected to
Selected bit line BL₁A dummy cell is connected to the bar
Bit line BL₁, BL₁Bar potential V_BL1, V
_{/ BL1}(/ BL1 indicates BL1 bar) [0005] (Equation 1) From the equations (1) to (3), the bit line BL₁, BL
₁Both bars have the same precharge level,
From the calculations of Equations (1)-(2) and Equations (1)-(3), the power
The difference is as follows. [0007] (Equation 2) The first term on the right side of equation (4) is the original read voltage.
Difference, the second term is the bit line BL of the adjacent bit line pair₀Ba
ー, BL_TwoThis is a noise component through the coupling capacitance from the. [0009] By the way, as the integration of the memory is advanced, the bit size is increased.
When the line pitch decreases, the capacitance C between the bit lines is reduced._ThreeBut
And the second term of equation (4) increases. Therefore
As a result, the read voltage is significantly impaired, and the read margin
And the soft error rate worsens, and finally
Causes a problem of malfunction. The following example is an apparatus devised by the present inventors.
This is a solution to the problems of the above equipment.
Readout due to noise between adjacent bit line pairs due to line capacitance
Semiconductor that can completely reduce the drop in voltage amplitude
3 shows a storage device. Semiconductor memory device according to this example
At the intersection of one or more locations on the bit line pair
, Each of the paired bit lines has an adjacent bit line.
Make the capacitive coupling noise received from the
The output voltage difference is prevented from lowering. Next, a semiconductor memory according to the conventional improved example will be described.
The apparatus will be described with reference to FIG. In this improved example,
As shown in FIG.₀, BL₀Bar, B
L₁, BL₁Bars,...) Represent the quadrants a, b,
divided into c and d, these equal points CP₁, CP_Two, CP
_ThreeAnd intersect as follows.   BL₀, BL₀Bar is CP_TwoCross at   BL₁, BL₁Bar is CP₁And CP_ThreeCross at 'BL_Two, BL_TwoBar is CP_TwoCross at 'BL_Three, BL_ThreeBar is CP₁And CP_ThreeCross at That is, the bit line pair BL₀, BL₀Odd number counting from the bar
The bit line pair is CP_TwoAt the even-numbered bit
Line pair is CP₁And CP_ThreeIntersect at This allows
Capacitive coupling that each bit line pair receives from adjacent bit line pairs
Considering the noise in the same way as the conventional example described above,
become. The bit line BL₁And BL₁Bar adjacent
Capacitive coupling noise ΔV received from bit line pair_BL1', V
_{/ BL1}'(/ BL1 indicates BL1 bar) [0013] (Equation 3) And both are completely equal.   Bit line BL_TwoAnd BL_TwoBar is adjacent bit line pair
Capacitive coupling noise ΔV_BL2', V_{/ BL2}´ (/ BL
2 indicates a BL2 bar) [0015] (Equation 4) And both are completely equal. The same applies hereinafter
For all bit line pairs,
However, the capacitive coupling noise received from adjacent bit line pairs is completely equal
It will be something new. The bit line pair B at the end of the memory array
L₀, BL₀About the bar, [0017] (Equation 5) And both are completely equal. in this way,
In this improved example, each of the paired bit lines
Sometimes capacitive coupling noise received from adjacent bit line pairs
Because they are completely equal, readout by this noise
Voltage drop can be completely eliminated, and readout
The gin can be expanded and the soft error rate can be improved. FIG. 7 shows a second conventional example of improvement. This improvement
The example differs from the improved example of FIG. 6 only in the odd-numbered bit line pairs.
(BL₀, BL₀Bar, BL_Two, BL_Twobar,……)
And the bit line end CP_FourThat the intersection is added
And Cross CP provided by this improvement₁, CP_Two, CP_Three
Are completely symmetric about the bit line pair.
It is impossible to lay out in shape. Improvement example of FIG.
, The even-numbered bit line pair (BL₁, BL₁bar,
BL_Three, BL_ThreeBars,…))
Since there are two locations, the balance for the entire bit line pair is
Layouts are possible. For example, if the bit line is Al
If the wiring layer that can cross this layer is a poly-Si layer, C
P₁Then, BL₁To Al, BL₁Bar with poly Si, CP
_ThreeThen, BL₁Is poly Si, BL₁If the bar is Al
Well, this allows the stray capacitance of the bit line pair to be unbalanced.
Can be avoided. The improvement of FIG.
For the purpose, balance the odd-numbered bit line pairs
So, the dummy intersection CP_FourIs added.
As a result, the capacity is balanced for all bit line pairs.
State can be realized. In the above-described improved example, the bit line pairs are divided into four sections.
Divided into minutes and crossed at appropriate places
However, this section is an integral multiple of 8 sections, 12 sections, etc.
Has the same effect. FIG. 8 shows an example in the case of eight sections.
This is a form obtained by repeating the form of FIG. 7 twice, and FIG.
It is clear that the same effect as in the example can be obtained. Next, the problems of the conventional improved example will be described.
State. Includes intersections in bit line pairs as in the above improved example
In this case, consider the case where the dummy cell method is applied. FIG.
Is the case where the conventional dummy cell method is applied to the device of FIG.
An example of the configuration will be described. In this figure, the word lines (WL₀, WL
₀', WL₁, WL₁´, ……) and the bit line
O indicates that the memory cell is arranged, and
Dummy word line (DWL₀, DWL₁) And the bit line
A circle at the intersection indicates that a dummy cell is arranged.
The memory cell arrangement is, for example, as shown in FIG.
Line WL₀Is selected by the bit line BL
₀, BL₁, BL_Two, BL_Three, …… connected to the word
Line WL₀Word line WL next to₀The menu selected by ´
The memory cell is connected to the bit line BL₀Bar, BL₁Bar, BL_Two
Bar, BL_ThreeBars, etc. are connected alternately, etc.
Have been. This is the same for the dummy cell arrangement.
For example, the dummy word line DWL₀Dami selected by
Cell is a bit line BL₀, BL₁, BL_Two, BL_Three,
.., And the dummy word line DWL₁Selected by
The dummy cell to be used is a bit line BL₀Bar, BL₁bar,
BL_TwoBar, BL_ThreeConnected to bars, ... A dummy cell is a via to which a memory cell is connected.
Bit line on the opposite side (the bit on the reference side)
Considering that it is necessary to connect
in the case of,   Word line in block a, WL₀, WL₀´ is selected
If done, WL₀If is selected, DWL₁Choose
Select, WL₀If 'is selected, DWL₀Select
Just fine.   Word line in block b, WL₁, WL₁´ is selected
DWL₀, DWL₁Whichever you choose
Only half of the total number of unmatched bit line pairs exist
I do.   Word line in block c, WL_Two, WL_Two´ is selected
If done, similarly WL_TwoIf is selected, DWL
₀And select WL_TwoIf 'is selected, DWL₁Choose
You can choose.   Word line in block d, WL_Three, WL_Three´ is selected
If this is done, the situation will be similar to that described above. As described above, the conventional dummy cell method does not
This is not applicable when the crossing is included in the line pair. [0023] A conventional semiconductor memory device
Is configured as above, so it intersects the bit line pair
When the dummy cell method is used, the dummy cell
A bit line pair that is not connected to the reference side bit line
However, there was a problem that the method was not adapted. The present invention solves the above problems.
In the case where a bit line pair contains an intersection
To obtain a semiconductor memory device to which the dummy cell method can be applied
The purpose is to: [0025] A semiconductor memory according to the present invention is provided.
The storage device has a plurality of memory cells arranged in a plurality of columns and a plurality of rows.
Memory cell array having a memory cell array,
Arranged in multiple rows, each in the corresponding row
The first bit to which half of the plurality of memory cells are connected
And the second bit line to which the other half are connected.
A plurality of bit line pairs, a plurality of columns of the above memory cell array.
Multiple menus, each arranged in a corresponding row
Semiconductor memory with multiple word lines connected to memory cells
In the memory device, the memory cell array is duplicated in the column direction.
Divided into a number of blocks.
Is the odd column in the block, Each of the even columnsWord line is odd-numbered
Of the first bit line and the second bit line of the bit line pair
Connected to the memory cell connected to the
Of the first bit line and the second bit line of the bit line pair
Combination of memory cells connected to
Is different for each block.
A reference for reading the memory cell potential is provided on the bit line pair.
Reference potential generator for generating reference potential
Step and the reference potential generating means are connected to a plurality of bit lines.
The first and second bits of the odd-numbered bit line pair of the pair
Connected to one of the lines, or
A set as to which one of the first and second bit lines is connected
Multiple reference word lines with different combinations
And the selected word line is
Word lines of these blocks, and odd and even columns
Based on the information on which word line is
REF to select one of the number of reference word lines
And a reference word line decoding means. [0026] Further, the semiconductor memory device according to the present invention comprises:
Has multiple memory cells arranged in multiple columns and multiple rows
Memory cell array, arranged in a plurality of rows of the above memory cell array
Multiple notes, each set in a corresponding row
The first bit line to which half of the recells are connected and the rest
And a second bit line to which half of the bit lines are connected.
And a plurality of memory cell arrays are arranged in a plurality of columns of the memory cell array.
Multiple memory cells each arranged in the corresponding column
A semiconductor memory device having a plurality of connected word lines
And the memory cell array has first to
4 is divided into four blocks, and the first block
In the memory block, word lines in odd columns are connected to bit line pairs in odd rows.
Memory cells connected to the first bit line, and even rows
Cell connected to the first bit line of the pair of bit lines
And in the second block, an odd column
Are connected to the first bit line of the odd-numbered bit line pair.
Connected memory cells and the second of the even-numbered bit line pairs.
Is connected to the memory cell connected to the bit line of
In the third block, the odd-numbered word lines are arranged in odd-numbered rows.
Memory cell connected to the second bit line of the bit line pair
Connected to the second bit line of the bit line pair in the even-numbered row.
Connected to the memory cell, and the fourth block
In the memory cell, the odd-numbered word lines are connected to the odd-numbered bit line pairs.
Memory cells connected to two bit lines, and
A memory cell connected to the first bit line of the bit line pair;
Connected to each other, and a note
Generate reference potential for recell potential reading
Potential generating means for generating
Potential generation means is connected to the odd-numbered row of the plurality of bit line pairs.
Connected to the second bit line of the bit line pair and
A first reference for connecting to a second bit line of a line pair
A word line and the reference potential generating means.
Of the bit line pairs in the odd-numbered row of the
Bit line connected to the first bit line of the even-numbered bit line pair.
A second reference word line for connecting to
The reference potential generating means is connected to a plurality of bit line pairs.
That is, the odd-numbered bit line pair is connected to the second bit line,
A plurality of bit line pairs for connecting to the first bit line.
3 reference word lines and the reference potential
Generating means for the odd-numbered bit lines of the plurality of bit line pairs.
Connected to the first bit line of the pair, and
Reference word for connecting to the bit line of
Line and the selected word line
Whether it is a word line of a shifted block, and odd columns, even numbers
Based on the information on which word line in the column
One of the first to fourth reference word lines
Reference word line decoding means for selecting
Things. Further, the semiconductor memory device according to the present invention comprises:
Having a plurality of memory cells arranged in a plurality of columns and a plurality of rows;
Divided into four blocks from first to fourth in the column direction
Memory cell array, arranged in a plurality of rows of the above memory cell array
Multiple notes, each set in a corresponding row
The first bit line to which half of the recells are connected and the rest
And a second bit line to which half of the bit lines are connected.
And a plurality of memory cell arrays are arranged in a plurality of columns of the memory cell array.
Multiple memory cells each arranged in the corresponding column
A plurality of word lines to be connected,
The line is divided into blocks corresponding to the plurality of blocks,
In the first block, the word lines in the odd-numbered columns are
A memory cell connected to the first bit line of the bit line pair;
And the first bit line of the even-numbered bit line pair
In the second block.
Indicates that the word line in the odd column is the first bit line pair of the odd line.
Memory cells connected to the bit line, and the bits in the even rows
Connected to the memory cell connected to the second bit line of the line pair.
In the third block, word lines of odd columns are used.
Connected to the second bit line of the odd-numbered bit line pair.
Memory cell and second bit line of bit line pair in even row
Is connected to the memory cell connected to
In the block, word lines in odd columns are paired with bit lines in odd rows.
Memory cell connected to the second bit line of
A memory cell connected to the first bit line of the bit line pair of the row
Connected to the memory cell array.
For the entire first to fourth blocks configured in the column direction,
And a reference voltage is applied to each of the plurality of bit line pairs.
Multiple reference potentials to giveOutbreakMeans,
The reference potential generating means is connected to a plurality of bit line pairs.
And connecting to the second bit line of the bit line pair in the odd-numbered row,
For connecting to the second bit line of the bit line pair in the even row.
A first reference word line and the reference potential
The generation means is used to select the bit of the odd-numbered row of the plurality of bit line pairs.
Connected to the first bit line of the line pair, and
A second reference wire for connecting to the first bit line;
The lead line and the reference potential generating means are connected to a plurality of vias.
Of the odd-numbered bit line pairs of the bit line pairs
And connected to the first bit line of the even-numbered bit line pair.
A third reference word line for
A plurality of bit line pairs of an odd number
Connected to the first bit line of the bit line pair in the row, and
A fourth reference for connecting to the second bit line of the
And a reference word line. [0029] Embodiments of the present invention will be described below.
You. FIG. 1 shows a semiconductor memory device according to a first embodiment of the present invention.
Is shown. In this embodiment, compared to the conventional one shown in FIG.
Therefore, the configuration of the dummy cell is different. Dummy word line
DWL₀~ DWL_ThreeDepends on the position of the selected word line.
And one of the four is selected. Each dummy
Dummy cells are arranged on the word lines as shown in the figure.
In addition, these dummy word lines DWL₀~ DWL_ThreeIs
Difference CP_FourAre arranged on both sides of the. In addition, each
Locks ad are row address RA_i, RA_j(I ≠
j) Block a: RA_i= RA_j= 0 Block b: RA_i= 0, RA_j= 1 Block c: RA_i= 1, RA_j= 0 Block d: RA_i= RA_j= 1 And the word line WL₀, WL₀', W
L₁, WL₁', ... are the row addresses RA_k(K ≠
i, k ≠ j), WL₀, WL₁, WL_Two, WL_Three, ...: RA_k= 0 WL₀', WL₁', WL_Two', WL_Three´,…: RA
_k= 1 Is assumed to be decoded as follows. In this embodiment, the selected word is
Corresponding to the dummy word line DWL₀~ DWL_ThreeTo
The following may be selected. In block a WL₀Is selected: DWL₀ WL₀'Is selected: DWL₁ In block b WL₁Is selected: DWL_Two WL₁'Is selected: DWL_Three In block c WL_TwoIs selected: DWL₁ WL_Two'Is selected: DWL₀ In block d WL_ThreeIs selected: DWL_Three WL_Three'Is selected: DWL₂ These are the row address RA_i, RA_j, RA_k
Select dummy word line as follows for the value of
Means to do. [0031] [Table 1]FIG. 2 shows an example of realizing such an operation. This
As a result, the dummy word line drive
Dynamic transistor T₀~ T_ThreeOne of the gates
"H" level and the dummy word line rise signal φ_R
Rises with the rise of the corresponding dummy word line
It becomes a selection state. As described above, according to the present embodiment, the conventional
Dummy cells and dummy words exactly the same as the Miesel method
One line (for two dummy word lines), intersection CP_Four
Include intersections easily by additionally arranging
A dummy cell method applicable to the bit line method is realized.
it can. In the above description, the word line WL₀,
WL₀'Represents a word line in block a as a representative.
This is for other word lines in block a.
Is exactly the same as for the other blocks.
You. The position of the dummy word line is
The position is not limited to the position and may be on both sides of another intersection. Ma
In the above embodiment, the present invention is applied to the conventional apparatus shown in FIG.
However, the present invention is applicable to other devices such as FIGS.
Application is possible as well. FIG. 3 shows a semiconductor according to a second embodiment of the present invention.
1 shows a storage device. In this case, the dummy word line DWL
₂, DWL₃For the crossing bit lines
Every two consecutive bit lines,
One dummy cell per bit line pair
are doing. In this way, the dummy cell arrangement is
Changes on one side of the intersection
Me word line DWL₀~ DWL₃And arrange four of them
Also, the dummy cell method can be realized without any trouble. Note that this
Also, the dummy word line DWL₀~ DWL₃Deco
The mode may be exactly the same as that in FIG. As described above, according to the first aspect of the present invention,
According to the semiconductor memory device, the plurality of columns and the plurality of rows are arranged.
Memory cell array having a plurality of memory cells
Arranged in multiple rows of memory cell array, each corresponding
Half of the memory cells arranged in the same row
Connected first bit line and second half connected to the other half
A plurality of bit line pairs including
Are arranged in multiple rows of the array, each in a corresponding row.
Multiple words connected to multiple memory cells arranged
In a semiconductor memory device having a line,
Rays are divided into multiple blocks in the column direction.
The blocks are odd columns in the block., Each of the even columns
The word line is a first bit line of an odd-numbered bit line pair,
Connected to the memory cell connected to any of the bit lines
Or the first bit line of the even-numbered bit line pair,
Connected to the memory cell connected to any of the bit lines
Are different for each block.
Further, the potential of the memory cell is read on each bit line pair.
A reference to generate a reference potential for readout
Reference potential generating means, and reference potential generating means
Out of the bit line pairs in the odd-numbered rows of the plurality of bit line pairs.
Connected to one of the first and second bit lines,
Any one of the first and second bit lines of the bit line pair of several rows
Multiple reflexes with different connection combinations
The reference word line and the selected word line
Of which block is the word line, and
And whether it is an odd column or even column word line
Based on one of the plurality of reference word lines,
And a reference word line decoding means for selecting a book.
So that when a bit line pair includes an intersection,
Semiconductor memory device to which the dummy cell method can be applied.
Has the effect. In addition, a half according to the invention of claim 2 of the present application.
According to the conductor storage device, a plurality of columns and a plurality of rows are arranged.
Number of memory cellsDoMemory cell array, the above memory
Arranged in multiple rows of cell array, each corresponding row
Half of the memory cells arranged in
The first bit line and the second bit to which the other half are connected.
And a plurality of bit line pairs,
B are arranged in multiple rows, each of which is
Multiple word lines connected to multiple memory cells
eSemiconductor memory device, the memory cell array
Is divided into the first to fourth four blocks in the column direction.
In the first block, the odd columns of words
Line connected to the first bit line of an odd row bit line pair
Memory cell and first bit of bit line pair in even row
Connected to the memory cell connected to the
In the block of, the word line of the odd column is replaced with the bit of the odd row.
A memory cell connected to the first bit line of the line pair; and
Note connected to the second bit line of the bit line pair in the even-numbered row
Connected to the recell, and in the third block,
The odd-numbered word line is the second bit of the odd-numbered bit line pair
Memory cells connected to lines, and bit line pairs in even rows
Connected to the memory cell connected to the second bit line
In the fourth block, word lines in odd columns are
Note connected to the second bit line of the bit line pair of the odd-numbered row
Resel, and the first bit line of the even-numbered bit line pair.
Connected to the connected memory cell, and
On each bit line pair, there is a level for reading the memory cell potential.
Reference potential generation to generate reference potential
Means and the reference potential generating means,
Of the bit line pairs in the odd-numbered row
Connected to the second bit line of the bit line pair in the even row.
A first reference word line for
The sense potential generating means is connected to the odd-numbered row of the plurality of bit line pairs.
Connected to the first bit line of the bit line pair of
A second reference for connecting to the first bit line of the
A reference word line and the reference potential generating means,
Among the plurality of bit line pairs, the second of the odd-numbered bit line pairs
Connected to the bit line, and First bit
A third reference word line for connecting to the
The reference potential generating means is connected to a plurality of bit line pairs.
That is, the odd-numbered bit line pair is connected to the first bit line,
A fourth for connecting to the second bit line of the bit line pair of the row
Reference word line and the selected word line
The word line of any of the blocks
And whether the word line is an odd column or an even column
Based on the information, the first to fourth reference
Reference word line data to select one of the
Code meansAre provided, so that the bit line pair
Semiconductors to which the dummy cell method can be applied even when differences are included
There is an effect that a storage device can be obtained. Claim 3 of the present application
According to the semiconductor memory device of the invention, a plurality of columns and a plurality of rows are provided.
Have multiple memory cellsAnd the first in the row direction
Divided into four fourth blocksMemory cell array
A, arranged in a plurality of rows of the memory cell array,
Of the memory cells arranged in the corresponding row.
The first bit line to which half is connected and the other half are connected
A plurality of bit line pairs comprising a second bit line
Arranged in multiple columns of memory cell array, each corresponding
Connected to multiple memory cells arranged in a fixed column
Equipped with word linesAnd the plurality of word lines
It is divided into blocks corresponding to the blocks,The first block
In the memory block, word lines in odd columns are connected to bit line pairs in odd rows.
Memory cells connected to the first bit line, and even rows
Cell connected to the first bit line of the pair of bit lines
And in the second block, an odd column
Are connected to the first bit line of the odd-numbered bit line pair.
Connected memory cells and the second of the even-numbered bit line pairs.
Is connected to the memory cell connected to the bit line of
In the third block, the odd-numbered word lines are arranged in odd-numbered rows.
Memory cell connected to the second bit line of the bit line pair
Connected to the second bit line of the bit line pair in the even-numbered row.
Connected to the memory cell, and the fourth block
In the memory cell, the odd-numbered word lines are connected to the odd-numbered bit line pairs.
Memory cells connected to two bit lines, and
A memory cell connected to the first bit line of the bit line pair;
Connected,Columns of the above memory cell array
Corresponding to the entire first to fourth blocks
And a reference potential is applied to each of a plurality of bit line pairs.
More to giveReference potential generating means,
The reference potential generating means is connected to a plurality of bit line pairs.
That is, the odd-numbered bit line pair is connected to the second bit line,
The second bit line for connecting the bit line pairs
1 reference word line and the reference potential
Generating means for the odd-numbered bit lines of the plurality of bit line pairs.
Connected to the first bit line of the pair, and
Second reference word for connecting to one bit line
Line and the reference potential generating means are connected to a plurality of bits.
Of the bit line pairs in the odd-numbered row
Connected to the first bit line of the even-numbered bit line pair.
A third reference word line for
The sense potential generating means is connected to the odd-numbered row
Connected to the first bit line of the bit line pair of
A fourth reference for connecting to the second bit line of the line pair
Word lineAndThe bit line pair
Semiconductors to which the dummy cell method can be applied even when intersections are included
The effect of obtaining a body memory device isYou.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a dummy word line decode according to the present invention. FIG. 3 is a configuration diagram showing a semiconductor memory device according to a second embodiment of the present invention. FIG. 4 is a configuration diagram of a conventional semiconductor memory device. FIG. 5 is a diagram for explaining a memory cell capacity of a conventional semiconductor memory device. FIG. 6 is a configuration diagram of a conventional semiconductor memory device having a bit line pair intersection. FIG. 7 is a configuration diagram of a conventional semiconductor memory device having a bit line pair intersection. FIG. 8 is a configuration diagram of a conventional semiconductor memory device having a bit line pair intersection. FIG. 9 is a configuration diagram when a dummy cell method is applied to a conventional semiconductor memory device having a bit line pair intersection. [Reference Numerals] SA the sense _{amplifier, CP 1, CP 2, CP} 3 intersections, CP ₄ bit line end intersection, a, b, c, d blocks, BL _0, ... bit lines, WL _0, ... word lines ,
DWL ₀ , ... Dummy word line.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References Patent No. 3014316 (JP, B2) Japanese Patent Publication No. 7-13851 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/401

Claims (1)

(57) [Claims] A memory cell array having a plurality of memory cells arranged in a plurality of columns and a plurality of rows, and a half of a plurality of memory cells arranged in a plurality of rows of the memory cell array and each arranged in a corresponding row is connected. A plurality of bit line pairs each including a first bit line to be connected and a second bit line to which the other half are connected, are arranged in a plurality of columns of the memory cell array, and are respectively arranged in corresponding columns. In a semiconductor memory device having a plurality of word lines connected to a plurality of memory cells, the memory cell array is divided into a plurality of blocks in a column direction, and the plurality of blocks are an odd-numbered column , an even-numbered number in the block. Column
Whether each word line is connected to the memory cell connected to the first bit line or the second bit line of the bit line pair in the odd-numbered row, or the first bit line or the The combination of which of the two bit lines is connected to the memory cell is different for each block, and a reference potential for reading the memory cell potential is generated on each bit line pair. Potential generating means for connecting to one of the first and second bit lines of a bit line pair in an odd row among a plurality of bit line pairs, or A plurality of reference word lines, which are different from each other in a combination of a first bit line and a second bit line of a bit line pair, and a selected word line is one of the plurality of blocks. Reference word line decoding means for selecting one of the plurality of reference word lines based on information as to whether the block is a word line of any one of the blocks and a word line of an odd column or an even column. A semiconductor memory device comprising: 2. Has multiple memory cells arranged in multiple columns and multiple rows
A first bit line connected to a half of a plurality of memory cells arranged in a plurality of rows of the memory cell array, each of which is connected to a corresponding row, and a remaining half connected to a first bit line A plurality of bit line pairs each including a second bit line; and a plurality of word lines arranged in a plurality of columns of the memory cell array and connected to a plurality of memory cells each arranged in a corresponding column . In the semiconductor memory device, the memory cell array includes first to fourth fours in a column direction.
In the first block, word lines in odd columns are divided into odd rows.
Memory cell connected to the first bit line of the bit line pair
Connected to the first bit line of a bit line pair in an even row
In the second block, word lines in odd columns are connected to odd rows.
Memory cell connected to the first bit line of the bit line pair
Connected to the second bit line of the bit line pair in the even-numbered row.
In the third block, word lines in odd columns are connected to odd rows.
Memory cell connected to the second bit line of the bit line pair
Connected to the second bit line of the bit line pair in the even-numbered row.
In the fourth block, word lines of odd columns are connected to odd rows.
Memory cell connected to the second bit line of the bit line pair
Connected to the first bit line of a bit line pair in an even row
Connected to the selected memory cell, and further read the memory cell potential on each bit line pair.
For generating a reference potential for
A plurality of bit line pairs.
And connecting to the second bit line of the bit line pair in the odd-numbered row,
For connecting to the second bit line of the bit line pair in the even row.
A first reference word line and the reference potential generating means are connected to a plurality of bit line pairs.
And connecting to the first bit line of the odd-numbered bit line pair,
For connecting to the first bit line of the bit line pair in the even row
A second reference word line and the reference potential generating means are connected to a plurality of bit line pairs.
And connecting to the second bit line of the bit line pair in the odd-numbered row,
For connecting to the first bit line of the bit line pair in the even row
A third reference word line and the reference potential generating means are connected to a plurality of bit line pairs.
Of these, the odd-numbered bit line pair is connected to the first bit line and the
The for connection to the second bit line of lines of the bit line pairs
4 and the selected word line are connected to any one of the plurality of blocks.
Whether it is the word line of the block and whether it is an odd or even column
Based on the information as to whether or not the word line is shifted, the first
Select one of the fourth reference word lines
And a reference word line decoding means . 3. Has multiple memory cells arranged in multiple columns and multiple rows
And divided into the first to fourth four blocks in the column direction.
A memory cell array is disposed in a plurality of rows of upper Symbol memory cell array, each the first bit line and the remaining half of half is connected among the plurality of memory cells arranged in rows corresponding connection a plurality of bit line pairs and a second bit line being, on SL are arranged in a plurality of columns of memory cell array, a plurality of word lines, each connected to a plurality of memory cells arranged in rows corresponding comprising a plurality of word lines corresponding to the plurality of blocks
In the first block, a memory cell in which a word line in an odd column is connected to a first bit line of a bit line pair in an odd row, and a first bit line in a bit line pair in an even row In the second block, a word line in an odd column is connected to a first bit line of a bit line pair in an odd row, and a bit in an even row is connected in the second block. In the third block, the word lines in the odd columns are connected to the second bit lines in the bit lines in the odd rows. The memory cell is connected to a memory cell connected to the second bit line of the bit line pair of the even-numbered row. In the fourth block, the word line of the odd-numbered column is connected to the memory cell connected to the second bit line of the odd-numbered bit line pair. Memory cell connected to two bit lines And even are connected to the memory cells connected to the first bit line of the bit line pairs of lines, further, the formed in the column direction of the memory cell array
Arranged corresponding to the entire first to fourth blocks,
To apply a reference potential to each bit line pair of
And reference potential generating means, said reference potential generating means, among the plurality of bit line pairs, connected to the second bit line of the bit line pairs in an odd row,
A first reference word line for connecting to a second bit line of the even-numbered bit line pair; and a reference potential generating means, the first reference word line being connected to the first bit line pair of the odd-numbered bit line among the plurality of bit line pairs. Connect to the bit line,
A second reference word line for connecting to a first bit line of an even-numbered bit line pair; and a reference potential generating unit, the second reference word line being connected to a second one of an odd-numbered bit line pair of the plurality of bit line pairs. Connect to the bit line,
A third reference word line for connecting to a first bit line of an even-numbered bit line pair; and a reference potential generating means, the first bit of an odd-numbered bit line pair of a plurality of bit line pairs. connected to the line, the semiconductor memory device is characterized in that a fourth reference word line for connection to the second bit line of the bit line pairs in an even row.