JPH05182470A - Semiconductor multi-valued memory - Google Patents

Abstract

PURPOSE:To provide a semiconductor multi-valued memory discriminating the reading signals of all memory cells driven by the same word line and equalizing the condition of a signal route between the reading signal and a reference signal. CONSTITUTION:This memory is provided with six pieces of sub arrays SAA, SAB constituted by containing a data line DA or DB connected with the memory cell MC and a dummy data line DDA, DDB connected with a dummy cell DC, and they are connected to a multi-valued sense circuit MSC through data generatrices GDA, GDB. Then the reading signal from the data line in the sub memory array SAA and the reference signal from the DB in the SAB are transmitted to the multi-valued sense circuit MSC simultaneously. Thus, the balance of the signal route is taken to the reading signal and the reference signal, and the semiconductor multi-valued memory with high S/N is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor multi-valued memory which stores multi-valued information in a memory cell, and more particularly to a semiconductor multi-valued memory which is suitable for high integration density and high S / N.

[0002]

2. Description of the Related Art In a semiconductor multi-level memory in which memory cells store N-value information of three or more values, to discriminate information of memory cells in which N-values are written, there are (N-1) kinds of information. It is necessary to judge the magnitude of the read signal with respect to the reference signal. The method of generating a reference signal using a dummy cell is
It is disclosed in JP-A-61-117796. In order to perform a high S / N read operation, the noise contained in the read signal must be canceled by the reference signal. Therefore, it is necessary to make the signal path from the memory cell and the signal path from the dummy cell have the same condition. In the above-mentioned invention, as a third embodiment shown in FIG. 3, the number of memory cells and dummy cells connected to the data line, the noise generation state at the time of driving the word line, the presence / absence of passage through the column selection circuit, the number of connected comparison circuits. The configuration is shown under the same conditions for all of.

[0003]

However, the above invention does not mention the method for discriminating the read signals of all the memory cells driven by the same word line.
In a memory cell for destructive reading such as a one-transistor / one-capacitor cell of a DRAM, read-out signals of all memory cells simultaneously selected by one word line must be determined for rewriting. (N-1) comparator circuits are required to determine the information of one memory cell. In general, the layout pitch of the comparison circuit is much larger than that of the memory cells. Therefore, it is impossible in terms of layout to provide (N-1) times as many comparators as the number of memory cells selected in the same manner. The above invention uses a non-destructive read-out memory cell such as a ROM, selects a part from a large number of memory cells driven by the same word line, and discriminates only the read-out signal. Becomes

It is also stated that both the read signal and the reference signal go through the column selection circuit and the conditions are the same.
No mention is made of the construction of the column selection circuit. The conditions such as parasitic capacitance are different in the column selection circuit, which may lead to a decrease in S / N.

The present invention has been made to solve these problems of the prior art. That is, the object of the present invention is to read the read signals of all the memory cells driven by the same word line, and read the read signal and the reference signal at the same signal path condition with high S / N. It is to realize a semiconductor multi-valued memory that operates.

[0006]

The features of the present invention for achieving the above-mentioned object are that a plurality of data lines divided into two groups of an equal number and a plurality of word lines arranged so as to intersect with them. And a memory cell which is arranged at a desired intersection of the data line and the word line and stores and holds at least three-valued m-value information, and when the word line is driven, the data is output from the memory cell to the data line. A multi-valued sense circuit for discriminating read signals and a plurality of dummy cells for generating (m-1) types of reference signals used for discriminating m values are provided, and read signals are read from all memory cells on a selected word line. Are read to the corresponding data lines, the read signals read to the data lines of one group are sequentially input to the multi-valued sense circuit in units of at least (m-1), and the read signals of the other group. Is to be compared with the reference signal read said read Heading from the number as many dummy cell signal to the data lines.

[0007]

The read signals of all memory cells driven by the same word line can be discriminated by sequentially selecting a fixed number of read signals of the memory cells read at the same time. Moreover, by comparing the same number of read signals and reference signals, it is possible to make the noise equal by canceling the noise by making the signal path conditions uniform, and it is possible to determine multi-valued information of the memory cell with a high S / N. ..

[0008]

EXAMPLES The present invention will be described below with reference to examples by taking the case of storing 2 bits, that is, 4 values in the memory cell MC as an example. In the following description, i = 1, 2, 3, j = 1,
A few.

FIG. 1 shows a first embodiment of the present invention. The data line of one group is DA and the data line of the other group is DB. Two groups of data lines DA,
The DB is further divided into three data line groups, and the memory array is divided into six sub arrays SAA (1) to SAA.
(3), SAB (1) to SAB (3).
The sub array SAA (i) or SAB (i) is configured as follows. A plurality of data lines DA or DB,
Memory cells MC are arranged at intersections with the plurality of word lines W. In addition, the dummy data line DDA or DDB
And a dummy cell DC (i) configured similarly to the memory cell MC is arranged at the intersection with the word line W. DDA
Since the memory cells are not connected and DDB is connected only to the dummy cells, DDB and DDB are called dummy data lines. DDA
Belongs to the same group as DA, and DDB belongs to the same group as DB. Dummy cell DC (i) is set to generate the i-th reference signal. Each data line and dummy data line are connected to the switch SW. These switches SW are selected and operated so that only one of them is turned on in each sub-array. The number of data lines for each sub-array shall be the same. The sub-array SAA (i) is on the data bus GDA (i) and SAB (j) is on GDB (j).
It is connected to the. A multi-valued sense circuit MSC is connected to the data buses GDA and GDB. The multi-level sense circuit MSC has nine comparators CP (1,1) to CP (3,
3) is included, and the comparator CP (i, j) is connected to the data buses GDA (i) and GDB (j).
In this figure, the X decoder, the Y decoder, etc. are omitted.

The read operation is performed as follows. By driving the word line W selected by an X decoder (not shown), a signal is read from the memory cell MC to each data line DA and DB in each sub-array SAA and SAB. At the same time, the reference signal is read from the dummy cell DC to the dummy data lines DDA and DDB. Here, the switch SW is sequentially switched, and the read signal is determined by the multi-valued sense circuit MSC in units of three. The read signals are input to the multi-valued sense circuit MSC one by one from the three sub-arrays SAA or SAB for discrimination. The order can be set arbitrarily. The read signal appearing on the data line DA in the sub array SAA is discriminated by comparing with the reference signal appearing on the dummy data line DDB in the sub array SAB. The read signal appearing on the data line DB in the sub array SAB is discriminated by comparing with the reference signal appearing on the dummy data line DDA in the sub array SAA. For example, in the sub-array SAA (i), one of the switches connected to the data line DA is turned on to turn on the data line D.
The read signal appearing at A is transmitted to the data bus GDA (i). In addition, the switch connected to the dummy data line DDB in the sub-array SAB (j) is turned on to transmit the reference signal to the data bus GDB (j). FIG. 1 shows the state of the switch SW at this time. By the comparator CP (i, j) in the multi-valued sense circuit MSC, the data bus G
The read signal transmitted to DA (i) is compared with the reference signal transmitted to GDB (j). As a result, the read signal transmitted from the sub-array SAA is discriminated by the multi-valued sense circuit MSC. The multi-valued sense circuit MSC is selected by a Y decoder (not shown), and the determination result of the read signal of the desired memory cell is output.

As described above, the read signals appearing on the data lines are sequentially input to the multi-valued sense circuit MSC to make a time-series determination, thereby reading all the memory cells MC on the selected word line W. Even if signals are discriminated, the number of multi-valued sense circuits MSC can be small. As a result, the layout pitch of the multi-valued sense circuit MSC is large and sufficient layout is possible.

In this structure, the data lines and the dummy data lines have the same structure of the memory cell MC and the dummy cell DC and have the same line length, so that the electrical balance such as parasitic capacitance can be maintained. Since the memory cell MC and the dummy cell DC are selected by the same word line, the noise coupled from the word line is the same for the data line and the dummy data line. In addition, the data bus has
Since the same number of switches SW and three comparators CP are connected to each other, they can be electrically balanced by equalizing the line lengths. As a result, the multi-valued sense circuit MSC is changed from the memory cell MC and the dummy cell DC.
Can be balanced for all signal paths up to, and the noise components included in the read signal and the reference signal can be the same. Since the common noise component is removed by the comparator, high S / N reading can be realized.

In FIG. 1, the sub array SAA (1) is used.
-SAA (3), sub-array SAB (1) -SAB
Although they are arranged in the order of (3), the arrangement on the chip is not limited to this. For example, SAA and SAB may be arranged alternately. Although the data lines and the dummy data lines are arranged in this order in the sub-array, the actual arrangement is not limited to this. For example, an arrangement different from that of FIG. 1 may be adopted, such as providing dummy data lines between a plurality of data lines.

FIG. 2 shows a second embodiment of the present invention. First
In this embodiment, one read signal or one reference signal is transmitted from each sub-array to the multilevel discriminator circuit. In this embodiment, however, three read signals are simultaneously discriminated from one subarray. Transmitted to the circuit. Further, the dummy cells DC are dispersed in the respective sub-arrays in the first embodiment, but in this embodiment, they are concentrated and arranged in the sub-array which does not include the memory cells, that is, the dummy sub-array.
The same number of sub-arrays SAA and SAB are provided, and dummy sub-arrays DSAA and DSAB are provided. The sub-array SAA or SAB is configured as follows, respectively. A memory cell MC is arranged at an intersection of three data lines DA (1) to DA (3) or DB (1) to DB (3) and a plurality of word lines W. Each data line DA
Alternatively, the switch SW is connected to DB. These switches SW perform the same operation for each sub array.
The dummy sub array DSAA or DSAB is configured as follows. Three dummy data lines DDA (1)-
DDA (3) or DDB (1) to DDB (3) are provided, and the dummy data line DDA (i) or DDB
At the intersection of (i) and the word line W, the dummy cell DC
(I) is provided. Dummy cell DC (i) is set to generate the i-th reference signal. A switch SW is connected to each dummy data line DDA or DDB. Sub array SAA and dummy sub array DSAA
Are connected to the data buses GDA (1) to GDA (3), and SAB and DSAB are GDB (1) to GDB (3).
It is connected to the. Data bus GDA (1) to GDA
A multi-valued sense circuit MSC is connected to (3) and GDB (1) to GDB (3) as in FIG. In this figure, the X decoder, the Y decoder, etc. are omitted.

The read operation is performed as follows. By driving a certain word line W, a signal is read from the memory cell MC to the data lines DA and DB in each sub-array SAA and SAB. At the same time, the reference signal is read from the dummy cell DC to the dummy data lines DDA and DDB. Here, the switch SW is sequentially switched for each sub-array, and the read signal is discriminated by the multi-valued sense circuit MSC in units of three. 1 sub array SA
Three read signals from A or SAB are input to the multi-level sense circuit MSC for determination. The order of selecting subarrays can be set arbitrarily. The read signal appearing on the data line DA in the sub array SAA is discriminated by comparing it with the reference signal appearing on the dummy data line DDB in the dummy sub array DSAB. On the other hand, the read signal appearing on the data line DB in the sub array SAB is discriminated by comparing with the reference signal appearing on the dummy data line DDA in the dummy sub array DSAA. For example, a subarray SAA
Turn on the three switches SW in the data line DA
The read signal appearing at (i) is transmitted to the data bus GDA (i). In addition, the three switches SW are turned on in the dummy sub-array DSAB to turn on the dummy data line DDB.
The reference signal appearing at (j) is transmitted to the data bus GDB (j). FIG. 2 shows the state of the switch SW at this time. Comparator CP (i, in the multi-valued sense circuit MSC
j), the read signal transmitted to the data bus GDA (i) is compared with the reference signal transmitted to GDB (j). As a result, the read signal transmitted from the sub-array SAA is discriminated by the multi-valued sense circuit MSC.

This embodiment is different from the first embodiment in the arrangement of data lines and dummy data lines. The first embodiment is characterized in that the configurations are logically the same, the layout pitch of the multi-valued sense circuit MSC is sufficiently large, and the noise can be canceled by adjusting the conditions of the signal paths of the read signal and the reference signal. Is the same as. In this embodiment, since each sub array is connected to the data bus, the switch S
A W control line may be provided for each sub-array, which facilitates layout.

Although the sub array SAA, the dummy sub array DSAA, the sub array SAB, and the dummy sub array DSAB are arranged in this order in FIG. 2, the arrangement on the chip is not limited to this. For example, a dummy sub array DSAB is provided in the middle of the sub array SAA, and a DS is provided in the middle of the SAB.
AA may be arranged. In such an arrangement, since the distance on the chip between the sub-array that generates the read signal and the dummy sub-array that generates the reference signal at that time is small, the difference in the noise component due to the difference in the position is small, and the high S / Can be converted to N.

FIG. 3 shows a third embodiment of the present invention. In this example, the data lines are paired and the memory cells are arranged at two intersections. A plurality of sub-arrays SA configured as follows are provided. Six data lines DA are intersected with the plurality of word lines WA and WB and the two dummy word lines DWA and DWB.
(1) to DA (3) and DB (1) to DB (3) are arranged. Memory cells MC are provided at the intersections of the data lines DA and the word lines WA and at the data lines DB and the word lines WB. Dummy cells DC (i) are provided at the intersections of the data lines DA (i) and the dummy word lines DWA and the intersections of the data lines DB (j) and the dummy word lines DWB. DWA
And DWB do not select the memory cell MC but only the dummy cell DC, and are therefore referred to as dummy word lines here. Dummy cell DC (i) is set to generate the i-th reference signal. Each data line DA or DB
The switch SW is connected to. Six switches SW perform the same operation for each sub-array. Sub array SA
Is a data bus GDA (1) to GDA (3), GDB
(1) to GDB (3). Data bus GDA
(1) to GDA (3), GDB (1) to GDB (3)
Are connected to the multi-valued sense circuit MSC having the same configuration as in FIG. In this figure, the X decoder, the Y decoder, etc. are omitted.

For example, the read operation of the memory cell MC connected to the data line DA is performed as follows. By driving the word line WA, a signal is read from the memory cell MC to the data line DA in each sub array SA. Further, by driving the dummy word line DWB, three dummy cells DC connected to DWB in each sub-array
To the data line DB, the reference signal is read out.
Here, the switch SW is sequentially switched for each sub-array SA, and the read signal is discriminated by the multi-valued sense circuit MSC in units of three. The order of selecting subarrays can be set arbitrarily. The six switches SW of a certain sub-array SA are turned on, and the read signal appearing on the data line DA (i) is transferred to the data bus GDA (i) and the data line DB.
The reference signal appearing at (j) is transmitted to the data bus GDB (j). FIG. 3 shows the state of the switch SW at this time. Comparator CP (i, in the multi-valued sense circuit MSC
j), the read signal transmitted to the data bus GDA (i) is compared with the reference signal transmitted to GDB (j). As a result, the read signal transmitted from the sub array SA is discriminated by the multi-valued sense circuit MSC.

Memory cell MC connected to data line DB
The read operation is also performed in the same manner. In that case, the word line WB
To read a signal from the memory cell MC to the data line DB and drive the dummy word line DWA to drive the data line DA.
Then, the reference signal is read from the dummy cell DC.

In the first and second embodiments, the dummy cell DC is connected to the dummy data line DD and selected by the same word line as the memory cell MC. Therefore, in order to make the conditions of the data line D and the dummy data line DD the same, the dummy cell DC must have the same configuration as the memory cell MC. On the other hand, in this embodiment, the dummy cell DC is connected to the same data lines DA and DB as the memory cell MC and selected by the dummy word lines DWA and DWB. Therefore, even if the dummy cell DC is configured differently from the memory cell MC, the conditions for the data lines can be the same.
Further, since the reference signal generated in the same sub-array as the read signal is used, there is no difference in noise component due to the difference in position, and high S / N can be achieved.

In the first and second embodiments, the ratio of the number of memory cells MC to the number of dummy cells DC depends on how many times the memory cells MC on one word line are divided in time series. Determined. On the other hand, in this embodiment, it depends on how many memory cells MC can be provided on one data line. Therefore, in some cases, this embodiment requires a smaller number of dummy cells and a smaller chip area. The degree of integration increases. Further, in a normal binary DRAM, the memory cells are generally arranged at two intersections. Therefore, in the configuration in which the memory cells are arranged at two intersections as in this embodiment, the same memory cell structure as that of the binary DRAM can be obtained and the same process can be performed. Is easy to manufacture.

FIG. 4 shows a fourth embodiment of the present invention. Applying the concept shown in Japanese Patent Application No. 2-159665 to the present invention, FIG.
It is an example in which the data lines in the first embodiment shown in FIG. 6 blocks BLKA (1) to BLKA
(3) and BLKB (1) to BLKB (3) are provided. The arrangement of the blocks on the chip is not limited to the order shown in FIG. Block BLKA (i) or BLKB
(I) is configured as follows. A common data line CDA (i) or CDB (i) is provided for each block. Common data line CDA (i) or CDB (i)
, A plurality of sub-arrays SAA (i) or SAB (i) are connected to each other via signal transmission means DS.
Each sub-array SAA (i) or SAB (i) is configured as shown in FIG. The blocks BLKA (i) and BLKB (i) having such a configuration are connected via the buffer circuit BUF and the common switch SWC or SWD.
Data bus GD (i) and dummy data bus DGD (i)
Connected to. A multi-valued sense circuit MSC is connected to the data bus lines GD (1) to GD (3) and the dummy data bus lines DGD (1) to DGD (3). Multi-valued sense circuit MSC
Is composed of nine comparators CP (1,1) to CP (3,3), and the comparator CP (i, j) is a data bus GD.
(I) and the dummy data bus DGD (j). In this figure, the X decoder, the Y decoder, etc. are omitted.

The read operation is performed as follows. By driving a certain word line, each block BLKA, BL
In the KB, a signal is read from the memory cell to the data line DA or DB in any sub array SAA or SAB, and at the same time, a reference signal is read from the dummy cell to the dummy data line DDA or DDB. The read signals are input from the three blocks BLKA or BLKB one by one to the multi-valued sense circuit MSC, and the multi-valued sense circuit MSC discriminates by using three read signals as a unit. The order can be set arbitrarily. The read signal in the block BLKA is determined by comparing it with the reference signal in the block BLKB. On the other hand, the read signal in the block BLKB is determined by comparing with the reference signal in the block BLKA. However, the read signal is transmitted to the data bus GD and the reference signal is transmitted to the dummy data bus DGD by the common switches SWC and SWD. For example, block BLKA (i)
One of the switches SW connected to the data line DA in the sub-array SAA (i) therein is turned on, and the read signal appearing on the data line DA is transferred via the signal transmission means DS to the common data line CDA (i. ). The signal transmitted to CDA (i) is further transmitted to data bus GD (i) via buffer circuit BUF and common switch SWC. Also, the sub-array SA in the block BLKB (j)
The switch SW connected to the dummy data line DDB in B (j) is turned on, the reference signal is passed through the signal transmission means DS through the common data line CDB (j), and further through the buffer circuit BUF and the common switch SWD. It is transmitted to the dummy data bus DGD (j). FIG. 4 shows the states of the switch SW and the common switches SWC and SWD at this time. The comparator CP (i, j) in the multi-valued sense circuit MSC compares the read signal transmitted to the data bus GD (i) with the reference signal transmitted to the dummy data bus DGD (j). As a result, the read signal transmitted from the sub-array SAA is discriminated by the multi-valued sense circuit MSC.

In this embodiment, one multi-valued sense circuit MSC is provided for six blocks. Since each block is composed of a plurality of sub-arrays, more sub-arrays share the multi-valued sense circuit than in the first embodiment. Since the multi-valued sense circuit MSC includes nine comparators CP, it has a large area. However, the multi-valued sense circuit MSC shares a large number of data lines with a small number, and the occupied area can be reduced. Although a common data line is added, the layout is easy because the layout can be made at the pitch of the sub array.
Further, since the common data line is shared by the plurality of sub-arrays, the area increase is small even if the buffer circuit BUF is provided for each common data line. By the buffer circuit BUF, the capacitance such as the input capacitance of the comparator CP connected to the data bus is
Since it is separated from the common data line, the read operation is performed at high speed. Moreover, similar to the first embodiment, the multi-valued sense circuit M is connected to the memory cell MC and the dummy cell DC.
The signal path to the SC is well balanced and the S / N ratio is high.
Read out can be realized. Although this embodiment has a configuration based on the first embodiment, the second embodiment and the third embodiment similarly apply the concept shown in Japanese Patent Application No. 2-159665 to obtain data. By hierarchizing the lines, a multi-valued sense circuit can be shared by many sub-arrays.

In this embodiment, the common switches SWC and S
By providing WD, the read signal is always transmitted to the data bus GD and the reference signal is always transmitted to the dummy data bus DGD. Therefore, the combination of comparators for discriminating one read signal in the multi-level sense circuit MSC is the block BL.
The same is true for the signal read in KA and for the signal read in BLKB. Therefore, it is easy to process the output signal of the comparator.

A specific circuit configuration and operation will be described below by taking the fourth embodiment as an example. 4 that are the same as those in FIG. 4 indicate the same parts.

FIG. 5 is a diagram showing the configuration of the block BLKA (1). Block BLKA (2), BLKA
(3) has the same configuration as BLKA (1) and is controlled by the same control pulse. A memory cell MC including one NMOS transistor and one storage capacitor is provided at each intersection of the plurality of word lines W and the plurality of data lines DA. At the intersection of the word line W and the dummy data line DDA, the dummy cell DC having the same structure as the memory cell MC is formed.
A plurality of (1) are provided. The plurality of data lines DA and the dummy data lines DDA are connected to the precharge circuit PD composed of NMOS transistors. Further, it is also connected to a switch circuit SWA composed of a plurality of NMOS transistors that operate as a switch SW. The sub array SAA (1) is configured as described above. Switch circuit SWA
Is connected to a signal transmission means DS composed of three NMOS transistors Q1 to Q3. The common precharge circuit PDA is connected to the gate terminal of the transistor Q1 in the signal transmission means DS. Transistors Q2 and Q3
The drain terminal of is connected to the common data line CDA (1).

FIG. 6 is a diagram showing the structure of the block BLKB (1). Sub-array SAB (1) is SAA (1)
The data line is called DB, the dummy data line is called DDB, and the common data line is called CDB (1). Further, instead of the common precharge circuit PDA controlled by the control pulse FPDA, a common precharge circuit PDB controlled by the control pulse FPDB is provided. Instead of the switch circuit SWA controlled by the control pulses FSAD, FSA (1) to FSA (t), control pulses FSBD,
A switch circuit SWB controlled by FSB (1) to FSB (t) is provided. That is, the block BLKB
(1) has the same configuration as BLKA (1), but the control pulse is different. Block BLKA (2), B
LKB (3) has the same configuration as BLKB (1) and is controlled by the same control pulse.

As shown in FIGS. 5 and 6, each subarray does not include a PMOS transistor and does not require an n-type well. Therefore, no well isolation region is needed.

FIG. 7 is a diagram showing a buffer circuit BUF and the like connected to the block BLKA (1). The blocks BLKA (2) and BLKA (3) are also connected to circuits having the same configuration and controlled by the same control pulse. The common data line CDA (1) is connected to the buffer circuit BUF and the write switch SWE. Buffer circuit BUF
Is composed of two PMOS transistors Q4 and Q5 and a differential amplifier DAMP. The output terminal of the differential amplifier DAMP is connected to the data bus GD via the common switch SWC.
(1) and the dummy data bus DGD (1). In addition, the write switch SWE is also connected to the data bus GD.
(1) and the dummy data bus DGD (1).

FIG. 8 is a diagram showing a buffer circuit BUF and the like connected to the block BLKB (1). 7 has the same configuration as that of FIG. 7, but instead of the common switch SWC controlled by the control pulses FSC and FSCD, the control pulse FS
A common switch SWD controlled by D and FSDD is provided. Further, instead of the write switch SWE controlled by the control pulses FSE and FSED, the control pulse FS
A write switch SWF controlled by F and FSFD is provided. That is, in the block BLKB (1), B
A circuit having the same configuration as LKA (1) is connected, but the control pulse is different. Block BLKA (2), BL
A circuit having the same configuration as in FIG. 8 is also connected to KB (3) and controlled by the same control pulse.

FIG. 9 shows the structure of the multi-valued sense circuit MSC. The multi-valued sense circuits MSC connected to the data bus lines GD (1) to GD (3) and the dummy data bus lines DGD (1) to DGD (3) each have three multi-valued determination circuits MLR (1) having the same configuration. -MLR (3), register circuits MDR (1) -MDR (3), multi-value write circuit MLW
(1) to MLW (3) and common write switch circuit S
It is composed of WW. The multi-value discrimination circuit MLR (i) is composed of three comparators CP (i, j) connected to the data bus GD (i) and the dummy data bus DGD (j). The register circuit MDR (i) is composed of three registers DR (i, 1) to DR (i, 3) each storing a plurality of bits, and has comparators CP (i, 1) to CP (i, 3). The output signal of is input. These registers have a configuration (FIFO) in which the first input information is first output. The register circuit MDR (i) is a multilevel write circuit ML.
It is connected to the input terminal of W (i). Multi-value writing circuit ML
The output terminal of W (i) is a common write switch circuit SW
Data bus GD via NMOS transistor in W
Connected to (i). In addition, the reference signal voltage VREF
(J) is the NMO in the common write switch circuit SWW
Dummy data bus DGD via S-transistor
Connected to (j). Multi-value writing circuit MLW (1) to M
The LW (3) can be realized, for example, by the configuration as shown in FIG. 12 of Japanese Patent Application No. 2-322967 for four values.

FIG. 10 is a diagram showing the timing of the read operation for the specific configuration of the fourth embodiment shown in FIGS. 5 to 9. The read operation will be described using this.
In the standby state, control pulses FPD, FPDA, FPDB
Is a high potential VCC, and FSA (1) to FSA (t), F
SAD, FSB (1) to FSB (t), FSBD are used as the word line potential (VCC + α), and the data lines DA, DB and the dummy data lines DDA, DDB and the switch circuits SWA, SWB in each sub-array are set to the precharge potential VP. Precharge. First, control pulses FPD, FSA
(1) to FSA (t), FSAD, FSB (1) to FS
B (t) and FSBD are set to a low potential of 0V, the transistors in the precharge circuit PD and the switch circuits SWA and SWB are turned off, and the data lines DA and DB and the dummy data lines DDA and DDB are in a floating state of the precharge potential VP. And Next, the word line W selected by the X decoder (not shown) is raised to the word line potential (VCC + α), a signal is output from the memory cell MC connected thereto to the data lines DA and DB, and a reference signal is input from the dummy cell DC. The dummy data lines DDA and DDB are read. Here, the control pulse FDR is set to the high potential VCC and FBUF is set to the low potential 0V to activate the signal transmission means DS and the buffer circuit BUF.

At this time, the signal transmission means DS causes the NMOS
A current corresponding to the voltage input to the gate of the transistor Q1 flows into the transistor Q1 from the common data line CDA or CDB through the transistor Q2. That is, the signal voltage is converted into a signal current and output. Switch circuit SW
The input impedance of the signal transmission means DS viewed from A and SWB is large. Since the wiring capacitance of the common data line CDA or CDB is not added, the data line capacitance is small,
Since the read signal is large, the read operation is performed at a high S / N. The output current of the signal transmission means DS flows through the PMOS transistors Q4 to Q5 of the buffer circuit BUF. The voltage of the common data line CDA or CDB is input to the differential amplifier DAMP, differentially amplified with the bias potential VB, and the output is applied to the gate of the transistor Q4. By negative feedback, common data line CDA or CD
The input impedance of the buffer circuit BUF seen from B is small, and the potential of the common data line CDA or CDB becomes almost the same as the bias potential VB. Common data line CDA
Alternatively, since the potential fluctuation of CDB is small and the wiring capacitance is not charged / discharged, a signal is transmitted at high speed. The output voltage of the differential amplifier DAMP of the buffer circuit BUF is transmitted to the common switch SWC or SWD. That is, the output current of the signal transmission means DS is converted into a voltage by the buffer circuit BUF.

The read signal appearing on the data line DA in the sub-array SAA in the block BLKA is first discriminated. The control pulse FSCD is set to the high potential VCC, and the common switch S
The signal of the sub-array SAA (i) is transmitted to the data bus GD (i) by the WC. Further, the control pulse FSDD is set to the high potential VCC, and the signal of the sub array SAB (j) is transferred to the dummy data bus DGD by the common switch SWD.
It is transmitted to (j). The control pulses FPDA and FPDB are set to a low potential of 0 V to turn off the common precharge circuits PDA and PDB. FSA (1) is connected to the word line potential (VCC +
α), sub-array SAA (1) ~ SAA (3)
Then, the data line DA is connected to the signal transmission means DS by the switch circuit SWA. The read signal from the data line DA in the sub-array SAA (i) is read by the switch circuit SWA, the signal transmission means DS, the common data line CDA (i), the buffer circuit BUF, the common switch SWC, and the data bus GD (i).
Via the multivalued sense circuit MSC
Three comparators CP (i, 1) to CP (i, in R (i)
Input to 3). At the same time, FSBD is raised to the word line potential (VCC + α), and sub-arrays SAB (1) to SAB
At B (3), the signal transmission means D is generated by the switch circuit SWB.
The dummy data line DDB is connected to S. Sub array SA
The reference signal from the dummy data line DDA in B (j) is the switch circuit SWB, the signal transmission means DS, and the common data line C.
DB (j), buffer circuit BUF, common switch SW
D, through the dummy data bus DGD (j), the three comparators CP (1, j) to CP in the multi-valued sense circuit MSC.
Input to (3, j). The comparator compares the read signal with the reference signal, and the comparison result of MLR (i) is input to and stored in the register circuit MDR (i).
Then, the control pulse FSA (1) is set to a low potential of 0 V, and the data lines DA are set by the sub-arrays SAA (1) to SAA (3).
Is disconnected from the signal transmission means DS. Further, FPDA is raised to the high potential VCC, and the common precharge circuit PDA precharges the connection portion between the switch circuit SWA and the signal transmission means DS. Hereinafter, the control pulse FSA is changed to FSA.
Up to (t), the word line potential (VCC + α) is sequentially increased, the read signal on the data line DA is transmitted to the multi-valued sense circuit MSC, and the determination and the register circuit by the multi-valued determination circuits MLR (1) to MLR (3) are performed. The data is stored in MDR (1) to MDR (3). At this time, in order to add the influence of the coupling noise of the control pulse FSA to the reference signal, the control pulse FSBD is once set to the low potential 0V and the word line potential (VCC).
Repeat returning to + α). Then, the control pulse FS
BD, FSC, and FSDD are returned to low potential 0V. The control pulses FPDB and FPDA are set to the high potential VCC, and the common precharge circuits PDA and PDB are used to switch the switch circuit SW.
The connection portion between A and SWB and the signal transmission means DS is precharged.

Subsequently, the read signal appearing on the data line DB in the sub array SAB in the block BLKB is discriminated. The control pulse FSCD is set to the high potential VCC, and the signal of the sub array SAA (j) is transmitted to the dummy data bus DGD (j) by the common switch SWC. Further, the control pulse FSD is set to the high potential VCC, and the signal of the sub array SAB (i) is sent to the data bus GD by the common switch SWD.
Communicate to (i). The control pulses FPDA and FPDB are set to a low potential of 0 V to turn off the common precharge circuits PDA and PDB. FSB (1) is connected to the word line potential (VCC +
α), sub array SAB (1) ~ SAB (3)
Then, the data line DB is connected to the signal transmission means DS by the switch circuit SWB. The read signal from the data line DB in the sub-array SAB (i) is the switch circuit SWB, the signal transmission means DS, the common data line CDB (i), the buffer circuit BUF, the common switch SWD, the data bus GD (i).
Via the multivalued sense circuit MSC
Three comparators CP (i, 1) to CP (i, in R (i)
Input to 3). At the same time, FSAD is raised to the word line potential (VCC + α), and sub-arrays SAA (1) to SA
At A (3), the signal transmission means D is generated by the switch circuit SWA.
The dummy data line DDA is connected to S. Sub array SA
The reference signal from the dummy data line DDA in A (j) is the switch circuit SWA, the signal transmission means DS, and the common data line C.
DA (j), buffer circuit BUF, common switch SW
C, through the dummy data bus DGD (j), the three comparators CP (1, j) to CP in the multi-valued sense circuit MSC.
Input to (3, j). Each of the comparators compares the read signal and the reference signal, and the result is input to and stored in the register circuits MDR (1) to MDR (3). Next, regarding the sub arrays SAB (1) to SAB (3),
The control pulse FSB (1) is set to the low potential 0V, the FPDB is raised to the high potential VCC, and the common precharge circuit PDB precharges the connection portion between the switch circuit SWB and the signal transmission means DS. Hereinafter, the control pulse FSB is set to FSB.
The word line potential (VCC + α) is sequentially increased until (t), the read signal on the data line DB is transmitted to the multi-valued sense circuit MSC, and the multi-valued determination circuits MLR (1) to MLR (3) perform the determination and the register circuit. The data is stored in MDR (1) to MDR (3). At this time, in order to add the influence of the coupling noise of the control pulse FSB to the reference signal as well, the control pulse FSAD is once set to the low potential 0 V and the word line potential (VCC).
Repeat returning to + α). Then, the control pulse FS
AD, FSCD, FSD are returned to low potential 0V. In addition, the control pulse FDR is set to low potential 0V and FBUF is set to high potential VC.
Then, the signal transmission means DS and the buffer circuit BUF are set to C so as to be inoperative.

FIG. 11 is a diagram showing the timing of the rewriting operation performed after the reading operation shown in FIG. First, the stored voltage is transmitted to the sub-arrays SAA (1) to SAA (3). By raising the control pulse FSA (1), the data line DA in which the read signal is first discriminated in the sub-array SAA (i) is connected to the signal transmission means DS by the switch circuit SWA. The control pulse FDW is raised to the word line potential (VCC + α), and the signal transmission means DS is generated in the sub-arrays SAA (i) and SAB (j).
Of the switching circuit SWA or SWB by the transistor Q3 of the common data line CDA (i) or CDB.
Connect to (j). Further, the control pulse FSE is raised to the word line potential (VCC + α), and the common data line CDA (i)
Data bus GD by writing switch SWE
Connect to (i). Further, the control pulse FW is raised to the word line potential (VCC + α), and the data bus GD (i) is changed to
Common write switch circuit S in the multi-valued sense circuit MSC
It is connected to the multilevel write circuit MLW (i) by WW. From the above, the data line DA in the sub-array SAA (i) is
Through the switch circuit SWA, the signal transmission means DS, the common data line CDA (i), the write switch SWE, the data bus GD (i), and the common write switch circuit SWW to the multilevel write circuit MLW (i). Connected. Here, from the register circuit MDR (i), the sub array SAA
The determination result of the read signal appearing on the data line DA in (i) is transmitted to the multilevel write circuit MLW (i). For example,
Register DR (1,1) in register circuit MDR (1)
One bit at a time from ~ DR (1,3) is transmitted to the multi-level write circuit MLW (1). In response to this, one of the m-valued accumulated voltages is output from the multi-level write circuit MLW (i) and transmitted to the data line DA in the sub-array SAA (i). By lowering the control pulse FSA (1),
In the sub-array SAA (i), the data line DA is separated from the signal transmission means DS by the switch circuit SWB.
Thereafter, the control pulse FSA is sequentially increased to the word line potential (VCC + α) up to FSA (t) and the same operation is repeated, and the accumulated voltage according to the determination result of the read signal stored in the register circuit MDR is changed to the multi-value writing circuit. It is transmitted from the MLW to the data line DA in the sub array SAA. After that, the control pulse FSE is lowered to the low potential 0V, and the block BLKA is
The common data line CDA (i) of (i) is connected to the data bus GD
Separate from (i).

Subsequently, sub arrays SAB (1) to SA
The stored voltage is transmitted to B (3). Control pulse FSB
By raising (1), the data line DB for which the read signal is first determined in the sub-array SAB (j) is connected to the signal transmission means DS by the switch circuit SWB. Further, the control pulse FSF is raised to the word line potential (VCC + α), and the common data line CDB (j) is connected to the data bus GD (j) by the write switch SWF. The data line DB in the sub array SAB (j) is connected to the switch circuit S
WB, signal transmission means DS, common data line CDB (1),
It is connected to the multilevel write circuit MLW (j) via the write switch SWF, the data bus GD (j), and the common write switch circuit SWW. Here, the register circuit M
The determination result of the read signal appearing on the data line DB in the sub-array SAB (j) is transmitted from DR (j) to the multilevel write circuit MLW (j). In response to this, one of the m-valued accumulated voltages is output from the multi-level write circuit MLW (j) and transmitted to the data line DB in the sub-array SAB (j). By lowering the control pulse FSB (1),
In the sub array SAB (j), the data line DB is separated from the signal transmission means DS by the switch circuit SWB.
Thereafter, the control pulse FSB is sequentially raised to the word line potential (VCC + α) up to FSB (t) and the same operation is repeated to transmit the accumulated voltage to all the data lines DB in the sub array SAB. Then, the control pulse FSF is lowered to the low potential 0V, and the common data line CDB of the sub-array SAB (j) is
(J) is separated from the data bus GD (j). In addition, the control pulse FW is lowered to the low potential 0V, and the data bus GD
(J) is separated from the multilevel write circuit MLW (j).

After that, the sub-arrays SAA (1) to SAA
(3) The reference voltage is transmitted to the dummy data lines DDA and DDB in SAB (1) to SAB (3). Control pulse F
By increasing SAD and FSBD, sub array SA
In A (i) and SAB (i), the dummy data line DDA is connected to the signal transmission means DS by the switch circuits SWA and SWB. In addition, the control pulse FWD is applied to the word line potential (V
CC + α), common data lines CDA (i), CDB
(I) is connected to the dummy data bus DGD (i) by the write switches SWE and SWF, and the dummy data bus DGD (i) is connected to the reference voltage VREF (i by the common write switch circuit SWW in the multi-valued sense circuit MSC. ) Is transmitted. The reference voltage VREF (i) is the dummy data bus DGD (i), the write switch SWE or SWF, the common data line CDA (i) or CDB.
(I), the signal transmitting means DS, the switch circuit SWA or SWB, through the sub-array SAA (i), SAB
It is transmitted to the dummy data line DDA or DDB in (i). Then, the control pulses FSAD and FSBD are lowered to the low potential 0V, and the dummy data lines DDA and DDB are connected to the signal transmission means DS in the sub-arrays SAA (i) and SAB (i).
Separate from. The control pulse FDW is lowered to separate the switch circuit SWA or SWB from the common data line CDA (i). Control pulse FWD lowered, common data line CD
A (i) and CDB (i) are dummy data bus DGD
Separated from (i), the transistors in the common write switch circuit SWW are turned off.

With the above, the sub-arrays SAA (1) to SAA
(3), data lines DA and DB from which signals are read in SAB (1) to SAB (3) and dummy data lines DDA and D
The accumulated voltage or the reference voltage is transmitted to DB, and each is in a floating state. Here, by lowering the word line W to a low potential of 0V, the storage voltage or the reference voltage of the word line W is stored in the memory cell MC or the dummy cell DC. After that, control pulses FPD, FP
DA and FPDB are set to high potential VCC, FSA (1) to F
SA (t), FSAD, FSB (1) to FSB (t),
Using FSBD as the word line potential (VCC + α), the data lines DA and DB and the dummy data line DD in each sub-array
A, DDB and switch circuit SWA are precharged to V
Precharge to P and return to standby state.

By performing the read operation and the rewrite operation in this way, the memory cell MC connected to the word line W can be refreshed. All memory cells are refreshed by sequentially selecting word lines and performing the same operation. Further, between the read operation and the rewrite operation, the multi-value discrimination circuit is selected by the Y decoder (not shown) and the signal is exchanged with the outside, whereby the external writing or reading can be performed. The exchange of signals with the outside can be performed in units of the amount of information for one memory cell MC, or in units of 1 bit. Further, it is also possible to use the amount of information for the memory cells that are discriminated in time series by the same multi-level discrimination circuit MLR (i) as a unit.

In the above, the sub-arrays SAA (1) to SA
The read signal of A (3) is discriminated, and then the sub array S
The read signals of AB (1) to SAB (3) are discriminated, and then the accumulated voltage is transmitted to the sub-arrays SAA (1) to SAA (3), and subsequently the sub-arrays SAB (1) to SAB (3) are transmitted.
The operation of transmitting the accumulated voltage has been described in (3). The order of data line selection in read and rewrite operations is
It is not limited to this. For example, the data line can be selected in the reverse order of the read operation to perform the rewrite operation. In that case, the register circuits MDR (1) to MDR
In (3), the last input information is first output (LIFO). Multi-value discrimination circuit MLR (1) to M
The result determined last by LR (3) is the register circuit MD
If the data is not stored in R and is input to the multi-level writing circuit MLW, the storage capacity of the register DR in the register circuit can be reduced by 1 bit.

Further, each time the read signal is discriminated by the multilevel discriminator circuits MLR (1) to MLR (3) without using the register circuit MDR, the discriminant result is output as the multilevel write circuit MLW.
It is also possible to rewrite by inputting into (1) to MLW (3). In that case, since the accumulated voltage is transmitted to the data line adjacent to the data line from which the signal is being read, the interference noise between the data lines becomes a problem. For example, IEE, transaction on electron devices, Volume 37, 3 (March 1990) pp. 737 to 743 (IEEE, Trans.on Electron Devices, vol3
7, on.3 (March 1990) pp.737-743), using a memory cell with a small coupling capacitance between data lines by shielding the data lines with another conductive layer. Can reduce the effect.

When a one-transistor / one-capacitor type memory cell is used, the signal appearing on the data line is a change in the potential of the data line due to the charge stored in the storage capacitance of the memory cell being redistributed to the capacitance of the data line. Is. Therefore, the magnitude of the signal is affected by the deviation of the storage capacity of the memory cell and the capacity of the data line due to process variations and the like. In the present invention, since the reference signal is obtained by the reference signal obtained by reading the charge stored in the dummy cell to the dummy data line, the reference signal is also affected by the deviation between the storage capacity of the dummy cell and the capacity of the dummy data line. It Therefore, by matching the electrical characteristics of the memory cell and the dummy cell and the data line and the dummy data line, the influence of these deviations is offset.

In this embodiment, the reference voltage VREF (j) is stored in the dummy cell DC at the same time when the storage voltage is written in the corresponding memory cell MC, and thereafter the reference voltage VREF (j) is left as it is until the next selection. That is, the charge stored in the dummy cell DC is attenuated with time due to a leak current or the like in the storage capacitor portion, like the charge stored in the memory cell MC. Therefore, conventional dummy cell construction methods such as the 1980 IEE, International Solid State Circuits Conference, Digest of Technical Papers, pp. 234-235 (1980 IEEE ISSCC Digest o
f Technical Papers, pp.234-235), such as the method of adding a circuit to the dummy cell to set the terminal in the dummy cell to the desired potential and fixing it to that potential during the precharge. As compared with the case of application, it is possible to extend the time until the charge accumulated in the memory cell MC is attenuated and the read signal is erroneously determined, that is, the data holding time. This means that the time interval for refreshing the memory cell MC can be lengthened, and the ratio of the time during which the semiconductor memory device is performing a refresh operation can be reduced.
It is possible to increase the percentage of time the semiconductor memory device can be used in the system. In addition, the power consumption required for refresh can be reduced.

In the one-transistor / one-capacitor type memory cell, since the accumulated charges are redistributed and read out to the data lines, the read signal is small. Moreover, for destructive read, read signals of all memory cells driven by the same word line must be discriminated and rewritten. Since the multi-valued memory stores m values, the size of the effective read signal, that is, the difference between adjacent levels becomes one-half of the binary value (m-1). Therefore, when storing multiple values in a one-transistor / one-capacitor memory cell, the effective read-out signal is very small, and thus a high S / N technique is particularly important. The semiconductor multi-valued memory according to the present invention can determine the read signals of all the memory cells driven by the same word line, and can make the noise the same by canceling the noise by adjusting the signal path conditions. Since an S / N operation can be realized, it is particularly effective when using a one-transistor / one-capacitor memory cell.

The present invention can also be applied to a semiconductor multilevel memory using memory cells other than the one-transistor / one-capacitor type memory cell. For example, when a charge transfer element such as CCD or BBD is used as a memory cell,
The present invention can be applied.

FIG. 12 is a block diagram showing an example of application of the semiconductor memory device according to the present invention, which constitutes an audio recording / reproducing device. In the figure, MIC is a microphone as a voice input means, SP is a speaker as a voice output means, PAMP and MAMP are amplifiers, ADC is an analog / digital converter, DAC is a digital / analog converter, M is a semiconductor multi-valued memory according to the present invention, The MCT is a control circuit that controls the semiconductor multilevel memory M. In the same figure, the bandpass low pass filter and the waveform shaping low pass filter are omitted.

In the recording operation, the voice input to the microphone MIC is amplified by the amplifier PAMP, the analog signal is converted into a digital signal by the analog / digital converter ADC, and the semiconductor circuit is controlled by the control circuit MCT. It is done by writing in M. At this time, the address and clock signal of the semiconductor multi-level memory M are supplied to the control circuit MCT.
Generated by. On the other hand, in the reproducing operation, the semiconductor multi-valued memory M is controlled by the control circuit MCT, the stored information is read out, converted into an analog signal by the digital / analog converter DAC, amplified by the amplifier MAMP, and then the speaker SP. Output more.

When the input / output of the semiconductor multi-valued memory M is bit by bit, and when a plurality of bits of information are output in parallel from the analog / digital converter ADC, a parallel / serial converter is provided to perform time series. It may be converted into information and transmitted to the semiconductor multilevel memory M. When the digital / analog converter ADC has a configuration in which a plurality of bits of information are input in parallel, a serial / parallel converter may be provided to convert the output of the semiconductor multilevel memory M into parallel information. ..

The data rate of the voice information may be 64 kbit / sec, and a semiconductor multilevel memory having a cycle time of 15 μs can be used. The information is data that is continuous in time series. Therefore, the storage device used for the voice recording device is required to be inexpensive and have a large capacity without causing a speed problem. The semiconductor multi-valued memory according to the present invention has a high S / N and is suitable for high integration, and can reduce the chip area and the bit unit price. Therefore, the semiconductor multi-valued memory of the present invention is more suitable for such applications than the conventional DRAM.

[0053]

As is apparent from the embodiments described above,
A plurality of data lines divided into two groups of an equal number, a plurality of word lines arranged so as to intersect with them, and a plurality of word lines arranged at desired intersections of the data lines and the word lines and having at least three values or more. A memory cell that stores and holds information on an m value, a multi-valued sense circuit that determines a read signal output from a memory cell to a data line by driving a word line, and a multivalued sense circuit (m-1) ) Has a plurality of dummy cells DC for generating reference signals, and read signals are read from all memory cells on the selected word line to corresponding data lines and read out to one group of data lines. The signals are sequentially input to the multi-valued sense circuit in units of at least (m-1), and read from the same number of dummy cells as the number of the read signals to the data line of the other group. By being compared with the reference signal,
Read signals of all memory cells driven by the same word line can be identified, and by comparing the same number of read signals and reference signals, it is possible to cancel the noise by making the signal path conditions uniform. Therefore, a high S / N semiconductor multilevel memory can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment.

FIG. 2 is a diagram showing a second embodiment.

FIG. 3 is a diagram showing a third embodiment.

FIG. 4 is a diagram showing a fourth embodiment.

FIG. 5 is a diagram showing a configuration of a block BLKA (1).

FIG. 6 is a diagram showing a configuration of a block BLKB (1).

FIG. 7 is a diagram showing a buffer circuit BUF and the like connected to a block BLKA (1).

FIG. 8 is a diagram showing a buffer circuit BUF and the like connected to a block BLKB (1).

FIG. 9 is a diagram showing a configuration of a multi-valued sense circuit MSC.

FIG. 10 is a timing diagram of a read operation.

FIG. 11 is a timing chart of a rewriting operation.

FIG. 12 is a block diagram of an example applied to an audio recording / reproducing device.

[Explanation of symbols]

MC ... Memory cell, DC ... Dummy cell, W ... Word line,
DWA, DWB ... Dummy word line, DA, DB ... Data line, DDA, DDB ... Dummy data line, BUF ... Buffer circuit, GD, GDA, GDB ... Data bus bar, DGD ...
Dummy data bus, DC ... Dummy cell, MSC ... Multi-valued sense circuit, CP ... Comparator, CDA, CDB ... Common data line, DS ... Signal transmission means, SAA, SAB, SA ... Sub array, DSAA, DSAB ... Sub dummy array, SW
... switch, SWA, SWB, ... switch circuit, SW
C, SWD ... switch circuit, PD ... precharge circuit,
PDA, PDB ... Common precharge circuit, SWE, SW
F ... Writing switch, DAMP ... Differential amplifier, SWW
... Common write switch circuit, MLR ... Multi-value discrimination circuit,
MDR ... Register circuit, DR ... Register, MLW ... Multi-value writing circuit, MIC ... Mic, SP ... Speaker, PAM
P, MAMP ... Amplifier, ADC ... Analog / digital converter, DAC ... Digital / analog converter, M ... Semiconductor multi-valued memory, MCT ... Control circuit.

Claims (19)

[Claims] 1. A plurality of data lines divided into two groups of an equal number, a plurality of word lines arranged so as to intersect with them, and arranged at a desired intersection of the data lines and the word lines. A memory cell for storing and holding information of m value which is at least three values or more, a multi-valued sense circuit for discriminating a read signal outputted from the memory cell to the data line by driving the word line, The multi-valued sense circuit has a plurality of dummy cells for generating (m-1) kinds of reference signals used for determining the m value, and all the memory cells on the selected word line are read to the corresponding data line. , In units of at least (m-1) or more, the read signals read out to the data lines of one group are sequentially input to the multi-valued sense circuit, and the data of the other group are read. Semiconductor multi-valued memory is compared with q number of reference signal read from the dummy cell. 2. The multi-valued sense circuit is configured to include comparators of the square of the number q of read signals and reference signals input at the same time, and the read signals and the reference signals are q comparators. 2. The semiconductor multi-valued memory according to claim 1, wherein 3. The semiconductor multi-valued memory according to claim 2, wherein the number q of read signals and reference signals simultaneously input to the multi-valued sense circuit is one less than the number m of multi-valued levels stored in the memory cell. A semiconductor multi-valued memory characterized by being equal to the number of reference levels. 4. The semiconductor multi-valued memory according to claim 2, wherein the number q of read signals and reference signals simultaneously input to the multi-valued sense circuit is equal to the number m of multi-valued levels stored in the memory cell. A semiconductor multi-valued memory characterized by. 5. The semiconductor multi-valued memory according to claim 1, wherein a dummy data line having the same shape as the data line is provided, and the dummy cell is arranged at an intersection of the dummy data line and the word line. And semiconductor multi-valued memory. 6. The semiconductor multi-valued memory according to claim 1, wherein a dummy word line having the same shape as that of said word line is provided, said data line is composed of a pair of lines, and any one of a certain word line and data line pair is provided. A semiconductor multi-valued memory characterized in that the memory cell is arranged at an intersection with one and the dummy cell is arranged at an intersection between one of a dummy word line and a data line pair. 7. The semiconductor multi-valued memory according to claim 1, wherein a data bus bar is provided perpendicular to the data line, the multi-valued sense circuit is connected to the data bus line, and the read signal is transmitted through the data bus line. A semiconductor multi-valued memory which is transmitted to a multi-valued sense circuit. 8. The semiconductor multilevel memory according to claim 7, wherein a buffer circuit having a large input impedance is connected to said data bus, and said read signal is transmitted to said data bus via said buffer circuit. Characteristic semiconductor multi-level memory. 9. The semiconductor multilevel memory according to claim 1, wherein a common data line is provided in parallel with said data line, and said read signal is transmitted to said multilevel sense circuit through said common data line. Characteristic semiconductor multi-level memory. 10. The semiconductor multi-valued memory according to claim 9, wherein said data line is connected to said common data line by a signal transmitting means having a large input impedance, and said read signal is said common signal via said signal transmitting means. A semiconductor multilevel memory characterized by being transmitted to a data line. 11. The semiconductor multi-valued memory according to claim 1, wherein a switch circuit is provided in a signal path from the data line to the multi-valued sense circuit, and the switch circuit selectively selects from a plurality of read signals. A semiconductor multi-valued memory, wherein q pieces are inputted to the multi-valued sense circuit. 12. The semiconductor multi-valued memory according to claim 7, wherein a dummy data bus is provided in parallel with the data bus, and the multi-valued sense circuit is connected to the data bus and the dummy data bus, and the read operation is performed. A semiconductor multi-valued memory, wherein a signal is transmitted to the multi-valued sense circuit through the data bus and the reference signal is transmitted to the multi-valued sense circuit through the dummy data bus. 13. The semiconductor multi-valued memory according to claim 12, wherein a common switch circuit is provided to the data bus and the dummy data bus, and the read signal is sent to the data bus via the common switch circuit to the data bus. A semiconductor multi-valued memory, wherein a reference signal is transmitted to the dummy data bus through the common switch circuit. 14. The semiconductor multi-valued memory according to claim 7, wherein said data bus line is composed of a pair of lines, said multi-valued sense circuit is connected to said data bus line pair, and said read signal is one of said data bus line pair. A semiconductor multi-valued memory, wherein the reference signal is transmitted to the multi-valued sense circuit through one of the data bus lines, and the reference signal is transmitted to the multi-valued sense circuit through the other of the data bus pairs. 15. The semiconductor multi-valued memory according to claim 1, wherein the memory cell comprises one MOS transistor and one storage capacitor. 16. The semiconductor multi-valued memory according to claim 15, wherein the storage capacitor is in contact with one of the impurity-doped regions of the transistor, and extends over the transistor and the data line, and the electrode. A semiconductor memory comprising an insulating film provided on the upper surface and a conductive electrode further provided on the insulating film. 17. The semiconductor multi-valued memory according to claim 1, wherein the multi-valued sense circuit includes a multi-valued determination circuit including the comparator, and a multi-valued write circuit that outputs a multi-valued signal. A semiconductor multi-valued memory characterized by being processed. 18. The semiconductor multi-valued memory according to claim 17, wherein said multi-valued sense circuit includes a register circuit for temporarily storing the output of said multi-valued discrimination circuit. 19. The semiconductor memory according to claim 1, wherein the voice input means, an amplifier for amplifying an output signal of the voice input means, and an analog to which the output signal of the amplifier is input. A digital / analog converter, a semiconductor memory to which the output signal of the analog / digital converter is input, a digital / analog converter to which the output signal of the semiconductor memory is input, and an output signal of the digital / analog converter. A semiconductor memory, which is a constituent element of an audio recording / reproducing apparatus having an amplifier for amplifying and an audio output means to which an output signal of the amplifier is input.