JP3307163B2 - Encoding method and encoding device, and decoding method and decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding method and apparatus.
And a decoding method and apparatus. In particular, the present invention
An image compressed and encoded independently of the video data of other frames
The predetermined relationship between intra-frame data and other frames
Inter-frame data compressed and encoded to have
A method and apparatus for packing compressed video data
And depackage the data so packed.
A method and apparatus for locking.

[0002]

2. Description of the Related Art Video data is transmitted every predetermined number of frames.
One or more of the predetermined number of frames are decoded using intra-frame data (I-frame data) that can be decoded independently of other frames, and the other one or more are decoded using data of immediately preceding or both adjacent frames. An MPEG method or the like for compressing and encoding inter-frame data (P-frame data and B-frame data, hereinafter simply referred to as "B-frame data" when these are collectively referred to) is a popular method for compressing video data. Used.

Specifically, a frame is divided into macroblocks each having a predetermined number of pixels (for example, 16 × 16), and every two frames, one of them is discrete cosine transform (DCT) in macroblock units independently of the other frames. ) And variable-length coding and compression coding to generate I-frame data DC, AC1,..., DC ', AC1',... Corresponding to each macroblock, for example, as shown in FIG. These intra frame data DC, AC
, DC ′, AC1 ′,... Are arranged in a line in order from the direct-current component and the low-frequency component, are arranged in a predetermined recording frame in this order, and are recorded on a digital video tape or the like. The B frame data is arranged and recorded after the I frame data.

[0004]

As shown in FIG. 10, I frame data and the like generated from a video frame are
When the data is simply recorded in a line, for example, when a data error occurs in the I-frame data AC1, the I-frame data is variable-length coded. …, D
C ', AC1',... Cannot be reproduced at all.

[0005] On the other hand, when video data compressed and encoded by DCT or the like is reproduced, it is known that the effect on the quality of the reproduced video is greater for lower frequency components. That is, when reproducing the compression-encoded video data, a reproduced video having no practical problem can be obtained even if some high frequency components are missing. Also, video cannot be reproduced from B-frame data without I-frame data.
Video can be reproduced from I-frame data without frame data.

The present invention has been made in view of the above-described facts, and even if a data error occurs in the middle of video data after compression encoding, the video data after compression encoding has a low level. Code that can rescue most of the frequency components
It is an object of the present invention to provide a decoding method and its device and a decoding method and its device . Further, according to the present invention, when a data error occurs in the middle of compression-encoded video data, it is possible to rescue intra-frame data which is more necessary for video playback in preference to inter-frame data. Encoding Method and Apparatus, and Decoding Method and Applicable Method
It is intended to provide a device .

Further, the present invention provides an encoding method, an apparatus and a decoding method capable of obtaining a higher quality reproduced video even if a data error occurs in the video data after compression encoding.
The purpose of the law and its equipment . Further, the present invention provides an encoding method and apparatus capable of obtaining high-quality reproduced video even when performing variable-speed reproduction such as so-called jog shuttle reproduction.
An object of the present invention is to provide a decoding method and an apparatus therefor.

[0008]

According to a first aspect of the present invention, there is provided an encoding apparatus for encoding video data, comprising: encoding means for encoding the video data in an intra frame or an inter frame; When packing the intra picture encoded as the intra frame and the inter picture encoded as the inter frame to have a predetermined fixed length, the intra picture is preferentially given to the inter picture. An encoding device is provided, which includes packing means for packing and packing the inter picture so that the head position of the inter picture can identify the packing position of the inter picture.

Preferably, the packing area of the intra picture and the packing area of the inter picture are distinguished from each other, and the packing means sequentially performs the above processing for the intra pictures within a first length. Intra-picture packing area is stored in the intra-picture packing area, and the intra-pictures having the first length or more are packed in the free area of the intra-picture packing area.
Are sequentially stored in the inter-picture packing area, and the inter-pictures having the second length or more are packed in a free area of the inter-picture packing area.

Preferably, the first length and the second length are determined from a data amount when the video data is compression-coded into an intra picture and an inter picture.

More preferably, the apparatus further comprises outer code / inner code adding means for adding an outer code and an inner code to the packed data.

Further, a data recording apparatus according to the present invention has respective means for realizing the above-described data recording method according to the present invention. Further, the data reproducing device according to the present invention,
It has respective means for realizing the above-described data reproducing method according to the present invention.

According to a second aspect of the present invention, there is provided a method for performing the above-described processing of the encoding apparatus. The encoding method includes the steps of: encoding video data in an intra frame or an inter frame; and translating the intra picture encoded as the intra frame and the inter picture encoded as the inter frame into a predetermined fixed length. When packing such that the intra picture is preferentially packed with respect to the inter picture, the packing position of the inter picture is packed such that the head position of the inter picture can be identified. And a packing step.

According to a third aspect of the present invention, there is provided an apparatus for decoding the encoded data. The decoding device is such that video data is encoded in an intra frame or an inter frame, and the intra picture encoded as the intra frame and the inter picture encoded as the inter frame have a predetermined fixed length. When packed, the intra picture is preferentially packed with respect to the inter picture, and the packing position of the inter picture is such that the head position of the inter picture can be identified. Means for inputting coded video data, means for depacking the intra picture and the inter picture in a process opposite to the packing process, and decoding processing for the depacked picture inverse to the encoding process. Decryption means for performing Characterized by comprising.

According to a fourth aspect of the present invention, there is provided a decoding method for performing the operation of the decoding apparatus. The decoding method is such that the video data is encoded in an intra frame or an inter frame, and the intra picture encoded as the intra frame and the inter picture encoded as the inter frame have a predetermined fixed length. When packed, the intra picture is preferentially packed with respect to the inter picture, and the packing position of the inter picture is such that the head position of the inter picture can be identified. Inputting the coded video data, depacking the intra picture and the inter picture in a process opposite to the packing process, and decoding the depacked picture in a direction opposite to the encoding process. Performing a decryption step and Characterized by comprising.

[0016] By packing the coded intra picture in preference to the inter picture, even if an error or the like occurs, the intra picture can be corrected and reproduced. In particular, since the intra-picture packing area and the inter-picture packing area are distinguished, the packing processing in the encoding device is easy, and the depacking processing in the decoding device is also easy.

Further, when packing, since the packing is performed with a fixed length, error correction can be easily and accurately performed.

By adding an outer code and an inner code to the packed data, the error correction capability is improved.
The encoding means performs an encoding process represented by, for example, MPEG.

[0019] The decoding method and the decoding apparatus perform processing reverse to that of the encoding method and the encoding apparatus.

[0020]

Embodiment 1 Hereinafter, a first embodiment of the present invention will be described.
FIG. 1 shows a digital video recorder (VT) according to the present invention.
2 is a diagram illustrating a configuration of an (R device) 1. FIG. As shown in FIG.
The VTR device 1 includes a compression encoder 10, an error correction code encoder (ECC encoder; ECCE) 12, a main memory 16, an inner code decoder 20, an ECC decoder 22, a jog shuttle memory 24, a decompression decoder 26, and a frame memory. 28. In FIG. 1, a portion for processing data relating to audio is omitted for simplification of illustration.

The ECC encoder 12 includes a pack circuit 14, an outer code encoder 122, a first FIFO circuit 124, a second FIFO circuit 126, and an inner code encoder 128. Also, the ECC decoder 22
Is composed of a tracking circuit 220, a memory circuit 222, an outer code decoder 224, a jog memory control circuit 226, and a depacking circuit 30.

The VTR 1
Is, for example, independently compresses and encodes one of the above two frames into intra-frame data (I-frame data) capable of reproducing original video data (hereinafter referred to as video data) by the MPEG system or the like. , The other is compressed and encoded into reproducible bidirectional predictive encoded data (a type of B-frame data or intra-frame data) by using video data of both adjacent frames after the reproduction, and these data are converted into data relating to audio (hereinafter, referred to as audio data). , Audio data)
At the same time, the data is recorded on the video tape 40, and the recorded audio / video data is read out from the video tape 40 and reproduced.

FIG. 2 is a block diagram of the compression encoding apparatus 10 shown in FIG.
FIG. 2 is a diagram showing a configuration of a pack circuit 14. FIG.
FIG. 3 is a diagram for explaining processing of the compression encoding device 10,
(A) shows the configuration of the macroblock included in the frame, (B) shows the generated I frame data and B frame data, and (C) shows the I frame data and B frame data shown in (B). (D)
Is a picture group GOP composed of the I frame data and the B frame data shown in (B) and (C).
Is shown. 4A and 4B are diagrams illustrating a configuration of a recording frame, wherein FIG. 4A illustrates a configuration of a recording frame, and FIG. 4B illustrates a configuration of a recording unit (synchronous block) that configures the recording frame. is there.

As shown in FIG. 2, the compression encoding device 10
Comprises a motion compensation circuit (MEP) 102, a discrete cosine transform circuit (DCT circuit) 104, and a variable length coding circuit (VLC) 106. With these components, the compression encoding apparatus 10, from the outside, for example, two frames of video data VI inputted corresponding data respectively to a component signal (luminance data Y, color difference data C _r, C _b) as One for I-frame data,
The other is compression-encoded into B frame data.

The motion compensation circuit 102 converts the above two frames into luminance data Y as shown in FIG.
And color difference data C _r, 16 × corresponding to C _b respectively
The macroblock is divided into 16 macroblocks, and the other of the two frames is subjected to motion compensation processing in units of macroblocks between the immediately preceding and succeeding frames, and the detected motion vector is sent to the motion compensation circuit 102. Output to

The DCT circuit 104 includes a motion compensation circuit 102
And a motion vector detected for each of the macroblocks included in one of the two video frames in the time domain and the motion vector detected for each of the macroblocks included in the other frame. ) To convert to frequency domain data,
Further, quantization is performed at predetermined quantization steps, and
I frame data and B frame data corresponding to each macro block included in one frame are generated, and output to the variable length coding circuit 106 in order from a DC component and a low frequency component.

Actually, as shown in FIG. 3A, the DCT circuit 104 stores 16 bits corresponding to the luminance data Y.
The macroblock of × 16 pixels is further divided into four blocks each composed of 8 × 8 pixels, and the color difference data C _r , C
The macroblock of 16 × 16 pixels corresponding to _b is divided into two blocks each of 8 × 8 pixels, and DCT processing is performed for each divided block.

Further, the DCT circuit 104 has the configuration shown in FIG.
As shown in (C), when the motion of the video is large and the data amount of the B frame data is large, the quantization step for the I frame data is increased to reduce the I frame data. Is large, the amount of I-frame data is increased by reducing the quantization step for the I-frame data, and the quantization process is performed so that the data amount of each picture group GOP is almost the same. By performing such a quantization process, the DCT circuit 104 reduces the data amount of each picture group GOP to the data amount that can be accommodated by the recording frame, and
The data amount of each picture group GOP is averaged.

The variable length coding circuit 106 is a DCT circuit 1
FIG.
As shown in (B) to (D), one frame corresponds to one frame.
From the two frames of video data composed of 440 or 1710 macroblocks, a picture group GOP (Group Of Picture) composed of one I frame data and one B frame data, respectively.
s) is output to the pack circuit 14 as compressed video data RED including one for each cycle of the synchronization signal SGOP. Note that the variable-length coding circuit 106 adds an end identifier EOB indicating the end of the I-frame data and the B-frame data to the end.

Further, as shown in FIG.
Is the data length detection circuit 140, the memory write control circuit 1
42, an address generation circuit 144, 146, a remaining data length calculation circuit 148, a sub memory write control circuit 150,
Sub memory write control circuit 152 and sub memory 1
54. With these components, the pack circuit 14 operates in synchronization with the synchronization signal SF synchronized with the video data VI, and the I / O signal input from the compression encoding device 10 is input.
The frame data, B frame data, and audio data AI are arranged in 36 recording frames in the PAL system and 30 recording frames in the NTSC system as shown in FIG. However, for clarity of explanation,
The processing related to the audio data AI is omitted and described.

The recording frame is shown in FIG.
1440 recording units (synchronous blocks) (or 1
710 pieces) which, in this synchronization block, respectively, the first two bytes synchronization code SYNC are arranged, followed by the 4-byte identification code ID is arranged, followed by compression encoding apparatus to 108 bytes 10 Group GOP or outer code encoder 1 generated by
The outer code generated by the inner code encoder 128 is arranged in the last 12 bytes.

The synchronizing block includes macroblocks of a frame of video data and a picture group GOP generated from these macroblocks.
It corresponds to each, from the top 1440 (NTS
C system) or 1710 units (PAL system)
By the time, I-frame data generated from each corresponding macro block (up to the 108th byte from the beginning when the data length of the I-frame data is 108 bytes or more) is arranged, and the I-frame data is The portion of the data after the 109th byte and the data of the B frame are arranged. The arrangement of the I frame data and the B frame data in the recording frame is as follows.
It will be described later with reference to FIG.

FIG. 5 is a diagram for explaining I-frame data and B-frame data arranged in recording frames by the pack circuit 14 shown in FIGS. FIG. 5 shows a case where the number of synchronous blocks is 8, for simplicity of illustration and description. Picture group GO by pack circuit 14 described above
The arrangement of P in the recording frame corresponds to packing the I frame data and the B frame data shown in FIG. 5A into the recording frame as shown in FIG. 5B .

That is, by the above-described operation, the pack circuit 14 stores the I-frame data (I-frame data of 10
If it is 9 bytes or more, the 108th byte from the beginning is arranged in the corresponding synchronization block, and overflow data (109th byte or more of I-frame data with a data length of 109 bytes or more) is arranged in I-frame data. The B frame data is arranged in order from the head of the free area after these data are arranged.

As shown in FIG. 5C, a macro block (FIG. 3) is placed at the beginning of the synchronous block in which the I-frame data is arranged by the operation of the pack circuit 14 described above.
(A)) The DC component (DC) and the low-frequency components (AC1, AC2,
…)). Therefore, at the time of reproduction, even if a data error occurs in the middle, by reading each synchronous block from the beginning,
It is possible to obtain a DC component and a low-frequency component of I frame data important for video reproduction.

The outer code encoder 122 (FIG. 1) operates in synchronization with the synchronization signal SF, and adds an error correcting outer code shown in FIG. 4A to the recording frame stored in the main memory 16. I do. The FIFO circuit 124 reads the recording frame stored in the main memory 16 in synchronization with the synchronization signal SF, buffers the read frame, and outputs the buffer to the FIFO circuit 126.

The FIFO circuit 126 includes the FIFO circuit 12
4 is buffered and output to the inner code encoder 128 in synchronization with a synchronization signal RF used for writing data to the video tape 40. The inner code encoder 128 outputs the synchronization signal R
It operates in synchronization with F, generates an inner code for error correction shown in FIG. 3 (A), adds it to the recording frame, completes the recording frame, and records it on the video tape 40 via the recording head. .

The recording frame recorded on the video tape 40 is read out via the reproducing head and input to the inner code decoder 20. The inner code decoder 20 is shown in FIG.
Error correction is performed for each of the synchronous blocks using the inner code shown in FIG. The tracking circuit 220 uses the memory circuit 222 to control the reproducing head to correctly trace the track on the video tape 40.

The outer code decoder 224 performs error correction on the I frame data and the B frame data of the picture group GOP arranged in the recording frame using the outer code shown in FIG. Output to the circuit 226. Jog memory control circuit 226
Stores the I-frame data and the B-frame data input from the outer code decoder 224 in the memory 24, reads them out according to an external instruction, performs a process related to a special reproduction such as a so-called jog shuttle, and sends the data to the depacking circuit 30. Output to

FIG. 6 is a diagram showing a configuration of the depacking circuit 30 shown in FIG. However, in FIG. 6, the jog memory control circuit 226 between the depacking circuit 30 and the memory 24 is omitted for simplification of the drawing. As shown in FIG. 6, the depack circuit 30 includes a data length error detection circuit 300, an address generation circuit 302, a read control circuit 304, an output buffer circuit 306, and an output control circuit 3.
08, and reproduces the I frame data and the B frame data arranged in the recording frame as shown in FIG.

The decompression decoding device 26 processes the I-frame data and the B-frame data input from the depacking circuit 30 in accordance with the processing performed by the compression coding apparatus 10, that is, the variable-length coding corresponding to the variable length coding circuit 106. The decoding process, the inverse discrete cosine transform (IDCT) process corresponding to the DCT circuit 104, and the motion compensation process for the B frame data corresponding to the motion compensation circuit 102 are performed.
The video data VO and the audio data AO corresponding to the original video data VI are generated and output.

Hereinafter, the operation of the VTR device 1 will be described. The video data VI input to the compression encoding device 10 is compression-encoded by the compression encoding device 10 into I frame data and B frame data for each of two frames and for each macroblock, and is output to the ECC encoder 12. . The ECC encoder 12 arranges the I frame data and the B frame data input from the compression encoding device 10 into a recording frame as shown in FIG. 5B, and adds an outer code and an inner code. And FIG.
The recording frame shown in (A) is completed and recorded on the video tape 40.

The inner code decoder 20 includes a video tape 40
The I data and the B data included in the recording frame recorded in the recording frame are error-corrected using the inner code included in the recording frame, and output to the ECC decoder 22. E
The CC decoder 22 performs error correction on the I frame data and the B data using the outer code.

Further, the depacking circuit 30 takes out an I frame having a data length (108 bytes) or less that can be arranged in a synchronous block as it is, and outputs an I frame having a data length of 109 bytes or more.
Each of the portions from the top of the frame to the 108th byte and the corresponding portions of the I frame from the 109th byte onward are added to reproduce the original I frame data, and the B frame data is extracted and separated. , FIG.
The original picture group GOP is returned to the macro block arrangement shown in FIG.

As described above, the VTR according to the present invention
According to the device 1, the DC component and the low-frequency component of the I frame data that are important at the time of reproduction can be always read from the head of the synchronous block forming the recording frame. Therefore, in the I frame data included in the transmission frame, the inner code decoder 20 and the outer code decoder 224
Even if a data error that cannot be corrected by the above occurs, only the part from that part to the last data of the same synchronization block is lost. That is, even if a data error occurs, the low-frequency portion of the I frame data is not lost, and the high-frequency component (1
And the B-frame data are not lost.

In addition, since I-frame data, which is more important than B-frame data, can be repaired prior to B-frame data for video playback, even if a data error as described above occurs, playback can be performed. The effect on later images can be reduced. ECC decoder 2
2, when performing variable speed playback called a so-called “jack shuttle” using the jog memory control circuit 226 and the memory 24, only a part of the front of each of the synchronization blocks included in the recording frame is recorded on the video tape 40.
However, also in this case, the DC component of the I frame and the component on the low frequency side are always reproduced, and only the B data which has a relatively small effect even if it is lost during video reproduction is relatively small. The quality of reproduced video during variable speed reproduction is improved.

Further, at the time of variable speed reproduction, by reading from the beginning of each synchronous block to the end identifier EOB or the end of each block, the DC component and the low frequency component of the I frame can be taken out, so that the variable speed reproduction processing is facilitated. . Also, despite the above effects,
In order to realize the present invention, the amount of hardware to be added is small.

In addition to using the recording frame as shown in FIG. 5B, for example, the clock shown in FIG. 5B is used as a clock for writing the I frame data and the B frame data in the recording frame. 1 / N (N is an integer of 2 or more) of the synchronization signal when the recording frame is used as described above.
May be used by dividing the synchronization block of the recording frame into N pieces. In this case, the DC component and the low frequency component of the I frame data or the B frame data can be extracted by performing depacking from a predetermined position of the synchronization block.

FIG. 7 shows an example of extracting a macroblock when one I frame is associated with one synchronous block. As shown in FIGS. 7A and 7B, 1
A macroblock of 6 × 16 pixels is converted from one frame to 45 ×
32 (1440; for NTSC) or 45
X38 pieces ( 1710 pieces; in the case of the PAL system ) are cut out and made to correspond one-to-one to each of the synchronous blocks shown in FIG. Since the relationship is 1440: 1710 ≒ 10: 12, this ratio becomes the ratio of the data amount on the video tape 40 as it is.

Therefore, in the VTR device 1, one synchronous block is recorded for each track of the video tape 40 in association with each other, and in the case of the NTSC system, the processing is performed by treating ten tracks as one set. 12 in case
By treating the book tracks as one set, processing such as jog shuttle reproduction and the like concerning these two types of data can be performed using the same apparatus without changing the mechanical part of the VTR apparatus 1 and the recording format of the video tape 40. Becomes possible.

[0051]

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described.
In the second embodiment, the VTR device 1 shown in FIG.
The operations of the packing circuit 14 and the depacking circuit 30 are improved so that, when data is reproduced from the video tape 40, even if a data error occurs in a recording frame, I
Not only DC components and low frequency components of frame data but also DC components and low frequency components of B frame data can be rescued.

FIG. 8 is a diagram for explaining the operation of the pack circuit 14 shown in FIGS. 1 and 2 in the second embodiment. As shown in FIG. 8E, in the second embodiment,
The pack circuit 14 uses the recording frame shown in FIG. 5B in the first embodiment by dividing the recording frame into an I-frame area and a B-frame area.
The I frame data and the B frame data are packed in the same manner as in the first embodiment.

Hereinafter, the pack circuit 1 in the second embodiment will be described.
Operation 4 will be described. First, the pack circuit 14 is configured as shown in FIG.
The data length of the I frame data shown in FIG.
8 (A) (I1, I3 to I6 and I8 shown in FIG. 8 (A)) and the data length of the I frame area shown in FIG. 8 (A) and the data length not less than a (FIG. 8 (A)). Are arranged from the beginning of the I-frame area of the corresponding synchronous block from the beginning of I2, I7) to the data length a (I0-0 to I8-0 shown in FIG. 8E).
Processing 1).

Next, the pack circuit 14 generates I-frame data whose data length is equal to or longer than the data length a (I-frame data shown in FIG. 8A).
2, I7), the portion (overflow data) after the data length a is arranged in order from the head of the free area of the I-frame area after the above-mentioned processing 1 (I2 shown in FIG. 8E).
-1, I2-2, I7-1 to I7-3); processing 2).

Further, the pack circuit 14 performs processing corresponding to processing 1 and processing 2 on the B frame data. First, the pack circuit 14 has a data length of less than or equal to the data length b of the B frame area shown in FIG. 8E among the B frame data shown in FIG.
1 to B3, B6, and B7) and the portion from the beginning to the data length b of data whose data length is equal to or longer than the data length b (B4, B5, and B8 shown in FIG. (B0-0 to B7-0 shown in FIG. 8E; processing 1 ').

Next, the pack circuit 14 transmits the B frame data whose data length is equal to or longer than the data length b (B frame data shown in FIG. 8A).
4, (B5)) and the part (overflow data) after the data length b are sequentially arranged from the head of the free area of the I-frame area and the B-frame area after the end of the processing 1 '(see FIG. 8E). B4-1, B5-1, B5-2,
B8-1 to B8-4); Treatment 2 ′).

The operation of the pack circuit 14 described above is based on the first
The processing of the pack circuit 14 in the embodiment is performed only on the I frame data in the I frame area.
This can be realized by repeatedly performing only the B frame data in the frame area. FIG.
The video data arranged in the I frame area and the B frame area as shown in FIG.
Is stored.

The operation of the depack circuit 30 will be described below. The video data reproduced from the video tape 40 is arranged in the recording frame shown in FIG.

The depacking circuit 30 converts the I frame data whose data length is equal to or less than the data length a and the I frame data whose data length is equal to or more than the data length a from each of the I frame areas of the synchronous frame shown in FIG. The part from the beginning of the data to the data length a is extracted. Further, the depacking circuit 30 adds the corresponding overflow data to the extracted I frame data, and reproduces the original I frame data shown in FIG.

The depacking circuit 30 reproduces the B frame data by performing the same processing as that for the I frame area for the B frame area. That is, the depack circuit 30
Is a B frame whose data length is less than or equal to the data length b from each of the B frame areas of the synchronization frame shown in FIG.
The frame data and the portion from the head of the B frame data whose data length is equal to or longer than the data length b to the data length b are extracted. Further, the depacking circuit 30 adds the corresponding overflow data to the extracted B frame data, and reproduces the original B frame data shown in FIG.

By changing the processing of the depacking circuit 30 as described above, the original I frame data and B frame data can be reproduced from the video data arranged in the recording frame as shown in FIG. Can be. The operation of the depacking circuit 30 described above is different from the operation of the depacking circuit 30 in the first embodiment in that the processing of the depacking circuit 30 is performed in the I frame area.
This can be realized by repeating only the B frame data in the remaining portion of the I frame area after extracting the B frame area and the I frame data after extracting only the frame data.

When a data error occurs in the transmission frame, the conventional method of simply arranging the I frame data and the B frame data shown in FIG. 8C from the beginning of the recording frame is used. , All the data after the position where the data error occurs becomes unreproducible. When the method of arranging the I frame data and the B frame data by the method described in the first embodiment shown in FIG. 8D is used, only a predetermined portion of the I frame data can be rescued. is there.

When the I frame data and the B frame data are arranged by the method shown in the second embodiment as compared with the case where these methods are used, the I frame data and the B frame data are read out from the predetermined positions of the synchronous blocks, respectively. A predetermined portion of the data and a DC component and a low frequency component of the B frame data can be rescued. Therefore, the second
When the I-frame data and the B-frame data are arranged by the method shown in the first embodiment, the same effect as that of the method shown in the first embodiment can be obtained, and when a data error occurs in the transmission frame, The quality of the reproduced video is higher than when the video data is recorded by the method shown in the first embodiment.

The data length a of the I frame area and the data length b of the B frame area in the recording frame
Can be determined, for example, from the ratio of the average data amount when compression-coding normal image data into I-frame data and B-frame data. When the data lengths a and b are obtained from the average data amount, the actual I frame data and B frame data of each picture group GOP cannot be accommodated in the I frame area and the B frame area, respectively. There are cases. However, as shown in FIG. 8 (E), the area for the I frame is made larger, and B
There is no problem because the remainder of the frame data can be arranged. Further, the data lengths a and b do not necessarily have to be fixed lengths. The data amount ratios of the I frame data and the B frame data are calculated for each picture group GOP, and the data amount ratios are calculated for each picture group based on this data amount ratio. May be determined.

[0065]

Embodiment 3 Hereinafter, a third embodiment of the present invention will be described.
The third embodiment corresponds to the case where the picture group GOP is composed of a larger number of I-frame data, B-frame data and forward prediction coded data (P-frame data). The operation of the pack circuit 14 and the depack circuit 30 shown in FIG. Hereinafter, the operation of the pack circuit 14 in the third embodiment will be described. FIG. 9 is a diagram for explaining the operation of the pack circuit 14 shown in FIGS. 1 and 2 in the third embodiment. FIG. 9 shows a case where there are five synchronization blocks for simplification of illustration and description.

As shown in FIGS. 9A and 9B, in the third embodiment, a picture group GOP is composed of I frame data and three B frame data (B, B ',
B ") and P frame data.
As shown in FIG. 9C, each of these five types of data is arranged in each of the five areas obtained by dividing the recording frame by the method described in the second embodiment.

First, the pack circuit 14 of the I frame data shown in FIG. 9A has a data length less than or equal to the data length a of the I frame area shown in FIG. 9C (FIG. 9A).
(I2, I3, I5 shown in FIG. 9A), and the part from the head of data having a data length equal to or greater than the data length a (I1, I4 shown in FIG. Arrayed from the beginning of the frame area (FIG. 9
(I0-0 to I5-0 shown in (E)).

Next, the pack circuit 14 sets the data length of the B frame data (B ', B, B ") and the P frame data shown in FIG.
The data length b ', b, b "of the frame area and the data length c of the P frame area or less (B'1, B'3 to B'5, B2 to B4, B" shown in FIG. 9B) 1, B "3
~ B "5, P1, P3, P5) and those having a data length equal to or longer than the data lengths b ', b, b", c (B'2, B1, B5, B "2 shown in FIG. 9B). , P2, P4) to the data lengths b ′, b, b ″, and c, respectively,
The three B frame areas and the P frame areas of the corresponding synchronous blocks are arranged from the head of each (B1'-0 to P1-0 shown in FIG. 9C).

Next, the pack circuit 14 is constructed as shown in FIG.
Overflow data (I1-1 to I1-5, I4-1 to I4-5, B'2-) of I frame data, three types of B frame data, and P frame data shown in FIG.
1, B'2-1, B1-1, B1-2, B5-1, B "
2-1 and P2-1 and P4-1) are defined as an I-frame area,
The three B-frame areas and the P-frame area are arranged in order from the beginning of the empty area as shown in FIG. 9C.

The processing of the pack circuit 14 described above is performed in the first
The processing of the pack circuit 14 in the embodiment is performed on the I frame data, the three types of B frame data, and the P frame data in the I frame area, three B frame areas, and the P frame area. This can be realized by performing the processing on the overflow data of these five data in the free area of the area.
As shown in FIG. 9C, the I frame area and three B
The video data arranged in the frame area and the P frame area is stored on the video tape 40.

Hereinafter, the operation of the depacking circuit 30 will be described. The video data reproduced from the video tape 40 is arranged in the recording frame shown in FIG.

The depacking circuit 30 converts the I frame data and the data of the three types of B frame and P frame regions of the synchronous frame shown in FIG. Data length a from the beginning of I frame data whose length is longer than data length a
Up to the data lengths b ', b,
B frame data below b "and a portion from the beginning of I frame data having a data length of b ', b, b" or more to the data length b', b, b ", and a data length of not more than data length c And the portion from the beginning of the P frame data whose data length is equal to or longer than the data length c to the data length c is extracted.

Further, the depacking circuit 30 adds overflow data corresponding to the extracted I-frame data, three types of B-frame data and P-frame, respectively, to obtain the original data shown in FIGS. 9A and 9B. , And three types of B frame data and P frame data. The operation of the depacking circuit 30 described above is based on the processing of the depacking circuit 30 in the first embodiment, in which the I frame data, the three B frame areas, and the P frame
The repetition is performed for each of the three types of B-frame data and P-frame data, and the I frame data and the overflow data for each of the three types of B-frame data and P-frame data are obtained in the remaining portion of the recording frame after extracting these data. Can be realized by performing

When I-frame data, three types of B-frame data and P-frame data are arranged by the method shown in the third embodiment, the data is read from this known position because the respective leading portions are known. By doing
Even if a data error occurs in the recording frame, the DC component and the low frequency component of each of the I frame data, the three types of B frame data, and the P frame data can be rescued.

As described above, according to the method shown in the third embodiment, the method shown in the second embodiment is also applied to a case where the picture group GOP is composed of two or more types of data. be able to. Therefore, if the video data is 3
Even if the data is composed of more than two types of data, when a data error occurs in a transmission frame including video data, the first
The quality of the reproduced video can be further improved as compared with the case where the video data is recorded by the method described in the embodiment. Note that the method shown in the third embodiment is also the same as that of the second embodiment.
Modifications similar to the method described in the embodiment can be made.

[0076]

As described above, according to the present invention, the code according to the present invention
According to the encoding method and apparatus and the decoding method and apparatus , even if a data error occurs in the video data after compression encoding, many of the low frequency components of the video data after compression encoding are rescued. be able to. Further, the symbol according to the present invention
According to the encoding method and apparatus and the decoding method and apparatus , when a data error occurs in the middle of video data after compression and encoding, it is necessary to reproduce video in preference to inter-frame data. Highly reliable intra-frame data can be rescued.

Further, the encoding method and the apparatus according to the present invention
According to the decoding method and the apparatus , even if a data error occurs in the video data after the compression encoding, a higher quality reproduced video can be obtained. Also, the encoding according to the present invention
According to the method and the apparatus and the decoding method and the apparatus ,
Even if variable speed playback such as so-called jog shuttle playback is performed, a high-quality playback video can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a VTR device according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a compression encoding device and a pack circuit illustrated in FIG. 1;

FIG. 3 is a diagram for explaining processing of the compression encoding device shown in FIG. 3;

FIG. 4 is a diagram showing a configuration of a recording frame.

FIG. 5 is a diagram illustrating I-frame data and B-frame data arranged in a recording frame by the pack circuit shown in FIGS. 1 and 2;

FIG. 6 is a diagram illustrating a configuration of a depack circuit illustrated in FIG. 1;

FIG. 7 shows an example of cutting out a macroblock when one I frame is associated with one synchronization block.

FIG. 8 is a diagram illustrating the operation of the pack circuit shown in FIGS. 1 and 2 in the second embodiment.

FIG. 9 is a diagram illustrating the operation of the pack circuit shown in FIGS. 1 and 2 in the third embodiment.

FIG. 10 is a diagram showing a method of arranging I-frame data in a recording frame using a conventional data reproducing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... VTR apparatus, 10 ... compression coding apparatus, 102 ... motion compensation circuit, 104 ... DCT circuit, 106 ... variable length coding circuit, 12 ... ECC encoder, 122 ... outer code encoder, 124, 126 ... FIFO circuit, 128 ... Inner code encoder, 14 ... Data length detection circuit, 142 ... Memory write control circuit, 144,146 ... Address generation circuit, 148 ... Remaining data length calculation circuit, 150 ... Sub memory write control circuit, 154 ... Sub memory, 16 ... Main memory, 20 ... inner code decoder, 22 ... ECC decoder,
220: tracking circuit, 222: memory circuit, 22
4 outer code decoder, 226 outer code decoder, 24
Memory: 30: depacking circuit, 300: data length error detection circuit, 302: address generation circuit, 304: read control circuit, 306: output buffer circuit, 308: output control circuit, 26: decompression decoding device, 28: frame memory

Claims (10)

(57) [Claims] An encoding apparatus for encoding video data, comprising: encoding means for encoding the video data in an intra frame or an inter frame; an intra picture encoded as the intra frame; When packing an inter picture encoded as a predetermined fixed length, the intra picture is preferentially packed with respect to the inter picture, and the packing position of the inter picture is set to the inter picture. A coding unit for packing the inter picture so that a head position can be identified. 2. The packing area of the intra picture and the packing area of the inter picture are distinguished from each other, and the packing means sequentially performs the intra picture processing for the intra pictures within a first length. The intra picture is stored in a picture packing area, and the intra picture of the first length or more is packed in a free area of the intra picture packing area. The inter picture is sequentially stored for an inter picture of a second length or less. The encoding device according to claim 1, wherein the encoding unit stores the inter picture having the second length or more in a packing area and packs the inter picture in a free area of the inter picture packing area. 3. The encoding apparatus according to claim 2, wherein the first length and the second length are determined from a data amount when the video data is compression-coded into an intra picture and an inter picture. 4. The encoding apparatus according to claim 1, further comprising outer code / inner code adding means for adding an outer code and an inner code to the packed data. 5. The coding means divides the video data into a plurality of blocks, converts a predetermined number of time domain video data included in each of the blocks into frequency domain data, and The encoding device according to claim 1, wherein the encoding is performed by sequentially arranging the encoded data and performing variable length encoding to generate compressed video data corresponding to each of the predetermined number of frames and each of the plurality of blocks. 6. An encoding method for encoding video data, comprising: encoding the video data in an intra frame or an inter frame; encoding an intra picture encoded as the intra frame; and encoding the video data as the inter frame. When packing the converted inter-pictures to have a predetermined fixed length, the intra-pictures are preferentially packed with respect to the inter-pictures, and the packing position of the inter-pictures is set to the head position of the inter-pictures. And a packing step of packing the inter-picture so as to identify the inter-picture. 7. The video data is encoded in an intra frame or an inter frame, and packing is performed so that an intra picture encoded as the intra frame and an inter picture encoded as the inter frame have a predetermined fixed length. In this case, the intra picture is preferentially packed with respect to the inter picture, and the packing position of the inter picture is packed so that the head position of the inter picture can be identified. Means for inputting video data; means for depacking the intra-picture and the inter-picture in a process opposite to the packing process; and a process for decoding the depacked picture in a manner opposite to the encoding process. Decryption means to perform; Decoding and wherein the was e. 8. The packing area of the intra picture and the packing area of the inter picture are distinguished, and the packing area of the intra picture sequentially stores intra pictures of a first length or less. Is packed in a free area of the intra picture packing area, and inter pictures of a second length or less are sequentially stored in the packing area of the inter picture, and the second picture is stored in the packing area of the inter picture. An inter-picture part having a length or more is packed in a free area of the inter-picture packing area, and the depacking means performs de-packing according to a storage state of the intra-picture packing area and a storage state of the inter-picture packing area. Performing a process; Decoding device. 9. An outer code and an inner code are added to the depacked picture, and an inner code and an outer code for decoding the inner code and the outer code prior to the depacking process by the depacking means. The decoding device according to claim 7, further comprising code decoding means. 10. The video data is encoded in an intra frame or an inter frame, and packing is performed so that an intra picture encoded as the intra frame and an inter picture encoded as the inter frame have a predetermined fixed length. In this case, the intra picture is preferentially packed with respect to the inter picture, and the packing position of the inter picture is packed so that the head position of the inter picture can be identified. Inputting video data; depacking the intra-picture and the inter-picture in a process opposite to the packing process; and decoding the depacked picture in a direction opposite to the encoding process. The decryption steps to perform Decoding wherein the was e.