JP3307149B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a trench formed in a semiconductor substrate and a method of manufacturing the trench.

[0002]

2. Description of the Related Art When a semiconductor device or the like is formed, a concave trench (groove) is formed in a semiconductor substrate, and an insulating filling material is buried in the trench to perform element isolation or to form a trench capacitor or the like. Has been done.

For example, as shown in FIG. 6, when element isolation is performed by using a trench 32, a semiconductor has a smaller area than that of a so-called LOCOS method in which an oxide film is selectively formed on a semiconductor substrate 1. Element isolation can be performed to a deep position in the substrate.

[0004]

However, the trenches conventionally formed in a semiconductor substrate such as silicon are formed by etching the silicon substrate from its surface by reactive ion etching (RIE) or the like. Has a problem that a local stress is generated at each corner edge of the trench due to the thermal oxidation treatment and damages the crystal of the substrate.

Hereinafter, problems that occur in a general semiconductor device manufacturing process will be described with reference to FIGS.

As shown in FIG. 2C, first, the semiconductor substrate (silicon substrate) 1 is etched by RIE or the like to form a trench 32 having a large (deep) aspect ratio. Next, the side wall inside the trench 32 is oxidized, and polycrystalline silicon (Poly-S) is formed on the obtained side wall oxide film 20.
i) or the like, and burying an insulating burying material,
To form

Next, when a transistor having, for example, a general MOS structure is formed as a semiconductor element, a gate electrode 5 is formed on the semiconductor substrate 1 via a gate insulating film. Further, in order to form a source / drain (S / D) region, high-concentration impurity implantation (for example, ion implantation) is performed using the gate electrode 5 as a mask. The region into which the impurities are implanted is an amorphous region 6 as shown in FIGS. 6A and 2D, and the region 6 is activated by annealing (annealing) so that the implanted impurities are activated. And source / drain regions are formed.

However, at the time of this heat treatment, FIG.
As shown in FIG.
2 may have a crystal defect D. The cause may be due to the following reasons.

(1) Stress concentration occurs at corner edge portions E1 and E2 due to side wall oxidation performed after formation of trench 32, and the crystal is damaged. Further, the trench 32 is damaged by a film stress or the like when the filling material is buried. Then, these damages are synergistically generated to generate a crystal defect D.

(2) When high-concentration impurities are introduced for forming source / drain regions, that is, at the time of ion implantation, an amorphous region 6 is formed in the corner edge portion E1 of the trench 32. In the process in which the amorphous region 6 is solid-phase grown by the heat treatment, the corner edge E
1 finally grows in solid phase. For this reason, a misfit occurs at the corner edge portion E1, which becomes a crystal defect D.

In a region where a crystal defect D generated for the above-described reason exists, a leak current is likely to occur. In general, in a configuration in which the trench 32 is buried to perform element isolation (trench isolation) as described above, the generated leakage current is reduced by a normal LOC.
It is known that it is one or two orders of magnitude larger than the element isolation by the OS structure.

Therefore, as one of countermeasures, the corner edges E1 and E2 of the trench 32 are smoothed and the trench 3
It has been required to reduce the stress applied to the semiconductor substrate 1 at the time of the side wall oxidation treatment or the heat treatment for activating the impurities.

An object of the present invention is to provide a semiconductor device capable of preventing the occurrence of crystal defects by forming a corner of a trench to have a smooth shape in order to meet the above demand.

[0014]

A semiconductor device in which a trench is provided in a semiconductor substrate, wherein the trench comprises:
The present invention relates to a structure in which a portion near the substrate surface is formed in a tapered shape expanding toward the surface, and a trench bottom portion is formed in a rounded shape.

[0015] The present invention is a manufacturing method of a semiconductor device trenches in a silicon substrate is provided, and forming an oxide film by thermal oxidation on the silicon substrate, a multi one layer on said oxide film forming a crystalline silicon insulating film, the polycrystalline silicon insulating film and by removing a portion of the oxide film and forming an opening the silicon substrate is exposed, the polycrystalline silicon insulating film and the Forming a USG (Undoped Silicate Glass) insulating film on the opening, removing the USG insulating film while leaving the USG insulating film formed on the side surface of the opening, Forming a tapered V-shaped groove from the opening by using an alkaline etching solution; and forming the U-shaped groove formed on the side surface of the opening.
A step of vertically etching the bottom of the V-shaped groove of the silicon substrate using the SG insulating film as a mask, thereby forming a trench in the semiconductor substrate.

In the method of manufacturing a semiconductor device described above, the semiconductor substrate is a silicon substrate having a (100) surface.

The method of manufacturing a semiconductor device, further comprising: filling a predetermined filling material in the formed trench to form a buried portion; and oxidizing the substrate surface side of the buried portion by heat treatment. And selectively forming an oxide film on the upper portion of the trench.

[0018]

According to the present invention, the portion of the trench near the substrate surface has a tapered shape expanding toward the substrate surface. For this reason, the intersection angle between the side wall near the surface of the trench and the substrate surface becomes large, and the stress concentration at the corner of the trench can be reduced in the oxidation of the side wall of the trench, and the generation of crystal defects can be prevented.

Further, in the present invention, the V-shaped groove is formed with high dimensional accuracy by etching the semiconductor substrate from the opening thereof using an alkali etching solution. This allows
The plane orientation near the substrate surface where crystal defects are likely to occur is removed. Therefore, at the time of oxidation treatment or heat treatment performed after the formation of the trench, the crystal of the semiconductor substrate is not damaged at the corner of the trench, and the generation of crystal defects can be prevented.

Further, after forming the V-shaped groove, the bottom of the V-shaped groove is etched in the vertical direction of the substrate using the second insulating film remaining on the side surface of the opening as a mask. Thereby, the lower region of the trench is formed while the tapered shape of the V-shaped groove near the substrate surface is maintained, and the bottom of the trench has a round shape reflecting the V-shaped shape of the bottom of the V-shaped groove. . Therefore, the concentration of stress is also reduced at the bottom of the trench,
It is possible to prevent the occurrence of crystal defects at the bottom of the trench during the subsequent oxidation treatment or the like.

The surface of the semiconductor substrate is (10)
When the semiconductor substrate is etched from the opening with an alkaline etchant using the silicon substrate of the 0) plane, anisotropic etching is performed until the (111) plane of the silicon crystal is exposed, and the depth corresponding to the width of the opening Etching stops automatically when the (111) plane is exposed. In addition, etching from the opening toward the surface of the substrate is performed by first etching the upper part of the substrate.
It stops at the portion where the insulating film exists. As described above, it becomes possible to form a V-shaped groove having a width and a depth corresponding to the pattern of the opening very easily and with high dimensional accuracy.

Furthermore, in the present invention, a predetermined filling material is filled in a trench formed in the semiconductor substrate to form a filling portion, and an oxide film is formed on the filling portion. By using such a trench and a buried portion for element isolation of a semiconductor element formed on a semiconductor substrate after the formation thereof, an element isolation structure with a small area and a small leak current can be obtained. High breakdown voltage can be realized.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited by the following examples.

First, the configuration of the semiconductor device of this embodiment will be described with reference to FIGS. For example, the trench 2 formed in the semiconductor substrate 1 has a tapered V-shaped groove 17 whose portion near the substrate surface expands toward the substrate surface.
From the bottom of the V-shaped groove 17.
The groove further extends in the vertical direction of
Are formed. The trench bottom 19 at the lower portion 18 of the trench has a rounded round shape (see FIG. 2A). In this embodiment, single-crystal silicon having a (100) plane is used as the semiconductor substrate 1.

As shown in FIG. 1, an oxide film (SiO 2) 20 obtained by thermally oxidizing the side wall of the trench 2 is formed inside the trench 2. A buried portion 3 is formed by burying an insulating burying material such as polycrystalline silicon.

A thick oxide film (LOCOS portion) 4 is selectively formed on the substrate surface side of the buried portion 3. In addition,
The LOCOS portion 4 is formed to protrude from the upper part of the trench 2 toward the surface of the substrate. Then, the trench 2 and the insulating buried portion 3 buried in the trench 2
And the LOCOS section 4 constitute a trench-type element isolation section (trench isolation) for electrically isolating a semiconductor element.

After the formation of the trench isolation constructed as described above, for example, a MOS transistor is formed on the semiconductor substrate 1 as shown in FIGS. 1 (a) and 1 (b). Specifically, when the gate electrode 5 is formed on the semiconductor substrate 1 as shown in FIG. 1A, high-concentration impurities are implanted (ion-implanted) into the semiconductor substrate 1 using the gate electrode 5 as a mask. Thus, an amorphous region 6 is formed. Further, by performing a heat treatment (annealing), the impurities are activated and the source / drain regions 26 are formed. The end of the source / drain region 26 of the MOS transistor formed in this way is shown in FIG.
As shown in the figure, the portion partially overlaps the corner portion E of the trench 2.

Here, the trench isolation using the trench 2 of this embodiment as shown in FIG. 2B and the conventional rectangular trench 32 as shown in FIG. This is compared with a case where a trench isolation is configured by using the same.

As is clear from FIGS. 2B and 2D,
In both the semiconductor device of this embodiment and the conventional semiconductor device, the source / drain (amorphous) region 6 overlaps the corner E or the corner edge E1 of the trenches 2 and 32.

However, in the present embodiment, the corner E of the trench 2 has a tapered shape, and the damage to the crystal due to stress concentration generated during the side wall oxidation process of the trench 2 is shown in FIG. 1A. The structure is such that the damage received by the crystal during the ion implantation for forming the source / drain regions is not added synergistically to the corner portion E. Furthermore, the trench bottom 19 is also
Since the shape is a round shape, stress is prevented from being concentrated on the bottom portion 19 of the trench at the time of oxidizing the side wall of the trench 2 or the like.

On the other hand, in the case of the trench 32 having the conventional structure,
As shown in FIG. 2C, each corner edge portion E1, E2
Is highly likely to locally generate an oxidation-induced stress (for example, about 160 MPa) during the sidewall oxidation process of the trench 32, and there is a residual stress when the crystal of the amorphous region 6 is recovered (solid phase growth). It is highly possible that crystal defects occur at the edge portions E1 and E2.

As described above, in this embodiment, FIGS.
By adopting the trench structure shown in FIGS. 1A and 1B, it is possible to prevent the occurrence of crystal defects when the amorphous region 6 is crystal-recovered by the heat treatment (annealing) of FIG. 1B. Has become.

[Manufacturing Method] Hereinafter, a specific manufacturing method in this embodiment will be described with reference to FIGS.

First, as shown in FIG. 3A, a silicon substrate, which is the semiconductor substrate 1, is thermally oxidized to form an oxide film 11 on its surface (for example, 10 nm to 50 nm). 12 (for example, 100 nm to 6
00 nm) and a Si3 N4 (nitride film) 13 (for example, 100 nm to 250 nm). Further, USG (Undoped Slicate Glas) is deposited on the Si3N4 13 by CVD or the like.
s) 14 (for example, 100 nm to 250 n)
m).

Next, as shown in FIG. 3B, a multilayer CV is formed by RIE or the like using photolithography technology.
The D film and the oxide film 11 are etched to expose a part of the silicon substrate 1, and an opening 15 for forming an element isolation region is formed.
To form

After the opening 15 is formed, the USG 14 formed by CVD and the opening 1 are formed as shown in FIG.
USG 16 is further formed on CVD 5 by CVD or the like (for example, 200 nm to 500 nm).

Then, the USG 16 is etched by RIE, and as shown in FIG. 3D, the USG film 16 is etched while leaving the USG 16 on the side wall of the opening 15 for forming an element isolation region. A side wall (USG 16) 16 'is formed on the side wall of the portion 15. In addition,
The size of the opening for performing trench etching on the silicon substrate 1, that is, the gap between the sidewalls 16 'is adjusted by the sidewall length (the thickness of the USG 16).

Next, the silicon substrate 1 is anisotropically etched from the opening region of the side wall 16 'using an alkaline etching solution, thereby forming a V-shaped groove 17 as shown in FIG.
To form At this time, if the silicon substrate 1 is subjected to RIE beforehand under the width of the opening 15 or less and then alkali etching, the formation speed of the V-shaped groove 17 is increased.

In the above alkali etching, for example, when the silicon substrate 1 having a (100) surface is etched with a predetermined alkaline etching solution, the etching is automatically stopped at the point where the (111) surface of the silicon crystal is exposed (the etching speed is reduced). descend. Therefore, the formed V
The depth of the groove 17 depends on the gap between the openings 15. Further, in the region where the oxide film 11 exists on the semiconductor substrate 1, the etching in the direction parallel to the substrate surface is stopped. Therefore, the V-shaped groove 17 obtained by alkali etching
Has extremely high dimensional (depth and width) accuracy.

Further, as described above, the vicinity of the substrate surface is formed by the V-shaped groove 17, so that at the corner E of the trench, the intersection angle between the side wall of the trench (side wall of the V-shaped groove 17) and the substrate surface is reduced. It is getting bigger and smoother.

Next, the silicon substrate is anisotropically etched from the opening region of the side wall 16 'by trench etching by RIE. Thereby, without damaging the tapered shape in the vicinity of the surface of the V-shaped groove 17, the trench lower portion 18 is formed in a direction extending vertically from the bottom of the V-shaped groove 17 as shown in FIG. In addition,
Since trench etching is performed from the bottom of the V-shaped groove 17, the shape of the trench bottom 19 is a round shape reflecting the bottom shape of the V-shaped groove 17.

After the formation of the trench lower portion 18, the side wall 16 'of the opening 15 is removed by wet etching. Further, as shown in FIG. 4 (b), the side wall of the trench 2 is thermally oxidized by a heat treatment to form an oxide film (SiO2) 2.
0 is formed. At the time of this heat treatment, the corner portion E in the vicinity of the substrate surface of the trench 2 is tapered, so that, for example, the residual stress generated on the substrate surface at the time of oxidation of the side wall becomes smaller by about 20 MPa immediately after the oxidation than in the conventional case. In addition, since the bottom 19 of the trench is rounded and there is no corner edge unlike the related art, the concentration of stress generated in this region can be reduced.

Further, as shown in FIG. 4C, a buried portion 3 is formed by burying a burying material in the trench 2 whose sidewall has been oxidized. The filling material is not limited as long as it can form trench isolation. For example, SiO2 or BPSG (Boro Phos Silicate Glass
) And other flattening materials such as impurity-containing glass. In this embodiment, the structure is such that polycrystalline silicon is embedded in the trench 2 by CVD.

Next, as shown in FIG. 4D, a thermal oxidation treatment is performed to selectively oxidize the surface of the polycrystalline silicon, thereby
An OCOS part 4 is formed. In the case where BPSG is used as a filling material, a structure may be employed in which polycrystalline silicon is further formed on the buried BPSG, and this polycrystalline silicon is selectively oxidized to form the LOCOS portion 4.

After the formation of the LOCOS portion 4, a gate insulating film 21 of the MOS transistor is formed by thermal oxidation, and a polycrystalline silicon film is formed on the gate insulating film 21 by CVD or the like. Then, by performing a photolithography step (resist step and RIE), a gate electrode 5 made of polycrystalline silicon is formed as shown in FIG.

When ion implantation for forming source / drain regions is performed using the formed gate electrode 5 as a mask, an amorphous region 6 is formed in the region into which the impurities have been implanted, as shown in FIG. .

Thereafter, recovery annealing by heat treatment is performed. By this annealing, the crystal is recovered in the direction indicated by the arrow in FIG. Here, as described above, the corner portion E is tapered near the substrate surface of the trench 2 and the plane orientation near the semiconductor substrate surface where crystal defects easily occur is removed. In E, no misfit occurs and crystal defects are reliably prevented.

Further, since there is no corner edge at the bottom 19 of the trench, crystal defects are unlikely to occur in the bottom 19 during each process.

In the above embodiment, a description has been given of a configuration example in which the trench is used as a trench isolation for element isolation. However, the present invention is not limited to this. It may be used as a trench capacitor used for a memory or the like.
Even when the trench having the structure of this embodiment is used as a trench capacitor, it is possible to prevent the occurrence of crystal defects and to reduce the leak current. For this reason, the retention time of the stored contents can be extended, which contributes to the improvement of the reliability of the memory and the high integration of the memory.

[Brief description of the drawings]

FIG. 1 is a view schematically showing a manufacturing process in an example of the present invention.

FIG. 2 is a diagram conceptually illustrating the operation of the present invention and a conventional configuration.

FIG. 3 is a diagram illustrating a manufacturing process according to an example of the present invention.

FIG. 4 is a view illustrating a continuation of the manufacturing process of FIG. 3;

FIG. 5 is a diagram illustrating a continuation of the manufacturing process of FIG. 4;

FIG. 6 is a diagram showing a conventional technique.

[Explanation of symbols]

1 semiconductor substrate, 2 trench, 3 buried part, 4
LOCOS portion, 5 gate electrode, 6 amorphous region, 17 V-shaped groove, 18 trench lower portion, 19 trench bottom portion, 26 source / drain region.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/108 (72) Inventor Susumu Sugiyama 41-Cho, Yakumichi, Nagakute-cho, Aichi-gun, Aichi Prefecture 56) References JP-A-63-234534 (JP, A) JP-A-5-74929 (JP, A) JP-A-63-115348 (JP, A) JP-A-59-149030 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) H01L 21/76 H01L 21/762 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/108

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor device in which a trench is provided in a silicon substrate, comprising: forming an oxide film on the silicon substrate by thermal oxidation; and forming one layer of polycrystalline silicon on the oxide film. Forming an insulating film; forming an opening exposing the silicon substrate by removing a part of the polycrystalline silicon insulating film and the oxide film; and forming the opening on the polycrystalline silicon insulating film and the opening. USG on top
(Undoped Silicate Glass) a step of forming an insulating film; a step of removing the USG insulating film while leaving a USG insulating film formed on a side surface of the opening; and an alkali etching of the silicon substrate from the opening. A step of forming a tapered V-shaped groove by etching using a liquid; and using the USG insulating film formed on the side surface of the opening as a mask, vertically aligning the bottom of the V-shaped groove of the silicon substrate. A method of manufacturing a semiconductor device, comprising: forming a trench in a semiconductor substrate by: 2. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon substrate is a silicon substrate having a (100) surface. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising: filling a predetermined filling material in the formed trench to form a filling portion; and heat-treating the filling portion. Oxidize the substrate surface side of
Selectively forming an oxide film on the upper part of the trench.