JP3306497B2 - Rounding circuit in floating point multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to floating point multipliers and, more particularly, to a method and apparatus for increasing the rounding speed in such multipliers.

[0002]

2. Description of the Related Art Various configurations for forming a high-speed multiplication circuit for use in a computer have been proposed. Basically, by determining a plurality of partial products, each shifted one bit to the left from the preceding partial product, two n
Implements the product of bit binary operands. Next, the partial products are added to arrive at the result. To quickly add partial products, a binary tree configuration has been suggested in which individual partial products are grouped in pairs and the pairs of partial products are added in parallel by a carry-save adder. The result of the addition of these partial products is again grouped in pairs and the groups are likewise added in parallel by another carry-save adder. This process is continued until the last two partial products have been added to obtain a product. 1987 2
Monthly IEEE Journal of Solid-
High Speed M of Harata et al., Published in State Circuits SC-22, Volume 1, No. 1.
ultraplier Using a Redunda
The nt Binary Adder Tree describes such a circuit. A carry propagation adder may be used to add the carry and carry of the two last partial products from the previous stage of the binary tree multiplier.

[0003] These circuits may be used for integer multiplication or for generating mantissas at floating point. When using a multiplier circuit in a floating-point multiplier configuration, the multiplier circuit must produce a result that contains twice as many bits as it would with machine processing, so the result must be rounded. There are many.
For example, the standard for double precision binary numbers requires 53 bits. The product of two 53-bit binary numbers is 106 bits long. However, the double precision result uses only the upper 54 bits of this product, and the most significant bit indicates overflow. The lower 53 bits are used only to determine whether a carry is generated from the lower bits, whether rounding is required, and the precise rounding value.

In order to perform product rounding, first, the mantissa must be normalized. In a binary multiplication using two normalized operands, which only requires a one bit shift to the right of the mantissa, there is only one significant bit to the left of the binary point and the exponent Power should increase. Until the mantissa is normalized, the bit position at which rounding is performed is not known. Although the low order bits of the product are only used to generate carry and determine rounding,
Before the upper bit carry propagation adder can begin operation, the lower bit carry result must be generated. If carry addition of the upper bit is not completed, the mantissa cannot be extracted and cannot be normalized, so that the operation generates a lower carry as a whole, and the carry bit propagates through the upper bit. You usually have to wait for it to go. Therefore, the carry from the lower bit is in the critical path.

In such a multiplier, if normalization occurs to generate a rounding condition, if necessary, 1 is added to the normalized mantissa at the least significant bit, and the rounding result is obtained. It typically occurs. This scheme uses a carry propagation adder at the output of the multiplier tree and uses an incrementer at the output of the adder to generate rounding.
A common scheme to increase the speed of operation of this configuration is 2
One rounding circuit is used in parallel. One circuit assumes that the mantissa overflows, and the other circuit assumes that the mantissa does not overflow. When the most significant bit of the unrounded mantissa becomes available, select the correct result. In either case, a typical prior art floating point multiplier would wait for the result of carry propagation of the lower bits.

[0006]

Accordingly, it is an object of the present invention to increase the speed at which a floating point multiplier circuit reaches a result. Another, more specific objective of the present invention is to eliminate most of the delays of the floating point multiplier circuit caused by having to wait for the result of carry propagation from the lower bits.

[0007]

SUMMARY OF THE INVENTION The above and other objects of the present invention are based on the assumption that no carry-in has occurred without waiting for the generation of carry-in from the lower bits, and that the upper bits of the mantissa have not been generated. Means for supplying the upper bits of the mantissa, without waiting for the generation of the carry-in from the lower bits, assuming that the carry-in has occurred; and the actual carry-in from the lower bit adder. Means for providing a first set of low-order bits for the mantissa selected for a case without mantissa overflow based on the rounding condition; and based on the actual carry-in from the low-order bit adder and the rounding condition, Means for providing a second set of lower bits for the mantissa selected for the overflow case; whether carry-in propagates through the lower bits of the mantissa, and Implemented in rounding circuit of a floating-point multiplier and means for selecting upper and lower bits of the mantissa based on whether overflow has occurred.

[0008] These and other objects and features of the present invention will be understood by reference to the following detailed description, taken in conjunction with the accompanying drawings. In the drawings, the same reference numerals indicate the same elements throughout several drawings. [Notation and Terminology] In the following detailed description, there is a portion in which an operation regarding a data bit in a computer memory is indicated by a symbol. Such descriptions and displays are the means used by those skilled in data processing techniques to most effectively convey the substance of their work to others skilled in the art. The steps are those requiring physical manipulations of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated. At times, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like, primarily because they are terms commonly used. It should be remembered that all of these and similar terms are to be associated with the appropriate physical quantities and are merely labels attached to such quantities for convenience. Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with intelligent operations performed by an operator, but any of the operations described herein that form part of the present invention. However, such operator capabilities are unnecessary and often undesirable. The operation is an operation of a machine. Useful machines for performing the operations of the present invention include general purpose digital computers or other similar devices. In all cases, it should be noted that there is a clear distinction between the method operation when operating the computer and the method of calculation itself. The present invention relates to an apparatus for processing electrical or other physical (eg, mechanical, chemical) signals to operate a computer in generating other desired physical signals.

[0009]

DETAILED DESCRIPTION OF THE INVENTION To increase the speed at which a floating point multiplier reaches the end result, the present invention eliminates the generation of lower carry bits from the critical path. To understand the operation to accomplish this, FIG. 1 shows several diagrams representing various conditions at the output of the carry propagation adder used to generate the final product. In any of the cases shown there, this product MAN_PR [105: 5
2] are operands generated by the binary tree structure of the multiplier (two operands S1 [105: 52] and S1).
2 [105: 52] is the output of the carry propagation adder generated by adding the upper bits. The first four cases assume that there is no mantissa overflow that requires normalization, and the bottom four cases assume that there is a mantissa overflow.
In each case, the mantissa value is shown as the upper value, and the four possible conditions for the two least significant bits are shown below.

In the first to fourth cases, since there is no mantissa overflow, it is not necessary to normalize the mantissa (increase the exponent and shift it to the right), and therefore, the lower order by the carry propagation adder is not necessary. The rounding and carry bits supplied from the bit addition are provided at the same bit position. In the first case, there is no carry from bit 51 of the lower bits and no rounding is required. Therefore, the mantissa MAN_PR [105: generated by the carry propagation adder]
52] is already correct. In the second case, the carry bit (C51 = 1) from the lower bit of the carry propagation adder
Is generated, but no rounding bits are generated because rounding is not required. As can be seen, the mantissa MAN_PR
The carry from the least significant bit propagates through the position of bit 54 of the mantissa only if the two least significant bits of [105: 52] are both one. This is illustrated in FIG.
It is represented by a series of points on the left in the result of combining carry and mantissa. Therefore, only the mantissa MAN_PR [105: 52] having 1 in the two least significant bit positions overflows due to the presence of the carry bit C51.

The third case (there is no carry bit and there is a rounding bit) is the same as the second case since only one 1 is added at the least significant bit position of the mantissa. Therefore, in the third case, only the mantissa MAN_PR [105: 52] having 1 in the two least significant bit positions is overflowed by the presence of the carry bit C51.

In the fourth case, both the carry bit C51 and the round bit are generated from the lower bits. When these two bits are added, 1 is added at the bit position next to the mantissa. As can be seen, only the mantissa value having a 1 in the next lower bit position propagates the carry through mantissa bit 54. Again, they are indicated by the points to the left of the two least significant bits in the fourth case example.

The fifth to eighth cases assume that the mantissa must be normalized because of the overflow of the mantissa. This normalization shifts the mantissa bit by one position to the right, while the carry bit continues to be injected into the mantissa bit 52 while the rounding bit from the lower carry propagation adder is replaced by the mantissa bit 53. Has the effect of injecting into the level.

Therefore, the rounding bit and the carry bit are 2
Given in two different bit positions. In the fifth case, there is no carry from bit 51 of the lower bit, and no rounding is required. Therefore, the mantissa MAN_PR [105: 52] generated by the carry propagation adder is already correct regardless of the least significant bit of the mantissa. However, in the sixth case, the carry bit (C51 = 1) is generated from the lower bits of the carry propagation adder, but the rounding bit is not generated. As can be seen, the mantissa MAN_PR [10
5:52], the carry from the least significant bit is only the bit 54 of the mantissa.
Propagating through the location of This is also indicated by a series of points on the left side of the result of FIG. Therefore,
Mantissa MAN_PR with 1 in two least significant bit positions
[105: 52] Only the carry bit C51 may cause overflow.

The seventh case (there is no carry bit,
The rounding bit is present) is identical to the fourth case where a single 1 is added at the next lower bit position after the mantissa. The mantissa value MAN_P having 1 in the next lower bit position
Only R [105: 52] may be flooded by a one present in the next lower bit position and propagate the carry through the mantissa bit 54.

In the eighth case, the carry bit C51
And a rounding bit. When the two bits are added, a 1 appears in both least significant bit positions. As can be seen, the carry does not propagate through the mantissa bit 54 only if the mantissa value has a 0 in both least significant bit positions. Similarly, their propagation is indicated by the points to the left of the two least significant bits in the eighth case example.

As described above, by generating a pair of mantissas of a mantissa having no carry through the bit 54 and a mantissa having a carry through the bit 54, all conditions expressed in the above case can be easily satisfied. It can be seen that this can occur. These mantissas can be generated without waiting for carry from the lower bits. The mantissas are fed to a series of multiplexers, whose outputs are rounded,
As selected by the actual occurrence of lower carry and overflow, considerable time can be saved when obtaining results from the multiplier.

FIG. 2 is a block diagram of a circuit for realizing the present invention. The circuit 10 includes a first carry propagation adder 12
And a second carry propagation adder 13. The first carry propagation adder 12 has a pair of operands S as inputs.
1 [105: 52] and S2 [105: 52] are received, the two values are added, and the mantissa value MAN_0 [5
3: 0]. Since adder 12 receives a carry-in of 0 from the lower bit, it generates a mantissa assuming that there was no carry in bit 51. The second carry propagation adder 13 receives a pair of operands S1 as input.
[105: 54] and S2 [105: 54] are received,
The two values are added and the mantissa value MAN_4 [53:
2]. Adder 13 receives a carry-in of one from the least significant bit at the level of bit 54, and thus generates a mantissa assuming that the carry has propagated through bit 53.

Thus, these two carry propagation adders have no carry-in at bit 52 and bit 5
Assuming that the carry-in has propagated to 4, bit 5
From 4 to 105, a mantissa bit is generated. Adder 1
The two least significant bits of the mantissa from 2 are dropped and the remaining digits from the two adders 12 and 13 are
One pair of multiplexers 1 as one upper value [53: 2]
5 and 16 respectively. Therefore, if the operation by the carry propagation adders 12 and 13 is completed,
Rather than waiting for the carry resulting from the addition of the lower bits of the operands, the mantissa value is immediately available except for the two least significant bits. Multiplexers 15 and 16
The value selected by is determined by the other circuits in FIG.

While the adders 12 and 13 are operating to generate the upper bits of the two possible mantissa values, the combinational logic 18 uses the lower bits S1_M of the two operands.
[50: 0] and S2_M [50: 0] are added to generate a carry bit 51 and a sticky bit as output. The two bits are used to determine the actual rounding and carry required at the upper bit positions. 2
The IEEE Standard 754 for Hexadecimal Floating-Point Arithmetic creates a default rounding mode of "round to nearest", and in the case of Thailand, "round to nearest / even". / Round to even number) ". IE to solve Thailand
Generate a "sticky bit" according to EE754. The sticky bit has a value of 1 when any of the lower bits passing through the guard bit position of either of the two operands is 1. If there is no one bit, the sticky bit is one.

The IEEE defines not only the default mode described above but also other three modes. They are rounding toward zero, rounding toward positive infinity, and rounding toward negative infinity. The rounding values associated with these rounding modes would each be generated when the value of the sticky bit is known.

The three bits [5] of each of the operands S1 and S2 which change according to rounding, carry and overflow
3:51] is supplied to the 3-bit adder circuit 20.
This circuit 20 carries a carry bit C51 and a sticky bit generated by the adder 18 and a signal RAN_MO indicating which of the four rounding modes is desired.
The DE is further received. The adder circuit 20 adds the signals in a manner according to a rounding mode, and outputs an
And an output signal RV. Signal RN is a round value to be used when there is no mantissa overflow, and RV is a round value to be used when there is mantissa overflow.

The 2-bit adder 22 is supplied with the RN value of the least significant bit position. The adder 22 generates 2 for the mantissa by the carry propagation adder 12 and drops the mantissa when the mantissa is transferred to the multiplexers 15 and 16.
The least significant bits [52:51] (MAN_0 [1:
0] are also supplied. Their values,
The value of the carry bit 51 is combined with the final mantissa of 2
Generate the value RDO [1: 0] for the two least significant bits. The combination also generates the signal CN. The value of signal CN indicates whether there is a carry-in to bit 2 of the mantissa when overflow of the mantissa is not included. The output from the multiplexer 15 is selected using the presence or absence of the signal CN. If there is a carry, the value generated by the adder 13 receiving the carry-in (MAN_4 [53:
Select 2). When there is no carry, the value MAN_0 generated by the adder 12 without carry-in is output.
Select [53: 2]. Therefore, the signal CN from the adder 22 correctly selects one of the two partial mantissas depending on whether the carry-in is propagated to bit 2 of the final mantissa.

Similarly, the RV value is a two bit adder 2 at the next lower bit position associated with the least significant bit position of one.
3 is supplied. The adder 23 generates the mantissa by the carry propagation adder 12, but the multiplexer 1
The two least significant bits not transferred to 5 and 16 [52:
51] (shown here as MAN_0 [1: 0]). These values and the carry bit 51
And the possible values RD4 [1: for the two least significant bits of the mantissa to be used in the case of mantissa overflow
0]. The combination further generates a value CV that indicates whether there is a carry-in to bit 2 of the mantissa when a mantissa overflow occurs. This signal CV
The output from the multiplexer 16 is selected by using the presence or absence of. If there is a carry, the adder 13 that receives the carry-in selects the value MAN_4 [53: 2]. If there is no carry, the value MAN_0 [53:
Select 2). Therefore, the signal CV from the adder 23
Will correctly select one of the two partial mantissas depending on whether the carry-in is propagated to bit 2 of the final mantissa.

Finally, the upper bits transferred by the multiplexer 15 are communicated with the two lower bits from the adder 22 and supplied to the third multiplexer 25 as one input. Similarly, the upper bit value transferred by multiplexer 16 is communicated with the two lower bits provided by 2-bit adder 23 and provided to third multiplexer 25 as another input. The output generated by multiplexer 25 is controlled by the logic terms shown to the right of multiplexer 25. If overflow from the mantissa of the adder 12 without carry-in occurs, overflow must occur from the mantissa of the adder 13 with one carry-in. However, the opposite is not true. That is, the overflow of the adder 13 may occur due to one carry-in, but the adder 12 does not need to overflow.

Therefore, when the upper bit generated by the carry propagation adder 12 is 1 (indicating a mantissa overflow), the value from the multiplexer 16 and the value generated by the adder 23 are selected. Similarly, the carry propagation adder 1
The upper bit where 3 occurs is 1 (indicating mantissa overflow) and there is a carry-in to bit 2 of the final mantissa (C
If N = 1), select the value from multiplexer 16 and the result generated by adder 23. If neither of these events occurs, select the mantissa generated by multiplexer 15 and adder 22.

There is one case where the circuit of FIG. 2 as described above does not produce a correct result. There is a condition that all bits of the two operands S1 and S2 immediately to the left of bit 51 are one. If one is added to bit 51, the carry should propagate to the left through each step. Such a situation does not occur because no propagation is performed by the adder 13 that performs the addition starting from bit 54. Thus, a circuit 30 consisting of a series of half-adders is used to assimilate the initial carry bits when the output of the multiplier tree is an all ones string immediately to the left of bit 51.

As will be appreciated by those skilled in the art, once the operation of the carry propagation adder for the upper bits is completed, the circuit of the present invention does not have to wait for the carry from the lower bits before starting operation. Immediately generate all bits except the least significant bit of the possible mantissa to determine overflow. Therefore,
The circuit need only evaluate the value of the carry-in to bit 51, the sticky bit, and the rounding mode over three bit positions to provide the lower bits. Thus, carry bit C51 need only propagate through three bit stages, rather than through all stages of the higher carry propagation adder. Thus, the circuit of the present invention provides results much more quickly by substantially eliminating carry bits provided by the lower carry propagation adder from the critical path.

Although the present invention has been described with reference to a preferred embodiment, it will be understood that various modifications and changes can be made by those skilled in the art without departing from the spirit of the invention.
Therefore, the present invention should be evaluated by the appended claims and the following embodiments.

1. Means for selecting the upper and lower bits of the mantissa based on whether the carry-in propagates through the lower bits of the mantissa and whether or not the mantissa overflows provide a set of lower bits related to the mantissa. 2. A rounding circuit for a binary tree floating point multiplier according to claim 1, further comprising: means for detecting whether a carry-out is generated by each of the means for performing the carry-out.

2. The means for selecting the upper and lower bits of the mantissa based on whether or not the carry-in propagates through the lower bits of the mantissa and whether or not the mantissa overflows are provided by means for supplying the upper bits of the mantissa, respectively. 2. The rounding circuit for a binary tree floating-point multiplier according to claim 1, further comprising means for evaluating a condition of a most significant bit among supplied bits.

3. The means for selecting the upper and lower bits of the mantissa based on whether or not the carry-in propagates through the lower bits of the mantissa and whether or not the mantissa overflows are provided by means for supplying the upper bits of the mantissa, respectively. 2. A rounding circuit for a binary tree floating-point multiplier according to claim 1, further comprising means for evaluating a condition of a most significant bit among supplied bits.

4. The means for providing the first set of lower bits of the mantissa based on the actual carry-in from the lower bit adder and the rounding condition comprises means for providing the upper bits of the mantissa assuming that no carry-in has occurred. A first addition that adds the least significant bit generated, the rounded value generated from the lower bit, and the carry-in from the lower bit such that their values would be added without mantissa overflow. Means for providing a second set of low-order bits of the mantissa based on the actual carry-in from the low-order bit adder and the rounding condition, the high-order bits of the mantissa being assumed as if no carry-in had occurred. The least significant bit generated by the supplying means, the rounded value generated from the lower bit, and the carry-in from the lower bit are added together with their mantissa overflow. Binary tree floating point multiplier rounding circuit according to the above item 1, wherein comprising a second adder for adding as would be.

[Brief description of the drawings]

FIG. 1 shows various overflows in a floating point multiplier circuit;
FIG. 7 shows possible conditions as a result of carry-in and rounding possibilities.

FIG. 2 is a block diagram of a circuit configured according to the present invention.

[Explanation of symbols]

 12 First Carry Propagation Adder 13 Second Carry Propagation Adder 15, 16 Multiplexer 18 Combination Logic 20 3-Bit Adder Circuit 22, 23 2-Bit Adder 25 Multiplexer 30 Series of Half Adders

──────────────────────────────────────────────────続 き Continuing from the front page (73) Patentee 591064003 901 SAN ANTONIO ROAD PALO ALTO, CA 94303, U.S.A. S. A. (56) References JP-A-3-18925 (JP, A) JP-A-2-231629 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 7/52 310 G06F 7/38

Claims (1)

(57) [Claims] 1. Two binary operand bits [n:
0] in the floating point multiplication of bits [2n + 1: 0]
A rounding circuit for a binary tree floating point multiplier, wherein the binary tree floating point multiplier converts a partial product of a plurality of pairs of bits [2n + 1: 0] into a plurality of carry propagation adders. And the first addition means (12) for providing the first mantissa bits [n + 1: 0], wherein carry-in does not occur at the level of bit n. Assuming that the carry-in is not generated from the bits [n-1: 0] of the first and second partial products, the first and second partial products of the bits [2n + 1: n] are not waited for. A first adding means (12) for providing a first mantissa bit [n + 1: 0] by performing addition; a second adding means (13) for providing a second mantissa bit [n + 1: 2]; ) And carry-in does not occur at the level of bit n + 2 And adding the first and second partial products of bits [2n + 1: n + 2] without waiting for the generation of carry-in from bits [n + 1: 0] of the first and second partial products. And a first circuit means for providing a first set of bits of the final mantissa [1: 0] by providing a first mantissa bit [n + 1: 2]. (22) to be selected based on the actual carry-in from the addition of the first and second bits [n−2: 0] and the rounding condition in the case where there is no mantissa overflow. , A first circuit means (22) for providing a first set of bits [1: 0] of the final mantissa, and a second circuit means (22) for providing a second set of bits [1: 0] of the final mantissa. 23) to calculate the actual carry from the addition of the first and second bits [n−2: 0]. A second circuit means (23) for providing a second set of bits [1: 0] of the final mantissa as to be selected in the case where there is a mantissa overflow based on the key-in and the rounding condition; A multiplexer means (15, 16, 25) for selecting the bits [n + 1: 2] and bits [1: 0] of the final mantissa, and the bits [n + 1: 2] are added to the first adding means.
The bits of the first mantissa [n + 1:
2] and the second mantissa bits [n + 1: 2] given by the second adding means (13), the bits [1: 0] are converted to bits given by the first circuit means (22). [1: 0] the one set and the second circuit means
From the two sets of bits [1: 0] given in (23), based on whether the carry-in has propagated through bits [1: 0] of the final mantissa and whether a mantissa overflow has occurred, Multiplexer means for selecting
A rounding circuit in a floating-point multiplier, comprising (15,16,25).