JP3302819B2 - Selection signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a plurality of inputs, outputs,
The present invention relates to a device for generating a selection signal for switching and selecting an input / output signal or the like.

[0002]

2. Description of the Related Art In general, a switching device (multiplexer) for switching and selecting an analog input signal or an output signal is such that a plurality of switch means are driven sequentially by using the output of a decoder as a selection signal. .

[0003]

However, when the number of signals to be selected is known in advance, or when the number of signals to be selected is fixed and is on the same printed circuit board, it is good, but the number of signals to be selected varies. However, if the distance to the switch means is long or the number of signals is large, wiring using a signal from the decoder becomes complicated and difficult to cope with.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a selection signal generator capable of coping with a small number of signals even when the number of signals to be selected changes.

[0005]

According to the present invention, there are provided a plurality of flip-flop circuits in which an output terminal of a preceding stage is sequentially connected to an input terminal of a subsequent stage, and a first circuit for generating a reference signal at an input terminal of the first-stage flip-flop circuit. Pulse generating means, second pulse generating means for generating a clock pulse in each flip-flop circuit and sequentially generating a selection signal from an output terminal of each flip-flop circuit, and all the selection signals of each flip-flop circuit are not present And determine again the first
And a determining means for generating a pulse from the pulse generating means.

[0006]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a processing unit such as a microcomputer, which includes a first pulse generating unit 11, a second pulse generating unit 12, a discriminating unit 10, and the like. The reference signal E1 generated by the first pulse generating means 11 is supplied to, for example, an input terminal (D terminal) of a first D-type (first-stage) flip-flop circuit 21, and an output terminal (Q terminal) thereof is connected to the first terminal. The flip-flop circuit 22 is connected to the input terminal (D terminal) of the second flip-flop circuit 22, the output terminal of the preceding flip-flop circuit is connected directly to the input terminal of the subsequent flip-flop circuit, and so on. Circuit An
Up to one another. Each output A1, A2,..., An of each flip-flop circuit 21, 22,.
Is a selection signal, but may be driven by drivers 31, 32,.

The clock pulse E2 of the second pulse generating means 12 is supplied to each of the flip-flop circuits 21, 22,.
n are simultaneously supplied via a line L1. Also, each flip-flop circuit 21, 22,.
, An of the n outputs via buffers 41, 42,... 4n which are open collector outputs or the like, and the presence or absence of a selection signal whose OR output E3 is output to the determination means 10 via the line L2. I do. Each of the flip-flop circuits 21, 22,..., 2n has a resistor R and a capacitor C.
Although a clear signal is stably applied when the power is turned on through a time constant circuit made up of such a circuit, it can be omitted.
Note that the number of flip-flop circuits can be arbitrarily increased or decreased.

Next, the operation will be described with reference to FIG. When the power is turned on, the flip-flop circuits 21, 22,... Are stably and unifiedly cleared by a time constant circuit, and their outputs A1, A2,. 4n, the input of the determination means 10 is at the H level.

Next, the first pulse generator 11 generates a first (first-stage) H-level pulse E1 having a predetermined width.
When the clock signal E2 is input to the flip-flop circuit 21 and subsequently the H-level clock pulse E2 is generated from the second pulse generating means 22, the output of the first flip-flop circuit 21 becomes H level because the input of the first flip-flop circuit 21 was H. . This H-level output Al is used as a selection signal via a driver 31 such as an inverter, and an L-level signal is output to a discriminating means 10 via a buffer 41. The discriminating means 10 recognizes the start of signal selection. . At this time, the outputs A2,..., An of the other flip-flop circuits 22,.

Next, after the pulse E1 becomes L level,
When the second clock pulse is generated from the second pulse generation means 12, the output of the first flip-flop circuit 21 becomes L level because the input of the first flip-flop circuit 21 was L, and the second flip-flop circuit 21 Is at H level, the output A2 is at H level. A selection signal is output from the output A2 via the driver 32,
The L level is output to the discriminating means 10 via.

Thereafter, each time the clock pulse E2 is sequentially generated, each flip-flop circuit sequentially generates a selection signal. Then, the output A of the last flip-flop circuit 2n
When n becomes H level, a selection signal An is generated, and the input of the determination means 10 is L. Next, when the pulse E2 is generated, the output An of the flip-flop circuit An becomes L, and the determination means 10 outputs H level because all the selection signals do not exist. As a result, the determination means 10 causes the first pulse generation means 11 to generate a pulse, and starts the operation of generating the above-described series of selection signals again.

[0013]

As described above, the present invention uses a plurality of flip-flop circuits in which a preceding-stage output terminal is connected to a succeeding-stage input terminal sequentially to generate a plurality of selection signals sequentially. Device. Therefore, the number of selection signals can be easily changed by increasing or decreasing the number of connection of the flip-flop circuits in series, and the number of signal lines is three in total including connection of flip-flops. Only wiring is not required, and wiring processing is extremely easy and flexible signal selection is possible.

[Brief description of the drawings]

FIG. 1 is a configuration explanatory view showing one embodiment of the present invention.

FIG. 2 is an operation explanatory diagram showing one embodiment of the present invention.

[Explanation of symbols]

 1 processing means 11, 12 pulse generating means 10 discriminating means 21, 22, ..., 2n flip-flop circuits 31, 32, ... 3n drivers 41, 42, ..., 4n buffers

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 17/00 G11B 15/10 501 P

Claims (1)

(57) [Claims] 1. A plurality of flip-flop circuits in which an input terminal of a subsequent stage is sequentially connected to an output terminal of a preceding stage, first pulse generating means for generating a reference signal at an input terminal of a first stage flip-flop circuit, and each flip-flop. A second pulse generating means for generating a clock pulse in the circuit and sequentially generating a selection signal from an output terminal of each flip-flop circuit; A selection signal generation device comprising: a determination unit configured to generate a pulse from the pulse generation unit.