JP2706011B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus comprising a main unit for performing data processing and an optional device selectively connected to the main unit.

[0002]

2. Description of the Related Art In a data processing device such as a personal computer or a word processor, various peripheral devices are selectively used. For example, various printers can be connected as an output device, and further, an optional device such as a cut sheet feeder or a postcard feeder is designed to be connected to the printer. As described above, in a device that performs data processing, a plurality of types of optional devices are generally selectively used in combination with a main device. Normally, it is necessary to perform different control for different types of optional devices, and the main device is configured to be able to detect the type of the optional device connected to the main device.

[0003] 2. Identify optional devices from the main unit
One configuration example is shown in FIGS. 5 and 6, reference numeral 1 denotes a main body device, and 2 denotes an optional device. The option device 2 is provided with switches S1, S2, S3 as code generation units for generating a type code of the option device, an option main circuit, and the like. However, these switches are not provided with switches as components, but are usually set in advance by a wiring pattern on a circuit board. An output port 3 and an input port 4 are connected to a main bus of the main unit 1. The output port 3 and the option main circuit 5 are connected by a plurality of control signal lines 6. Input port 4 and switches S1, S
2 and S3 are connected by a detection signal line 7, respectively. Further, the power supply voltage _VA is supplied from the main device 1 to the optional device. In the configuration shown in FIG. 5, each input terminal of the input port 4 is pulled up by resistors R1, R2, R3, and the other ends of the switches S1, S2, S3 are connected to ground. With this configuration, the main unit reads the on / off states of the switches S1, S2, and S3 via the input port 4. On the other hand, in the configuration shown in FIG. 6, a dedicated output line 8 for outputting a selection signal from the output port 3 is provided, and one ends of the switches S1, S2, and S3 are connected to the dedicated output lines, respectively. Are connected in common and returned to the input port 4 on the main unit via one detection signal line 7. The input section of the input port 4 is pulled up by the resistor R1, and the output section of the output port for outputting the selection signal is of an open collector type. With this configuration, the selection signal is sequentially set to the ground potential, and the level of the detection signal is read through the input port 4, whereby the states of the switches S1, S2, and S3 are detected.

[0004]

However, as shown in FIG. 5, in the method of reading the state of the code generators (S1, S2, S3) through a plurality of detection signal lines, the state of the code generator is not changed. As the number increases, the number of detection signal lines increases. In addition, as shown in FIG. 6, in the case where a selection signal is supplied to the code generation unit via a dedicated output line and reading is performed via one detection signal line, the number of states of the code generation unit increases. As a result, the number of dedicated output lines increases. In any case, the number of signals between the main device and the optional device increases. Therefore, when selecting and using a plurality of optional devices for the same interface of the main unit, the interface must be set to the maximum number of signals necessary for using the optional devices. Therefore, it has not been possible to extend the number of states of the code generator using an already determined interface to enable use of more types of optional devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing apparatus capable of identifying various types of optional devices by input from one detection signal line without using a dedicated signal output line. .

[0006]

SUMMARY OF THE INVENTION The present invention provides a main unit for performing data processing and outputting a plurality of control signals from an output unit, and an optional device connected to the output unit and operated by the control signal. In a data processing device comprising: a code generator that outputs a logical sum of several control signal lines to one detection signal line is provided in an optional device, and a timing signal is sequentially output to the control signal line; Code detection means for reading the state of the detection signal line to detect a code is provided in the main unit.

[0007]

The data processing device of the present invention comprises a main unit and an optional device connected by a plurality of control signal lines, and a code generator provided in the optional device includes a control signal line for some control signal lines. The logical sum is output to one detection signal line. Code detection means provided in the main unit sequentially outputs a timing signal to a control signal line and detects a code by reading the state of the detection signal line.

FIG. 1 shows a configuration example of a data processing apparatus according to the present invention.
Shown in In FIG. 1, reference numeral 1 denotes a main body device, and 2 denotes an optional device. A control signal is output from the output port 3 of the main unit 1 to the control signal lines 6a to 6d. The option main circuit 5 on the option device side includes control signal lines 6a to
It operates according to the control signal of 6d. The optional device 2 includes switches S1, S2 in this example between the detection signal lines 7 and 6b, 6c, 6d among the plurality of control signal lines.
2, a code generator composed of S3 is provided. The code generator outputs a logical sum of several control signal lines to one detection signal line 7. For example, when the switches S1 and S3 are on and the switch S2 is off, the logical sum of the control signal lines 6b and 6d is given to the detection signal line 7.
The code detecting means provided on the main unit 1 sequentially outputs timing signals from the output port 3 to the control signal lines 6a to 6d, and sequentially reads the state of the detection signal line 7 via the input port 4. Thus, the states of the switches S1, S2, and S3 are detected.

As described above, since the control signal line is also used, there is no need to provide a dedicated signal output line.
The optional device can be identified by the input of the book detection signal.

[0010]

FIG. 2 is a circuit diagram of a data processing apparatus according to an embodiment of the present invention. In FIG. 2, 1 is a main unit, and 2 is an optional device. The main device 1 and the optional device 2 are connected via control signal lines 6a to 6d, a detection signal line 7, a power supply line 10, a ground line 11, and the like. In the main unit 1, an output port 3 and an input port 4 are connected to the main bus of the main unit. A transistor circuit including resistors RA1 to RA8 and transistors Q1 to Q4 is connected to output terminals D1 to D4 of the output port 3. The collectors of the transistors Q1 to Q4 are connected to the control signal lines 6a to 6d, respectively, so that the control signal line output section of the main unit has an open collector type. Further, a pull-up resistor RB1 is connected to the input terminal D5 of the input port 4 to pull up the detection signal line 7. In the optional device 2, L1 to L4 are excitation coils of a four-pole pulse motor, one end of which is connected to each of the control signal lines 6a to 6d, and the other end of which is connected to the power supply line 10. S1, S2, and S3 are switches serving as a code generator, one end of which is connected to control signal lines 6d, 6c, and 6b, and the other end of which is a diode Di1.
A common connection is made at point α via Di2 and Di3. Resistors RC1, RC2, RC3, RC4 and transistor Q
5 and Q6 is a level conversion circuit for converting the potential at the point α into a logic level voltage (+ Vcc-GND).

The operation of the circuit shown in FIG. 2 is as follows. When the output terminal D1 of the output port 3 is at "H" level, Q1 is turned on, and the exciting coil L1 is excited through the path of + V _A → L1 → Q1 → GND. If the output terminal D1 is at "L" level, L1 is not energized because Q1 is off. Output terminal D2 of output port 3 is "H"
If it is a level, Q2 turns on and + V _A → L2 → Q2 →
A current flows through the GND path, and the exciting coil L2 is excited. Similarly, when the output terminal D3 is at "H" level, L3 is excited, and when D4 is at "H" level, L4 is excited. Thus, the pulse motor is controlled by the output timing control of the output terminals D1 to D4 of the output port 3.
The states of the switches S1 to S3 differ depending on the type of the optional device. For example, if S1 is conductive,
When the transistor Q4 is on, + V _A → RC1 → RC
A current flows through the path of 2 → Di1 → S1 → Q4 → GND,
The point α is substantially at the ground potential. As a result, the divided voltages of RC1 and RC2 are applied between the base and the emitter of transistor Q5, and Q5 is turned on. When Q5 turns on, RC3
The divided voltage of RC4 is applied between the base and the emitter of transistor Q6, turning on Q6. As a result, the input terminal D5 of the input port 4 becomes "L" level (ground potential). If the switch S1 is off, the transistor Q
Even when 4 is turned on, the current loop is not formed, and the point α has a potential of approximately + _VA . As a result, the base current of Q5 does not flow, and Q5 is turned off. When Q5 is turned off, the base current of Q6 does not flow, and Q6 is turned off and the input terminal D5 of the input port 4 goes to the "H" level (+ Vcc).

That is, the relationship between the output terminals D1 to D4 of the output port and the input terminal D5 of the input port 4 in FIG. 2 is as follows.

When the output terminal D2 is at "H", the switch S
3 is on, D5 is at "L" level, when output terminal D3 is at "H", when switch S2 is on, D5 is at "L" level, when output terminal D4 is "H", when switch S1 is on, D5 is on. D5 is at "L" level, and under other conditions, D5 is at "H" level.

As described above, the states of the switches S1 to S3 can be read from the relationship between the state of the output data from the output port and the input data of the input port.

A pulse motor is a functional component for driving a mechanical device. To perform a predetermined operation, a current having a pulse width equal to or more than a predetermined pulse width must be supplied to the exciting coil. Conversely, if the current is less than the required pulse width,
The pulse motor does not rotate.

By utilizing such characteristics of the optional main circuit, the state of S1 to S3 can be read by applying a pulse less than a fixed pulse width to the output terminals D2 to D4 of the output port when the pulse motor is not driven. Can be.
Further, the state of S1 to S3 can be detected even during the driving of the pulse motor. For example, there is a two-phase excitation method in which two coils among a plurality of excitation coils of a pulse motor are always energized, and the rotor is rotated by the sequential energization. Under these conditions, since two coils are always energized, if one control signal line is not used for reading the switch state as shown in FIG. 2, the pulse motor of the pulse motor will be described later. The state of the switches S1 to S3 can be detected during driving.

Next, a method of detecting the states of the switches S1 to S3 will be described with reference to a timing chart of FIG. In FIG. 3, T0 is the non-driving time of the pulse motor, and T1 is the driving time of the pulse motor. T4 when the pulse motor is not driven
If the input terminal D5 goes to "L" level when the output terminal D4 goes to "H" level at 2 (t51), this indicates that the switch S1 is on. t
At 32, when the output terminal D3 is set to the “H” level, if the input terminal D5 remains at the “H” level, it is understood that the switch S2 is in the off state. t22 (t5
When the output terminal D2 is set to “H” level in 3),
If the input terminal D5 at that time becomes “L” level, this indicates that the switch S3 is in the ON state.
Note that the signal output from each of the above output terminals ends in a time shorter than the pulse width required for driving the pulse motor.

On the other hand, when the pulse motor is driven, t11,
t12, t13, t23, t24, t25, t33, t
During the output of 34, t35, t43, t44, t45, and t46, a state determined according to the states of the switches S1 to S3 appears at the input terminal D5. That is, t54, t58, t
At 512, the state of the switch S1 is confirmed, and t55, t5
At 9, 513, the state of the switch S3 is confirmed. At times t56, t510, and t514, the switches S2 and S
The state of the OR condition of No. 3 is confirmed. Further, t57, t
At 511 and t515, the state of the OR condition of the switches S1 and S3 is confirmed.

As described above, the states of S1 and S3 can be detected at a predetermined timing.
T56, t510, t only under the condition that 3 is in the off state.
Confirmed at 514.

In the example shown in FIG. 2, diodes Di1 to Di3 are provided to prevent a short circuit between control signal lines when a plurality of switches among S1 to S3 are on, but this portion is shown in FIG. It can also be configured as shown in FIG. In FIG. 4, RC21, RC22, and RC23 limit the current flowing through these resistors and switches when the pulse motor is driven. Therefore, any one of S1 to S3
When one or all of them are in the ON state, when the control signal line is pulled to the “L” level, the transistor Q5 is reliably turned on and has a resistance value that does not cause a malfunction to the pulse motor.

In the embodiment, the excitation coil of the pulse motor is taken as an example of the optional main circuit. However, any other circuit that receives a plurality of control signals and performs a predetermined operation can be similarly applied.

[0022]

According to the present invention, there is no need to provide a dedicated output line or a dedicated input line for reading the state of the code generator in the optional device, and a large number of optional devices can be identified with a small number of lines. can do.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the operation of the present invention.

FIG. 2 is a circuit diagram of a data processing device according to an embodiment of the present invention.

FIG. 3 is a diagram showing the timing of each unit.

FIG. 4 is a partial circuit diagram showing another example of the configuration of FIG. 2;

FIG. 5 is a circuit diagram of a conventional data processing device.

FIG. 6 is a circuit diagram of a conventional data processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main device 2 Optional device 6 Control signal line 7 Detection signal line S1-S3 Switch as code generation part

Claims (1)

(57) [Claims] 1. A data processing device comprising: a main unit for performing data processing and outputting a plurality of control signals from an output unit; and an optional device connected to the output unit and operated by the control signal. A code generator for outputting a logical sum of several control signal lines to one detection signal line is provided in an optional device, and a timing signal is sequentially output to the control signal line, and a state of the detection signal line is read. A data processing device, wherein a code detecting means for detecting a code is provided in a main body device.