JP3290639B2 - Reed-Solomon decoding device and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiple error correction Reed-Solomon code decoding device, that is, a Reed-Solomon decoding device, and a control method thereof.

[0002]

2. Description of the Related Art Reed-Solomon codes are widely known as codes capable of correcting multiple errors in information stored in various mass storage devices, transmission information of high-speed communication, and the like. The Reed-Solomon code is a code on a Galois field (Galois field) having the root α as a primitive element when a primitive polynomial is W (z) and a root of W (z) = 0 is α. This is one of the error correction codes. Where α is the Galois field

(Equation 1) And the primitive element of

(Equation 2) Consider a Reed-Solomon code having a code length n = 2 ^m −1 and having According to this code, m bits are one processing unit, that is, one symbol. The amount of original information is n-2t symbols. In the following description, it is assumed that m = 8 and one symbol is represented by 8 bits, that is, 1 byte. The received word of one packet is composed of n symbols. When t = 8, error correction of 8 symbols is possible.

[0003] A decoding method of a Reed-Solomon code is generally performed in the order of syndrome calculation, calculation of an error evaluation polynomial and an error position polynomial, calculation of an error position and error magnitude, and error correction. Details of these decoding methods are disclosed in JP-A-10-135846.

[0004]

Generally, error correction using Reed-Solomon codes has a very high correction capability. In addition, not only the Reed-Solomon code alone, but also the correction processing is realized in combination with the convolutional code and the interleave processing, and the Reed-Solomon code itself is double-processed as a product code. No error free state. However, if the state of the transmission path is so bad that it exceeds the error correction capability due to some factor, there is a possibility that no error correction is performed at all in the ordinary Reed-Solomon decoding process, or erroneous correction is performed.

Conventionally, in the Reed-Solomon decoding process, the maximum value of the number of error corrections is determined for the expected worst-case transmission path, so that an error-free state can usually be realized. However, when the number of error corrections exceeds the maximum value and error correction becomes impossible, in the conventional Reed-Solomon decoding process, only the fact that correction is impossible is reported by a flag. Flags that signal uncorrectable are usually
It is sent to a monitoring device that monitors an error correction error, which is different from the LSI including the device that performs the Reed-Solomon decoding process. However, the monitoring device is used only for a test at the time of manufacturing an LSI, and there is a problem that when performing Reed-Solomon decoding processing in an actual system, there is no means for monitoring an error of an error correction.

Therefore, even if a state exceeding the error correction capability frequently occurs, the processing corresponding to the state is not performed at all in an actual LSI that performs the Reed-Solomon decoding processing.
Furthermore, there is a problem that there is no index at which the LSI knows whether the error correction is performed, and if so, how much error correction is correctly performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a Reed-Solomon decoding device having means for monitoring the occurrence of an error exceeding the error correction capability and the degree of error correction. It is an object to provide a control method and a storage medium storing a program for performing the control.

[0008]

In order to achieve the above object, a Reed-Solomon decoding device according to the present invention provides a Reed-Solomon decoder for performing error correction of input data using a Reed-Solomon code, and an error correction using a Reed-Solomon decoder. And a correction state monitor that monitors the degree of error in the input data.The Reed-Solomon decoder uses a syndrome calculator that calculates a syndrome from the input data, An Euclidean algorithm for calculating an error location polynomial and an error evaluation polynomial; an error location calculator for calculating an error location indicating an error byte of input data from the error location polynomial and the error evaluation polynomial; Of the bits that make up the wrong byte By using the Is can, and a error corrector for correcting the input data, the size of the error, by either of the Euclidean mutual division calculator or the error position calculator, by using the error location polynomial and the error evaluator polynomial The corrected state monitor monitors the Euclidean algorithm and the error location calculator to determine the Euclidean algorithm.
Euclidean processing error flag output from the calculator and
Chien search error flag output from error location calculator
Received an uncorrectable indication signal which is a logical sum signal with
An error-free suggestion signal indicating the presence or absence of a Reed-Solomon decoding processing error is generated from the uncorrectable suggestion signal, and a bit error rate or a symbol is determined based on an error position and an error magnitude.
The error rate or the total number of bits of input data and the error bit
Or the total number of symbols in the input data and the error
A signal indicating the degree of error in the input data including the number of symbols is generated.

The correction state monitor includes an error bit number counter for counting the number of erroneous bits indicated by the magnitude of the error, and a synchronization counter for counting a synchronization byte suggestion signal output in synchronization with the synchronization signal of the input data. A signal indicating the degree of error in the input data, while the synchronization signal counter counts a predetermined number of synchronization byte indication signals, the total number of bits of data input to the Reed-Solomon decoding device, and It can include the number of error bits counted by the bit number counter.

The correction status monitor includes an error bit number counter for counting the number of erroneous bits indicated by the magnitude of the error, and a synchronization bit count signal for counting a synchronization byte indication signal output in synchronization with the synchronization signal of the input data. A signal counter;
While the synchronization signal counter counts a predetermined number of synchronization byte suggestion signals, a bit error rate is calculated from the total number of bits of data input to the Reed-Solomon decoding device and the number of erroneous bits counted by the error bit number counter. A bit error rate calculator, and the signal indicating the degree of error in the input data may include a bit error rate.

A bit error rate calculator for dividing the number of error bits by the total number of bits of the input data;
Can be provided. Also, the bit error rate calculator is
While the total number of bits of data input to the Reed-Solomon decoding device is calculated in advance while the predetermined number of synchronization byte suggestion signals are counted, when the synchronization signal counter counts the predetermined number of synchronization byte suggestion signals, A constant output device for outputting the total number of calculated bits.

In the bit error rate calculator, a plurality of ranges of values that the number of error bits can take are set in advance, and the error bit number counter counts while counting the predetermined number of synchronization byte indication signals. The bit error rate is determined from a determiner that determines to which range the number of bits belongs, a value arbitrarily selected from each of the ranges set in the determiner, and the total number of bits of the input data. An error rate output unit that calculates in advance and outputs a bit error rate corresponding to a range determined by the determiner from among the bit error rates calculated in advance can be provided.

Further, the correction state monitor includes an error symbol number counter for counting the number of erroneous bytes indicated by the error position, and a signal indicating the degree of error in the input data is generated when the synchronization signal counter indicates a predetermined number of synchronization bytes. While counting the signal, it may include the total number of data symbols input to the Reed-Solomon decoding device and the number of erroneous symbols counted by the error symbol number counter.

The correction state monitor includes an error symbol number counter for counting the number of erroneous bytes indicated by the error position, and a counter for counting a predetermined number of synchronization byte indication signals output in synchronization with the synchronization signal of the input data. The total number of data symbols input to the Reed-Solomon decoding device, and
A symbol error rate calculator that calculates a symbol error rate from the number of erroneous symbols counted by the error symbol number counter, wherein the signal indicating the degree of error in the input data can include the symbol error rate.

Further, the symbol error rate calculator can include a divider for dividing the number of error symbols by the total number of symbols of the input data. Further, the symbol error rate calculator previously calculates the total number of data symbols input to the Reed-Solomon decoding device while the predetermined number of synchronization byte indication signals are counted, and sets the synchronization signal counter to the predetermined number. And a constant output unit that outputs the total number of symbols calculated in advance when the synchronization byte suggestion signal is counted.

In the symbol error rate calculator, a plurality of ranges of values that the number of erroneous symbols can take are set in advance, and the number of erroneous symbols counted by the erroneous symbol counter while counting a predetermined number of synchronization byte suggestion signals is determined. A symbol error rate is calculated in advance from a determiner that determines which range is set, a value arbitrarily selected from each of the ranges set in the determiner, and the total number of symbols of the input data. And an error rate output unit that outputs a symbol error rate corresponding to a range determined by the determiner from among symbol error rates calculated in advance.

In order to achieve the above object, a control method of a Reed-Solomon decoding device for performing error correction of input data by using a Reed-Solomon code according to the present invention uses a syndrome calculating step of calculating a syndrome from the input data, and using the syndrome. An Euclidean mutual calculation step of calculating an error position polynomial and an error evaluation polynomial; an error position calculation step of calculating an error position indicating an error byte of input data from the error position polynomial and the error evaluation polynomial; Using an error evaluation polynomial, an error magnitude calculation step of calculating an error magnitude indicating which bit is erroneous among bits constituting an erroneous byte indicated by the error location; and an error correcting step of correcting the input data using the magnitude, Raw in Kuriddo mutual division calculation step
Euclidean processing error flag and error location calculation
Logic with Chien search error flag generated in step
Uncorrectable in response to uncorrectable indication signal that is a sum signal
An error-free indication signal indicating the presence or absence of a Reed-Solomon decoding processing error is generated from the indication signal, and the bit error rate or the symbol error rate,
Or the total number of input data bits and the number of error bits
Or the total number of symbols and error symbols in the input data.
And a correction state monitoring step of generating a signal indicating the degree of error in the input data.

The correction state monitoring step counts the number of erroneous bits indicated by the magnitude of the error, and counts a synchronization byte suggestion signal output in synchronization with the synchronization signal of the input data. While counting a predetermined number of synchronization byte suggestion signals by the synchronization signal counting step and the synchronization signal counting step,
A bit error rate calculation step of calculating a bit error rate from the total number of bits of the data input to the Reed-Solomon decoding device and the number of erroneous bits counted in the error bit number counting step; and The signal indicating the degree may include a bit error rate.

The bit error rate calculating step sets a plurality of ranges of possible values of the number of error bits in advance, and counts the number of error bits counted by the error bit number counting step while counting a predetermined number of synchronization byte indication signals. A determination step of determining which range the number belongs to, and a value arbitrarily selected from each of the ranges set in the determiner, and a bit error rate in advance from the total number of bits of the input data. An error rate output step of outputting a bit error rate corresponding to the determined range from among the bit error rates calculated in advance when the range is determined by the calculation and the determination step.

The correction state monitoring step counts the number of erroneous bytes indicated by the error position, and counts a predetermined number of synchronization byte indication signals output in synchronization with the synchronization signal of the input data. A symbol error rate calculation step of calculating a symbol error rate from the total number of data symbols input to the Reed-Solomon decoding device and the number of erroneous symbols counted by the error symbol number counting step. May include the symbol error rate.

In the symbol error rate calculating step, a plurality of ranges of possible values of the number of erroneous symbols are set in advance, and the number of errors counted by the erroneous symbol number counting step while counting the predetermined number of synchronization byte suggestion signals is set. A symbol error rate is determined from a determining step of determining which range the number of symbols belongs to, and a value arbitrarily selected from each of the ranges set in the determining step, and the total number of symbols of the input data. And an error rate output step of outputting a symbol error rate corresponding to the determined range from the symbol error rates calculated in advance when the range is determined by the determiner in advance.

In order to achieve the above object, a computer readable storage medium for storing a program according to the present invention stores a code of a program for controlling a Reed-Solomon decoding device for performing error correction of input data using a Reed-Solomon code. A computer-readable storage medium, wherein the program code includes a code of a syndrome calculation step of calculating a syndrome from input data, and a code of a Euclidean mutual calculation step of calculating an error location polynomial and an error evaluation polynomial using the syndrome. The code of the error position calculating step for calculating the error position indicating the erroneous byte of the input data from the error position polynomial and the error evaluation polynomial, and which of the bits constituting the erroneous byte indicated by the error position are erroneous Large error that indicates And code error correction step of correcting the code size calculation step of error, the input data using the magnitude of the error locations and error to calculate the of Yoo
-Euclidean generated in the computation step
Generated in the processing error flag and error position calculation step
Uncorrectable which is the logical sum signal with the chain search error flag
In response to the suggestion signal, read solo from the uncorrectable suggestion signal
Generates an error-free suggestion signal indicating the presence or absence of an error in the Mon decoding process , and determines the bit error based on the error location and error magnitude.
Rate or symbol error rate, or the total
Number of bits and error bits or the total
And a code for a correction state monitoring step for generating a signal indicating the degree of error in the input data, including the number of volts and the number of error symbols .

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a Reed-Solomon decoding device according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a Reed-Solomon decoding device 100 according to the present embodiment. Reed-Solomon decoding device 1 according to the present embodiment
Reference numeral 00 denotes a Reed-Solomon decoder 1 for performing error correction on input data, and a correction status monitor 2 for detecting an error correction processing error by the Reed-Solomon decoder 1 and monitoring the degree of error in the input data. And

The Reed-Solomon decoder 1 further calculates a syndrome calculator 3 for calculating the syndrome of the input data, calculates an error location polynomial and an error evaluation polynomial from the syndrome, and further calculates an error based on the result of the Chien searcher 5. Euclidean mutual calculator 4 for calculating the size of the error, an error location polynomial and an error evaluation polynomial, a Chien searcher 5 for calculating an error location, a differential value of the error location, and an error evaluation value, and data indicated by the error location data , An error corrector 6 that corrects the error based on the error position and the magnitude of the error, a data delay RAM 7 that holds input data for a predetermined time, and an error output from the Euclidean algorithm 4 and the Chien searcher 5. O which is obtained by ORing the indicated error flags
An R circuit 25 is provided.

In the present embodiment, the Chien searcher 5 has a function as an error position calculator for calculating an error position indicating an erroneous byte of the input data, and the Euclidean mutual aid calculator 4 determines that the error position is It has a function as an error magnitude calculator that calculates the magnitude of an error indicating which bit is erroneous among the bits constituting the erroneous byte. It should be noted that the function as the error magnitude calculator may be performed by a Chen searcher instead of the Euclidean mutual aid calculator. The correction state monitor 40 generates a signal indicating the presence or absence of a processing error in the Euclidean mutual calculator 4 and the Chien searcher 5, that is, an error-free suggestion signal and a signal indicating the degree of error in the input data.

Hereinafter, according to the order of the error correction processing,
The operation of each configuration will be described. The input data sent from the transmission line 8-1 is input to the syndrome calculator 3 in the Reed-Solomon decoder 1, and is also taken into the data delay RAM 7 via the signal line 8-2. For a long time. The syndrome calculator 3 calculates the syndrome from the input data, and sends the calculated syndrome to the Euclidean algorithm calculator 4 via the signal line 9. In addition, the syndrome calculator 3 determines whether or not there is an error in the input data, and if it determines that there is no error, sends the activated error-free state suggestion signal to the error corrector 6 via the signal line 10.

The Euclidean algorithm 4 calculates an error locator polynomial and an error evaluation polynomial from the syndrome,
The calculated error locator polynomial and error evaluation polynomial are sent to the Chien searcher 5 via the signal line 11. When detecting a processing error at the time of calculating the error locator polynomial and the error evaluation polynomial, the Euclidean mutual calculator 4 outputs the activated Euclidean processing error flag to the OR circuit 25 via the signal line 13.

The Chien searcher 5 calculates the error position of the input data from the data of the error locator polynomial and the error evaluation polynomial received from the Euclidean mutual calculator 4, and outputs the error rectifier 6 via the signal line 15-1. Then, the calculated error position data is sent to the correction state monitor 2 via the signal line 15-2, and the differential value and error evaluation value of the error position are calculated, and the Euclidean mutual error is calculated via the signal line 14. Send it to Calculator 4. When detecting a processing error when performing the above data calculation, the Chien searcher 5 sends the activated Chien search error flag to the OR circuit 2 via the signal line 16.
5 is output.

After calculating the above-mentioned error locator polynomial and error evaluation polynomial, the Euclidean algorithm calculator 4 receives the differential value and error evaluation value of the error location calculated by the Chien searcher 5 and determines the magnitude of the error. Calculate the signal line 12
The calculated error magnitude is output to the error corrector 6 via -1 and to the correction status monitor 2 via the signal line 12-2.

The error corrector 6 determines whether the error-free state indication signal sent from the syndrome calculator 3 is not active, that is, if there is an error in the input data,
The input data sent from the data delay RAM 7 via the signal line 8-3 is converted based on the error position detected by the Chien searcher 5 and the magnitude of the error calculated by the Euclidean algorithm calculator 3. Correct to the correct data. The correct data corrected in this way is output to any device connected to the Reed-Solomon decoding device 100 via the signal line 18. The correction state monitor 2 performs the following processing in order to output a signal for determining whether or not the above-described series of correction processing is correctly performed.

FIG. 2 is a flowchart for explaining an example of the operation of the correction status monitor 2. First, the correction state monitor 2 counts the number of error symbols and the number of error bits, respectively (step S1). On the other hand, the correction state monitor 2
Counts a synchronization byte suggestion signal that becomes active when a synchronization signal of input data is detected, and when the count value reaches a predetermined value (YES in step S2), an error-free suggestion signal and an error of the input data are detected. A signal indicating the degree is generated (step S3). In the present embodiment, the number of error symbols,
The number of error bits, the total number of input data symbols, and the total number of input data bits are output to any device. It is checked whether or not input data still exists (step S4). If there is data, the count value is initialized (step S5), and the process returns to step S1.

Step S1 will be described in more detail. The error correction state monitor 2 receives the data of the error position output from the Chien searcher 5, counts the number of error position data, and calculates the number of error symbols. For example,
Assume that the input data forms one packet with n bytes. The calculated error position is data indicating which position (byte) of the input data can be presumed to have an error. Therefore, actually, the calculated error position indicates the first to n-th positions.
To n. Since there is data at an error position for each erroneous byte in the packet, counting the number of error position data makes it possible to calculate the number of error bytes in the packet, that is, the number of error symbols. The calculated number of error symbols is output to an arbitrary device connected to Reed-Solomon decoding device 100 via signal line 21.

The correction state monitor 2 receives the data of the magnitude of the error output from the Euclidean algorithm calculator 4 and calculates the number of error bits. The error magnitude data is data that specifies which bit of the byte at the position indicated by the error position data is erroneous. For example, if one byte, that is, one symbol is composed of 8-bit data, the error magnitude data is also 8-bit data, and each of the first to eighth bits in one byte of the error magnitude data. Corresponds to the first to eighth bits in one symbol of the input data. The bits of the error magnitude data are as follows if there is no error in the corresponding bits in the input data.
For example, it becomes "0", and if there is an error, it becomes "1". For example, if the error position data is “33” in decimal and the error magnitude data is “55” in hexadecimal, there is an error in the 33rd symbol, and the 8-bit data of the 33rd symbol is , Means that the first, third, fifth, and seventh four bits from the right are incorrect (that is, the error magnitude data is represented as 01010101 in binary). Therefore, in the above example, the number of error bits can be calculated by counting "1" in the error magnitude data. The calculated number of error bits is output to an arbitrary device connected to the Reed-Solomon decoding device 100 via the signal line 22.

The correction state monitor 2 counts the number of erroneous symbols and the number of erroneous bits as described above, and outputs the obtained result. On the other hand, the synchronization state monitor 2 becomes active when a synchronization signal of input data is detected. The byte suggestion signal is received from the signal line 19, and the synchronization byte suggestion signal is counted. The synchronization signal is embedded at the beginning of a packet constituting input data. Before input data is input to the Reed-Solomon decoding device 100, a synchronization circuit (not shown) detects a synchronization signal and outputs an activated synchronization byte indication signal to the correction state monitor 2.

Step S2 will be described in more detail. The correction state monitor 2 includes a Reed-Solomon decoding device 10.
Although all the series of data input to 0 may be monitored collectively, usually, the series of input data is monitored separately for each predetermined amount of data, that is, for each predetermined number of packets. this is,
In particular, when the data amount of a series of input data is large, if the error of the input data exceeds the correction capability, the LSI is more efficient to deal with every predetermined number of packets than to deal with all the input data. Because it is a target. Therefore, the number of packets monitored by the correction state monitor 2 collectively, that is, the number of synchronization byte suggestion signals to be counted is set in advance, and the synchronization byte suggestion signal is counted up to the set value, and then the process proceeds to step S3.

Step S3 will be described in more detail. Since the number of bytes and the number of bits of one packet are determined, the number of packets can be determined by counting the synchronization byte indication signal, and the number of bytes and the number of bits of the input data can be calculated. Therefore, when the correction state monitor 2 counts the set number of synchronization byte suggestion signals, the number of bytes (symbols) and the number of bits of data included in the counted number of packets, that is, the Reed-Solomon decoding device 100 The total number of input data symbols input,
And the total number of input data bits are calculated.
4 to any device.

On the other hand, when the correction processing is not performed normally in the Reed-Solomon decoder 1, an error flag indicating that the processing was not performed normally, for example, an Euclidean processing error flag output from the Euclidean algorithm calculator 4,
The chain search error flag output from the chain searcher 5 becomes active, and the active flag is sent to the OR circuit 25. The OR circuit 25 ORs the input error flags to activate the uncorrectable suggestion signal, and sends the activated uncorrectable suggestion signal to the correction state monitor 2 via the signal line 17. . When the uncorrectable suggestion signal is active, the correction state monitor 2 outputs the error-free suggestion signal without activating it in order to indicate that the error correction processing is not correctly performed in the Reed-Solomon decoder 1.
Conversely, if the uncorrectable suggestion signal is not active, the activated error-free suggestion signal is transmitted from the signal line 20 to the Reed-Solomon decoder in order to indicate that the error correction processing has been correctly performed by the Reed-Solomon decoder 1. Output to any device connected to device 100.

As described above, the correction status monitor 2
Calculates the total number of input bytes (symbols) and the total number of input bits, the number of error symbols corrected by the Reed-Solomon decoder 1, and the number of error bits for each data of a preset number of packets. Output to any device.
Further, the uncorrectable suggestion signal is checked to confirm whether or not the corrective processing has been correctly performed by the Reed-Solomon decoder 1. If the corrective processing is normal, an error-free suggestive signal is output. Therefore, whether the total number of input data symbols, the number of bits, the number of error symbols, and the number of bits calculated by the correction state monitor 2 are valid data calculated when the Reed-Solomon decoder 1 correctly performs correction processing,
Alternatively, the error-free suggestion signal indicates whether the data is invalid data calculated when the data becomes uncorrectable.

Next, a detailed configuration of the correction state monitor 2 will be described. FIG. 3 is a block diagram showing the configuration of the correction status monitor 2. The correction state monitor 2 includes an error symbol number counter 30, an error bit number counter 31, and a synchronization signal counter 32.

The error symbol number counter 30 counts the number of error position data detected by the Chien searcher 5, that is, the number of error symbols, in order to calculate the number of error symbols. Line 33
Is output to the synchronization signal counter 32 via.

As described above, if the input data has a code length n, one packet has an n-byte structure, and the error position data is a number indicating the position of the byte containing the error, that is, from the first to the first. It is any number from 1 to n indicating the nth position. Error symbol counter 3
0 counts the number of error position data and calculates the number of erroneous bytes, that is, the number of error symbols.

The error bit number counter 31 receives the data indicating the error size calculated by the Euclidean algorithm calculator 4 in order to calculate the error bit number, and sets “1” in the error size data. The number of error bits is counted, and the number of error bits is output to the synchronization signal counter 32 via the signal line 34.

As described above, if the input data is, for example, one byte, that is, one symbol is composed of 8-bit data, the data of the error size is 8 bits.
The first bit in one byte of error magnitude data is bit data.
To the eighth bit are “0” if there is no error in the corresponding input data bit, and are “1” if there is an error. Therefore, the number of error bits can be calculated by counting "1" in the error magnitude data.

The synchronization signal counter 32 has roughly three functions. First, as a first function, as described above, the synchronization signal counter 32 counts the synchronization byte suggestion signal, and calculates the number of bytes and the number of bits of input data. As a second function, as described above, when the uncorrectable indication signal output from the Reed-Solomon decoder 1 is active, the synchronization signal counter 32 indicates that the Reed-Solomon decoder 1 cannot correct, as described above. Outputs the error-free suggestion signal without activating it. Conversely, if the uncorrectable suggestion signal is not active, the activated error-free suggestion signal is output.

As a third function, the synchronization signal counter 32
After counting the synchronization byte suggestion signal of the set value, the counter receives and outputs the number of error symbols output from the error symbol number counter 30 and the number of error bits output from the error bit number counter 31. Further, in synchronization with the output of the number of error symbols and the output of the number of error bits,
The error-free suggestion signal is activated or deactivated based on the uncorrectable suggestion signal, and an error-free suggestion signal is output from the signal line 20.

The total number of input data symbols and the number of bits are
It is output in synchronization with the output of the number of error symbols and the number of error bits. It should be noted that the number of data packets that are collectively monitored by the correction state monitor 2 is set in advance.
The total number of input data symbols and the number of bits are constant unless the number of packets to be monitored collectively is changed. Therefore, if the total number of input data symbols and the number of bits are calculated in advance in the synchronization signal counter 32, the total number of inputs does not have to be calculated every time the set number of synchronization byte indication signals is counted. .

The error-free suggestion signal, the number of error symbols, the number of error bits, the total number of input data symbols, and the total number of input data bits output from the synchronization signal counter 32 described above are effectively used by the Reed-Solomon decoder 1. Since it serves as an index for determining whether it is functioning, the accuracy of error correction can be improved by using the above signals.

For example, if the data when the error-free suggestion signal becomes inactive can be corrected again by the Reed-Solomon decoding device 100, errors in the input data can be eliminated or reduced. Also, if any device calculates the symbol error rate by dividing the number of error symbols by the total number of input data symbols, and calculates the bit error rate by dividing the number of error bits by the total number of input data bits,
The error frequency of input data can be known. Furthermore, if the calculated symbol error rate and bit error rate data can be corrected again by the Reed-Solomon decoding device 100, errors in the input data can be eliminated or reduced.

In this embodiment, the number of error symbols,
Although the number of error bits, the total number of input data symbols, and the total number of input data bits are output from the correction state monitor 2, the number of error bits and the total input data It is sufficient if at least the number of bits can be output.

As described above, according to the present embodiment, during the Reed-Solomon decoding process, the occurrence of a processing error in the Reed-Solomon decoding process and the number of bits and the number of symbols for error correction of input data are constantly monitored. , A signal serving as an index for determining whether the Reed-Solomon decoding unit is functioning effectively can be output. Therefore, the LSI including the Reed-Solomon decoding device 100 may be configured such that, based on the index output from the Reed-Solomon decoding device 100, when the error correction state is poor, for example, when error correction becomes impossible or when error occurs in the input data. In the case where the frequency is high, some measure can be taken to improve the accuracy of error correction. For example, based on various signals output from the correction state monitor 2, it can be determined whether or not it is necessary to perform error correction again.

Embodiment 2 FIG. 4 is a block diagram showing a configuration of Reed-Solomon decoding device 110 according to the second embodiment. 1 are given the same reference numerals. The Reed-Solomon decoding device 110 includes a Reed-Solomon decoder 1 and a correction state monitor 40. The configuration and operation of the Reed-Solomon decoder 1 are the same as in the first embodiment. The correction state monitor 40 signals the symbol error rate instead of the number of error symbols, the number of error bits, the total number of input data symbols, and the total number of input data bits output from the correction state monitor 2 of the first embodiment. The bit error rate is output from a signal line 42 through a line 41.

FIG. 5 is a flowchart for explaining an example of the operation of the correction state monitor 40. First, the correction state monitor 40 counts the number of error symbols and the number of error bits, respectively (step S20). On the other hand, the correction state monitor 40 counts a synchronization byte suggestion signal that becomes active when a synchronization signal of input data is detected, and when the count value reaches a predetermined value (YE in step S21).
S), a symbol error rate and a bit error rate are calculated (step S22).

Next, the correction status monitor 40 outputs the symbol error rate and the bit error rate to an arbitrary device as an error-free suggestion signal and a signal indicating the degree of error in the input data (step S23). It is confirmed whether or not there is input data (step S24). If there is data, the count value is initialized (step S25), and step S20 is performed.
Return to

FIG. 6 is a block diagram showing the configuration of the correction status monitor 40. The correction state monitor 40 includes a synchronization signal counter 50, an error symbol number counter 51, an error bit number counter 52, and an error rate calculator 53.
The error rate calculator 53 has a function as a symbol error rate calculator for calculating a symbol error rate and a function as a bit error rate calculator for calculating a bit error rate.

The error symbol number counter 51 receives the error position data, calculates the error symbol number in the same manner as the error symbol number counter 30 of the first embodiment, and
And outputs the number of erroneous symbols to the error rate calculator 53. The error bit number counter 52 receives the data of the magnitude of the error, and receives the error bit number counter 31 of the first embodiment.
Similarly to the above, the number of error bits is calculated, and the number of error bits is output to the error rate calculator 53 via the signal line 56.

The synchronization signal counter 50 receives an uncorrectable suggestion signal and outputs an error-free suggestion signal as in the case of the synchronization signal counter 32 of the first embodiment, but does not receive the number of error symbols or the number of error bits. When the synchronization signal counter 50 counts a specific number of synchronization byte suggestion signals, the synchronization signal counter 50 outputs the activated specific count value suggestion signal to the error rate calculator 53 via the signal line 54. The specific count value suggestion signal is a signal for indicating a packet interval when the correction state monitor 40 monitors the error correction state of the Reed-Solomon decoder 1 in units of a specific number of packets.
For example, a setting is made so as to output a specific count value suggestion signal every time the maximum count value of the synchronization signal counter 50 is counted. As described above, the synchronization signal counter 50
A specific count value suggestion signal and an error-free suggestion signal indicating a correction state are output.

The error rate calculator 53 includes an error symbol number calculated by the error symbol number counter 51, an error bit number calculated by the error bit number counter 52, and a specific count value suggestion signal output from the synchronization signal counter 50. The symbol error rate and the bit error rate are calculated and output.

As described above, the interval at which the synchronization signal counter 50 outputs the activated specific count value suggestion signal is set in advance. For example, it is assumed that the specific count value suggestion signal becomes active each time the maximum count value of the synchronization signal counter 50 is counted. The total number of input data symbols and the number of bits input to the Reed-Solomon decoder 1 after the output of the active specific count value suggestion signal until the output of the next active suggestion signal is determined by the synchronization signal counter 50. It becomes a constant value corresponding to the maximum count value. In other words, if the output interval of the active specific count value suggestion signal is set, the number of symbols and the number of bits of data input between two outputs of the count value suggestion signal can be calculated. Hereinafter, description will be made on the assumption that the specific count value suggestion signal is output every time the maximum count value of the synchronization signal counter 50 is counted.

The error rate calculator 53 is provided with the synchronization signal counter 5
In synchronization with the timing when 0 activates the specific count value suggestion signal, the ratio of the number of erroneous data symbols and the number of erroneous bits to the total number of input data symbols and bits is calculated, and the symbol error rate and the bit error rate are signaled. Output via lines 41 and 42.

FIG. 7 is a block diagram showing the configuration of the error rate calculator 53. The error rate calculator 53 includes a constant output unit 6
0, a first selector 61, a second selector 62, and a divider 63. In the constant output unit 60, the total number of input data symbols and the number of bits corresponding to the maximum count value are calculated or input in advance. Constant output device 6
0 is calculated in advance when a specific count value suggestion signal is received,
Alternatively, the total number of input data bits input
And the total number of input data symbols from the signal line 67
Each is output to the first selector 61.

As described above, the synchronization signal counter 50
However, since the time interval at which the activated specific count value suggestion signal is output is set in advance, the total time of data input to the Reed-Solomon decoder 1 between the output of the specific count value suggestion signal and the next output is determined. The number of symbols and the total number of bits can be calculated in advance. For example, if the output of the specific count value suggestion signal is performed every time the maximum count value of the synchronization signal counter 50 is counted, the calculated total number of input data symbols and bits is calculated by the synchronization signal counter 5.
It becomes a constant value corresponding to the maximum count value of 0.

The first selector 61 takes in the total number of input data bits and the total number of input data symbols calculated by the constant output unit 60, selects one of them, and outputs it to the divider 63 as selected data. Second selector 62
Captures the number of error symbols and the number of error bits, selects one of them, and outputs the selected data to the divider 63.

First selector 61 and second selector 6
2 indicates whether the first selector 61 selects the total number of input data symbols and the second selector 62 selects the number of error symbols by a control unit (not shown) for controlling the inside of the error rate calculator 53, The first selector 61 is controlled to select either the total number of input data bits, and the second selector 62 is selected to select the number of error bits.

When the divider 63 receives the total number of input data symbols as selection data of the first selector and receives the number of error symbols as selection data of the second selector,
The symbol error rate is calculated by dividing the number of error symbols by the total number of input data symbols, and the symbol error rate is output via the signal line 41. When the divider 63 receives the total number of input data bits as the selection data of the first selector and the error bit number as the selection data of the second selector, the divider 63 divides the error bit number by the total number of input data bits. The bit error rate is calculated by
Output via.

FIG. 8 is a flowchart for explaining an example of the operation of the error rate calculator 53. The constant output unit 60 receives the specific count value suggestion signal (Step S80).
And the total number of input data bits and the total number of input data symbols calculated in advance are output to the first selector 61.
The second selector 62 receives the error symbol number data and the error bit number data (Step S82).

The control unit of the error rate calculator 53 sets the first
When the second selectors 61 and 62 are instructed to select the number of symbols (step S83), the first selector 61 outputs the total number of input data symbols to the divider 63, and the second selector The number of error symbols is output to divider 63 (step S84), and divider 63 calculates a symbol error rate (step S85).

On the other hand, when the control unit of the error rate calculator 53 instructs the first and second selectors 61 and 62 to select the number of bits (step S83), the first selector 61 sets the total number of bits. The number of input data bits is output to the divider 63, the second selector outputs the number of error bits to the divider 63 (Step S86), and the divider 63 calculates a bit error rate (Step S87). Step S82
Is before step S83, the position of step S82 is not limited to the position shown in FIG.

Next, an error rate calculator having another configuration will be described. FIG. 9 is a block diagram showing a configuration of the error rate calculator 90. Note that the error rate calculator 90 is provided in the correction state monitor 40 instead of the error calculator 53 of FIG. Accordingly, a block diagram of the correction state monitor 40 including the error rate calculator 90 is omitted. Error rate calculator 90
Includes a third selector 80, a numerical range determiner 81, and an error rate output unit 82.

The third selector 80 fetches the number of error symbols from the signal line 55 and the number of error bits from the signal line 56, and receives a signal from a control unit (not shown) for controlling the inside of the error rate calculator 90. One of them is selected and output to the numerical range determiner 81 as selected data.

Numeric range determiner 81 receives error symbol number or error bit number data as selection data, receives a specific count value suggestion signal from signal line 54, and synchronizes with the timing at which the specific count value suggestion signal becomes active. Then, the range to which the value of the selected data belongs is determined, and the determined range, that is, the range suggestion data is transmitted to the signal line 86.
To the error rate output unit 82.

A plurality of ranges that can be selected data are input to the numerical range determiner 81 in advance. The numerical range determiner 81 compares the input selection data with each of the ranges input in advance, and determines which numerical range the selection data falls into. A number to be output as range suggestion data is assigned to each range input in advance. When the numerical range determiner 81 determines the range to which the selected data belongs,
The number assigned to the determined range is output as range suggestion data.

For example, the numerical range determiner 81 determines the range that the selected data can take, for example, from 1,000 to 99,9.
It is assumed that 99 ranges obtained by dividing 99 at 1,000 intervals are input, and 1, 2, 3,..., 99 are assigned to each range as range suggestion data in ascending order of numerical values. The numerical range determiner 81 determines that the selection data is 1,000 to
When it is recognized that the range is 1,999, "1" pre-assigned to the range of 1,000 to 1,999 is output as range suggestion data, and when the range is recognized to be 2,000 to 2,999. Outputs “2” as range suggestion data.

The error rate output unit 82 is a numerical range judgment unit 81
Receiving the range suggestion data output from the device and the specific count value suggestion signal transmitted by the signal line 54-2,
The error rate is output in synchronization with the timing when the specific count value suggestion signal becomes active.

As described above, the synchronization signal counter 50
However, since the interval for outputting the activated specific count value suggestion signal is set in advance, the total number of symbols of the data input to the Reed-Solomon decoder 1 between the output of the specific count value suggestion signal and the next output The number and the total number of bits are constant. For example, when the output of the specific count value suggestion signal is performed every time the maximum count value of the synchronization signal counter 50 is counted, the calculated total number of input data symbols and bits is calculated as the maximum count value of the synchronization signal counter 50. It will be the corresponding constant value. Therefore, the total number of input data symbols and the number of bits are calculated in advance by the error rate output unit 82.

The error rate output unit 82 preliminarily selects one numerical value within the range indicated by the range suggestion data as an approximate value, and treats the selected approximate value as the value of the number of error symbols and the number of error bits. To explain using the above example, if the error rate output unit 82 sets an intermediate value in the range as an approximate value, the number of error symbols or the number of error bits is uniform when the range suggestion data is “1”. And the intermediate value "1,500"
Becomes

As described above, the total number of input data symbols and the number of bits are fixed values. Further, since the approximate number of error symbols and the number of bits are set to one for each of the range suggestion data, the possible values of the number of error symbols and the number of bits are limited. Therefore, the error rate is calculated for each of the approximate values of the number of error symbols and the number of bits, and the error rate calculated in advance is selected and output according to the range suggestion data.

FIG. 10 is a flowchart for explaining the operation of the error rate calculator 90. The third selector 80 receives the number of error symbols and the number of error bits (step S9).
0), the number of symbols or the number of bits is selected according to an instruction from a control unit that controls the inside of the error rate calculator 90 (step S).
91).

When the number of symbols is selected, the numerical range determiner 81 determines the range to which the value of the number of erroneous symbols belongs in synchronization with the timing when the specific count value suggestion signal becomes active, and determines the determined range, that is, the range. The suggestion data is output to the error rate output device 82 (step S92).

The error rate output unit 82 synchronizes with the timing when the specific count value suggestion signal becomes active, and the numerical range determinator 81 actually selects the symbol error rate from the symbol error rates previously calculated for each range suggestion data. A symbol error rate corresponding to the output range suggestion data is selected and output (step S93).

On the other hand, when the number of bits is selected, the numerical range determiner 81 determines the range to which the value of the number of erroneous bits belongs in synchronization with the timing when the specific count value suggestion signal becomes active, and That is, the range suggestion data is output to the error rate output unit 82 (step S95).

The error rate output unit 82 synchronizes with the timing at which the specific count value suggestion signal becomes active, and the numerical range determiner 81 actually calculates the bit error rate from the bit error rates calculated for each range suggestion data. The bit error rate corresponding to the output range suggestion data is selected and output (step S96).

As described above, in the second embodiment, the symbol error rate and the bit error rate can be obtained in the correction state monitor 40. Further, if the error rate calculator 90 is used, an approximate value of the error rate can be output in accordance with the range suggestion data without performing division each time the range suggestion data is received. Is not necessary, or when the configuration of the correction status monitor 40 is to be simplified.

In the second embodiment, the symbol error rate and the bit error rate are output from the correction state monitor 40. However, the system in which the Reed-Solomon decoding device 110 according to the second embodiment is mounted has It suffices if at least one of the error rate and the symbol error rate can be output. For example,
When only one of the bit error rate and the symbol error rate is output, in the example of the correction state monitor 40 using the error rate calculator 53, the first and second selectors 61 and 62 are deleted and the error rate calculator In the example of the correction status monitor using 90, the third selector 80 may be deleted. It is also possible to adopt a configuration in which the bit error rate is always output and the symbol error rate can be output as needed.

Further, some or all of the functions described in the first and second embodiments can be realized by software program codes recorded on a computer-readable storage medium. Therefore, a storage medium on which the program code capable of realizing the functions of the above-described embodiments is recorded constitutes the present invention.

[0085]

As described above, the Reed-Solomon decoding apparatus according to the present invention detects a Reed-Solomon decoder that performs error correction of input data by using a Reed-Solomon code, detects an error correction processing error by the Reed-Solomon decoder, and outputs the input data. A Reed-Solomon decoder that calculates a syndrome from input data, and a Euclidean that calculates an error position polynomial and an error evaluation polynomial using the syndrome. An mutual error calculator, an error position calculator that calculates an error position indicating an erroneous byte of the input data from the error position polynomial and the error evaluation polynomial, and of the bits that constitute the erroneous byte indicated by the error position and the error position, Using the magnitude of the error to indicate which bit is incorrect,
And a error corrector for correcting the input data, the size of the error, by either of the Euclidean mutual division calculator or the error position calculator is calculated by using the error location polynomial and the error evaluator polynomial, the Euclidean mutual division computation vessel
Processing error flags and error positions output from
On the Chien search error flag output from the location calculator
In response to an uncorrectable indication signal that is a logical sum signal,
An error-free suggestion signal indicating the presence or absence of a Reed-Solomon decoding processing error is generated from the function suggestion signal , and the bit error rate or the symbol error is determined based on the error location and error magnitude.
Rate or total number of bits of input data and error bits
Number or total number of symbols of input data and error symbol
And generating a signal indicating the degree of error in the input data including the number of files.

Further, according to the control method of the Reed-Solomon decoding device for performing error correction of input data by using a Reed-Solomon code according to the present invention, a syndrome calculation step of calculating a syndrome from input data, and an error locator polynomial by using the syndrome An Euclidean mutual calculation step for calculating an error evaluation polynomial; an error position calculation step for calculating an error position indicating an error byte of input data from the error position polynomial and the error evaluation polynomial; and an error position polynomial and an error evaluation polynomial. An error magnitude calculating step of calculating an error magnitude indicating which bit is erroneous among bits constituting an erroneous byte indicated by the error location, and inputting using the error location and the error magnitude. and the error correction step to correct the data, user
Euclidean process generated in the algorithm
Error flag and the error
Uncorrectable indication that is a logical sum signal with the search error flag
In response to the solicitation signal, lead solo from the uncorrectable suggestion signal
Generates an error-free suggestion signal indicating the presence or absence of an error in the Mon decoding process , and determines the bit error based on the error location and error magnitude.
Rate or symbol error rate, or the total
Number of bits and error bits or the total
A correction state monitoring step of generating a signal indicating the degree of error in the input data, including the number of volts and the number of error symbols ,
Is provided.

The computer-readable storage medium for storing the program according to the present invention is a computer-readable storage medium for storing a code of a program for controlling a Reed-Solomon decoding device for performing error correction of input data by using a Reed-Solomon code. And the program code is
The code of the syndrome calculation step of calculating the syndrome from the input data, the code of the Euclidean mutual division calculation step of calculating the error location polynomial and the error evaluation polynomial using the syndrome, and the error of the input data from the error location polynomial and the error evaluation polynomial Error position calculation step code for calculating an error position indicating a byte that is present, and an error size for calculating an error size indicating which bit among the bits constituting the erroneous byte indicated by the error position is erroneous A code of a calculation step, a code of an error correction step for correcting input data using an error position and an error size, and a Euclidean mutual calculation step
Error flags and error locations generated by Euclidean
With the Chien search error flag generated in the calculation step
Receiving an uncorrectable indication signal, which is a logical sum signal,
An error-free indication signal indicating the presence or absence of a Reed-Solomon decoding processing error is generated from the impossibility indication signal, and a bit error rate or a symbol error is determined based on the error position and error magnitude.
Rate or total number of bits of input data and error bits
Number or total number of symbols of input data and error symbol
And a code for a correction state monitoring step for generating a signal indicating the degree of error in the input data , including a number of errors.

Therefore, whether the Reed-Solomon decoder is functioning effectively can be monitored during the operation of the Reed-Solomon decoder, and an index indicating the operating state of the Reed-Solomon decoder can be output. Therefore, the LSI including the device for performing the Reed-Solomon decoding process can take some measures when the Reed-Solomon decoder does not function effectively.

Further, since the processing error of the Reed-Solomon decoder and the number of error symbols and the number of bits of input data are constantly monitored, if the error correction state is poor, for example, if error correction becomes impossible or input When the frequency of occurrence of data errors is high, if the error correction is performed again, the accuracy of the error correction can be improved.

Further, at least one of the symbol error rate and the bit error rate may be obtained by the correction state monitor. At this time, if it is not necessary to calculate the correct symbol error rate and bit error rate, or if it is desired to simplify the configuration of the correction state monitor, prepare a plurality of possible values of the symbol error rate and the bit error rate. Then, the closest value may be output as an approximate value.

[Brief description of the drawings]

FIG. 1 is a Reed-Solomon decoding device 1 according to a first embodiment.
FIG. 2 is a block diagram showing a configuration of a 00.

FIG. 2 is a flowchart illustrating an example of an operation of a correction state monitor 2.

FIG. 3 is a block diagram showing a configuration of a correction state monitor 2;

FIG. 4 is a Reed-Solomon decoding device 1 according to a second embodiment.
It is a block diagram which shows the structure of 10.

FIG. 5 is a flowchart illustrating an example of the operation of the correction state monitor 40.

FIG. 6 is a block diagram showing a configuration of a correction status monitor 40.

FIG. 7 is a block diagram showing a configuration of an error rate calculator 53.

FIG. 8 is a flowchart illustrating an example of the operation of the error rate calculator 53.

FIG. 9 is a block diagram showing a configuration of an error rate calculator 90.

FIG. 10 is a flowchart illustrating an operation of the error rate calculator 90.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reed-Solomon decoder 2 Correction state monitor 3 Syndrome calculator 4 Euclidean mutual division calculator 5 Chien searcher 6 Error corrector 7 Data delay RAM 30 Error symbol number counter 31 Error bit number counter 32 Synchronization signal counter 40 Correction state monitor Reference Signs List 50 synchronization signal counter 51 error symbol counter 52 error bit counter 53 error rate calculator 60 constant output device 61 first selector 62 second selector 63 divider 80 third selector 81 numerical range determiner 82 error rate output 100,110 Reed-Solomon decoding device

Claims (17)

(57) [Claims] 1. A Reed-Solomon decoder for performing error correction of input data using a Reed-Solomon code, and a correction state for detecting an error correction processing error by the Reed-Solomon decoder and monitoring the degree of error in the input data. A Reed-Solomon decoder, comprising: a syndrome calculator that calculates a syndrome from the input data; a Euclidean algorithm that calculates an error locator polynomial and an error evaluation polynomial using the syndrome; An error position calculator that calculates an error position indicating an erroneous byte of the input data from an error locator polynomial and an error evaluation polynomial; and which of the bits constituting the erroneous byte indicated by the error position and the error position Error correction that corrects the input data using the magnitude of the error that indicates Comprising a vessel, the magnitude of the error, by any of the above Euclidean algorithm calculator or the error position calculator is calculated by using the error location polynomial and the error evaluation polynomial, the correction state monitor instrument , The Euclidean algorithm above,
And monitors the error position calculator, the Euclidean
Euclidean processing error flag output from mutual algorithm calculator
Search error output from the error location calculator
Received an uncorrectable indication signal which is a logical sum signal with the flag.
Te, generates an error free suggestion signal indicating the presence or absence of a Reed-Solomon decoding error from the uncorrectable suggestion signals, the position and size of the error of the error, bit error Ritsuwaka
Or symbol error rate or total bits of input data
Number and number of error bits or total symbols of input data
A Reed-Solomon decoding device that generates a signal indicating the degree of error in the input data, including a number and a number of error symbols . 2. The Reed-Solomon decoding device according to claim 1, wherein the correction state monitor includes an error bit number counter that counts the number of erroneous bits indicated by the magnitude of the error, and a synchronization signal of the input data. A synchronization signal counter that counts a synchronization byte suggestion signal that is output in accordance with the signal. The signal indicating the degree of error in the input data is output while the synchronization signal counter counts a predetermined number of the synchronization byte suggestion signals. A total number of bits of data input to the Reed-Solomon decoding device, and the number of error bits counted by the error bit number counter. 3. The Reed-Solomon decoding device according to claim 1, wherein the correction state monitor includes an error bit number counter that counts the number of erroneous bits indicated by the magnitude of the error, and a synchronization signal of the input data. A synchronization signal counter that counts a synchronization byte suggestion signal that is output in accordance with a total number of bits of data input to the Reed-Solomon decoding device while the synchronization signal counter counts a predetermined number of synchronization byte suggestion signals; And a bit error rate calculator that calculates a bit error rate from the number of erroneous bits counted by the error bit number counter, wherein the signal indicating the degree of error in the input data includes the bit error rate A Reed-Solomon decoding device characterized by the above-mentioned. 4. The Reed-Solomon decoding device according to claim 3, wherein the bit error rate calculator includes a divider that divides the number of error bits by a total number of bits of the input data. Solomon decoding device. 5. The Reed-Solomon decoding device according to claim 4, wherein the bit error rate calculator calculates a value of data input to the Reed-Solomon decoding device while the predetermined number of synchronization byte indication signals is counted. A constant output unit for calculating the total number of bits in advance, and outputting the total number of bits calculated in advance when the synchronization signal counter counts the predetermined number of synchronization byte suggestion signals. Reed-Solomon decoding device. 6. The Reed-Solomon decoding apparatus according to claim 3, wherein the bit error rate calculator sets a plurality of ranges of values that the number of error bits can take in advance, and counts the predetermined number of synchronization byte indication signals. A determinator that determines to which range the set number of erroneous bits counted by the erroneous bit number counter belongs, and a value arbitrarily selected from each of the ranges set in the determinator And a bit error rate calculated in advance from the total number of bits of the input data, and an error that outputs a bit error rate corresponding to the range determined by the determiner from the bit error rates calculated in advance. A Reed-Solomon decoding device comprising: a rate output device. 7. The Reed-Solomon decoding device according to claim 2, wherein the correction state monitor includes an error symbol number counter that counts an erroneous byte number indicated by the error position, and determines a degree of error in the input data. The signals indicated are the total number of data symbols input to the Reed-Solomon decoding device while the synchronization signal counter is counting a predetermined number of synchronization byte indication signals, and the number of erroneous symbols counted by the error symbol number counter. A Reed-Solomon decoding device comprising: 8. The Reed-Solomon decoding device according to claim 1, wherein the correction status monitor includes: an error symbol number counter that counts the number of erroneous bytes indicated by the error position; While counting a predetermined number of synchronization byte indication signals output in synchronization with the synchronization signal of the input data, the total number of data symbols input to the Reed-Solomon decoding device and the error count counted by the error symbol number counter. A symbol error rate calculator that calculates a symbol error rate from the number of symbols obtained, wherein the signal indicating the degree of error in the input data includes the symbol error rate. 9. The Reed-Solomon decoding device according to claim 8, wherein the symbol error rate calculator includes: a divider that divides the number of error symbols by the total number of symbols of the input data. Solomon decoding device. 10. The Reed-Solomon decoding device according to claim 9, wherein the symbol error rate calculator calculates a value of data input to the Reed-Solomon decoding device while the predetermined number of synchronization byte indication signals are counted. The total number of symbols is calculated in advance, and when the synchronization signal counter counts the predetermined number of synchronization byte indication signals,
A constant output device for outputting the total number of symbols calculated in advance, wherein: 11. The Reed-Solomon decoding apparatus according to claim 8, wherein the symbol error rate calculator sets a plurality of possible value ranges of the number of error symbols in advance, and counts the predetermined number of synchronization byte indication signals. A determinator that determines to which range the set number of erroneous symbols counted by the erroneous symbol counter belongs during the setting, and a value arbitrarily selected from each of the ranges set in the determinator. And the total number of symbols of the input data, calculating a symbol error rate in advance, and outputting an error rate corresponding to the range determined by the determiner from among the calculated symbol error rates. A Reed-Solomon decoding device comprising: a rate output device. 12. A control method for a Reed-Solomon decoding device for performing error correction of input data by using a Reed-Solomon code, comprising: a syndrome calculating step of calculating a syndrome from the input data; and an error locator polynomial using the syndrome. An Euclidean mutual calculation step of calculating an error evaluation polynomial; an error position calculation step of calculating an error position indicating an error byte of the input data from the error position polynomial and the error evaluation polynomial; An error magnitude calculating step of calculating the magnitude of an error indicating which bit is erroneous among the bits constituting the erroneous byte indicated by the error location, and the error location and the magnitude of the error an error correcting step of correcting the input data using ri, Yuktobanian generated by serial Euclidean mutual division computation steps
The lid processing error flag and the error position calculation step
The logical sum signal with the generated Chien search error flag
Receiving the uncorrectable suggestion signal, and
Error free indicating whether there is a Reed-Solomon decoding error
-Generate a suggestion signal, and determine the bit error rate or symbol error rate,
Is the total number of bits of the input data and the number of error bits.
Contains the total number of input data symbols and the number of error symbols.
No method for controlling the Reed-Solomon decoding apparatus comprising: a, a correction state monitoring step of generating a signal indicating the degree of error in the input data. 13. The control method for a Reed-Solomon decoding device according to claim 12, wherein the correction state monitoring step includes: an error bit number counting step for counting the number of erroneous bits indicated by the error magnitude; A synchronization signal counting step of counting a synchronization byte suggestion signal output in accordance with a synchronization signal of data; and a counter input to the Reed-Solomon decoding device while counting a predetermined number of synchronization byte suggestion signals by the synchronization signal counting step. A bit error rate calculation step of calculating a bit error rate from the total number of data bits and the number of erroneous bits counted in the error bit number counting step, wherein the signal indicating the degree of error in the input data is , A Reed-Solomon decoding device comprising the bit error rate, Your way. 14. The control method for a Reed-Solomon decoding device according to claim 13, wherein the bit error rate calculating step sets a plurality of possible value ranges of the number of error bits in advance and suggests the predetermined number of synchronization bytes. A determining step of determining to which range the number of error bits counted by the number of error bits counting step during signal counting belongs to the set range; and The bit error rate is calculated in advance from the selected value and the total number of bits of the input data, and when the range is determined by the determination step, the bit error rate is determined from the bit error rates calculated in advance. An error rate output step of outputting a bit error rate corresponding to the set range, a control method of a Reed-Solomon decoding device, comprising: . 15. The method for controlling a Reed-Solomon decoding device according to claim 12, wherein the correcting state monitoring step includes: an error symbol number counting step of counting the number of erroneous bytes indicated by the error position. While counting a predetermined number of synchronization byte indication signals output in accordance with the synchronization signal of the input data, the total number of data symbols input to the Reed-Solomon decoding device and the error symbol number counting step are counted. A symbol error rate calculation step of calculating a symbol error rate from the number of erroneous symbols obtained, wherein the signal indicating the degree of error in the input data includes the symbol error rate. Control method. 16. The control method for a Reed-Solomon decoding device according to claim 15, wherein the symbol error rate calculating step sets a plurality of ranges of values that the number of erroneous symbols can take in advance and suggests the predetermined number of synchronization bytes. A determining step of determining to which range the set number of erroneous symbols counted by the erroneous symbol number counting step during signal counting belongs; and any one of the ranges set in the determining step. And the total number of symbols of the input data, a symbol error rate is calculated in advance, and when the range is determined by the determiner, the symbol error rate is determined from the symbol error rates calculated in advance. An error rate output step of outputting a symbol error rate corresponding to the set range. Method of controlling the issue apparatus. 17. A computer-readable storage medium for storing a code of a program for controlling a Reed-Solomon decoding device that performs error correction of input data using a Reed-Solomon code, wherein the code of the program converts a syndrome from the input data. The code of the syndrome calculation step to be calculated, the code of the Euclidean mutual division calculation step of calculating the error location polynomial and the error evaluation polynomial using the syndrome, and the error byte of the input data from the error location polynomial and the error evaluation polynomial An error position calculating step of calculating an error position indicated by the code; and an error size calculating step of calculating an error size indicating which of the bits constituting the erroneous byte indicated by the error position indicates an error. And the error location and the above An error correction step code for correcting input data using the magnitude of the error, and a Euclidean algorithm generated in the Euclidean mutual calculation step.
The lid processing error flag and the error position calculation step
The logical sum signal with the generated Chien search error flag
Receiving the uncorrectable suggestion signal, and
Error free indicating whether there is a Reed-Solomon decoding error
-Generate a suggestion signal, and determine the bit error rate or symbol error rate,
Is the total number of bits of input data and the number of error bits.
Includes the total number of symbols in the input data and the number of error symbols.
No, storage medium characterized by having a code correction state monitoring step of generating a signal indicating the degree of error in the input data.