EP0445730A2 - Error correction system capable of correcting an error in a packet header by the use of a Reed-Solomon code - Google Patents
Error correction system capable of correcting an error in a packet header by the use of a Reed-Solomon code Download PDFInfo
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- EP0445730A2 EP0445730A2 EP91103307A EP91103307A EP0445730A2 EP 0445730 A2 EP0445730 A2 EP 0445730A2 EP 91103307 A EP91103307 A EP 91103307A EP 91103307 A EP91103307 A EP 91103307A EP 0445730 A2 EP0445730 A2 EP 0445730A2
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- 208000011580 syndromic disease Diseases 0.000 claims abstract description 54
- 238000001514 detection method Methods 0.000 claims abstract description 14
- 238000004364 calculation method Methods 0.000 claims description 20
- 238000012545 processing Methods 0.000 claims description 12
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
- H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
Definitions
- the transmitter is operable to calculate the first through the fourth error code units r0 to r3 in accordance with Equations 1 through 4 mentioned above. More specifically, the illustrated transmitter is successively supplied with an input signal of four bits, or each symbol unit in parallel through an input terminal 101. Each symbol unit of the packet header is sent to the transmitter in the order of a5, a6 a7, a8, a9 and a10.
- the second syndrome S1 is divided by the first syndrome S0 to obtain a result of division which is sent to the R1 register (Fig. 2) and which is memorized as a first content represented by a vector representation. Such division is carried out by the use of the access section 47 and the calculation converting RAM 46. Subsequently, the first content of the R1 register is converted into a power of ⁇ , as depicted at ⁇ R1 in Fig. 5, and memorized as a second content in the R1 register again.
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- Detection And Correction Of Errors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Description
- This invention relates to an error correction system for use in a packet exchange system which can transfer packets without necessity of re-transmission of information, such as datum, a speech, and an image.
- Heretofore, a packet exchange system of the type described is used for transferring a packet from a transmission end to a destination one of reception ends. In this event, information signals, such as a speech or voice signal and an image signal, are preceded by a packet header and are transmitted or conveyed by the packet in the packet exchange system which is operable in accordance with non-high level data link control procedure. The packet header is helpful to specify the destination reception end and the transmission end.
- It is to be noted that no re-transmission is carried out in such a system and that the packet should be delivered to the destination reception end without fail. Otherwise, the information signals are undesirably sent to a wrong one of the reception ends. Therefore, correct transmission is required for the packet header as compared with transmission of the information signals, such as the speech and the image signals.
- In general, it is known that use of a Hamming code or addition of a parity bit is considered in connection with an information signal of a comparatively short data length of, for example, several bits. In this case, a single bit error or a double bit error is corrected by use of the Hamming code or addition of the parity bit when the information signal has a short date length, as mentioned before.
- It is mentioned here that the packet header is usually composed of a long data length of, for example, several tens of bits. In addition, the packet exchange system is often used in very bad circumstances such that the packet header is subjected to an influence of a noise. Taking this into account, a double error, a triple error or a t-tuple error more than the triple error very often takes place in the packet header and may be preferably corrected in each packet header.
- Conventionally, consideration is however directed neither to correction of the packet header nor to correction of a double or a triple error.
- It is an object of this invention to provide an error correction system which is applicable to a packet exchange system and is capable of correcting a wide variety of errors in a packed header.
- It is another object of this invention to provide an error correction system of the type described, which is capable of correcting both single and double errors in the packet header.
- It is still another object of this invention to provide a transmitter which is applicable to the error correction system and which is capable of transmitting a packet header which can correct the single or the double error.
- It is yet another object of this invention to provide a receiver which is applicable to the error correction system and which is small in size and capable of preferably correcting the double error in the packet header.
- According to an aspect of this invention, a transmitter is for use in transmitting a packet which includes an input signal and a header information signal which precedes said input signal. The transmitter comprises packet header forming means responsive to the header information signal and operable in accordance with a predetermined algorithm determined for production of a Reed-Solomon code. The packet header forming means is for forming a packet header which is composed of the header information signal and an error correcting code signal for correcting the header information signal. The error correcting code signal is formed by the Reed-Solomon code. The transmitter further comprises signal producing means for producing the packet header followed by the input signal to form the packet.
- According to another aspect of this invention, a receiver is for use in combination with the transmitter to receive the packet as a reception packet including a reception packet header corresponding to the packet header and to produce a reception packet header information signal and a reception error correcting code signal corresponding to the packet header information and the error correcting code signal, respectively. The receiver comprises syndrome calculation means responsive to the reception packet header for calculating a plurality of syndromes on the basis of preselected formulae determined for the Reed-Solomon code, error detecting means coupled to the syndrome calculating means for detecting occurrence of an error in the reception packet header by monitoring the syndromes to produce an error detection signal on detection of the error, and error correcting means formed by a hardware circuit, energized by the error detection signal, and operable in accordance with a program determined for processing the Reed-Solomon code, for correcting the error in said reception packet header to produce the reception packet header information signal subjected to the error correction.
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- Fig. 1 is a block diagram of a transmitter used for an error correction system according to a preferred embodiment of this invention;
- Fig. 2 is a block diagram of a receiver used for the error correction system according to the preferred embodiment of this invention;
- Fig. 3 is a time chart for use in describing operation of the transmitter illustrated in Fig. 1;
- Fig. 4 is a time chart for use in describing a relationship between a transmission data signal and a reception data signal which are produced and received by the transmitter and the receiver, respectively; and
- Fig. 5 is a flow chart for use in describing operation of the receiver illustrated in Fig. 3.
- Referring to Fig. 1, an error correction system according to a preferred embodiment of this invention comprises a transmitter and a receiver both of which are illustrated in Figs. 1 and 2, respectively, and which are practically implemented by a very large scale integrated circuit (VLSI).
- Briefly, the transmitter illustrated in Fig. 1 produces a packet information signal which may be, for example, a data signal, a speech signal, or an image signal. In this case, the information signal is preceded by a packet header which specifies a destination receiver and the like and which comprises a header or a significant information signal of twenty-four bits and an error correcting code (namely, a redundancy code) following the header information signal. The packet information signal itself is directly regardless of this invention and will not be described any longer.
- In Fig. 3, the packet header is divided into the header information signal depicted at HI (Fig. 3) and the error correcting code which is shown as a forward error correcting code (FEC). The header information signal HI is subdivided into six signal units each of which is composed of four bits, namely, a half byte. The four bits are assumed to form a single symbol. The six signal units are represented by a5, a6, a7, a8, a9, and a10 with a0 to a4 omitted. This is because a0 to a4 are regarded as null data units in this invention, as will become clear as the description proceeds. In this connection, a5 to a10 may be referred to as first through sixth signal units, respectively, and regarded as being located at fifth through tenth symbol positions, respectively.
- On the other hand, the forward error correcting code (FEC) is added to the first through the sixth signal units a5 to a10 and is composed of first through fourth error code units r0 to r3 each of which is composed of four bits, namely, a half byte. It is to be noted that the illustrated packet header is formed by a Reed-Solomon code which is defined on a Galois field GF (2⁴). Herein, let the Reed-Solomon code have a total symbol number equal to 15, a significant information symbol number equal to 11, and a minimum hamming distance equal to 5 and be represented by RS (15, 11, 5). The Reed-Solomon code (15, 11, 5) can be defined by a polynomial P(x) of a fourteenth order which is given by:
- In the example, the significant symbol number is restricted to 6 and as a result, the total symbol number is equal to 10 as illustrated in Fig. 3. Under the circumstances, the first through the fourth error code units r0 to r3 may be collectively called the redundancy code and that are calculated in accordance with
Equations 1 through 4 given by:
r₁
r₂
r₃
where
and where in turn, ⊕ is representative of an Exclusive OR operation between four bits and four bits, a dot (.) is representative of a multiplication between a couple of four bits, and H is representative of a hexadecimal number. If x = αi, and y = αj, such a multiplication is given by α(i+j)mod 15 and will be called a specific multiplication. When either of x and y is equal to 0, the multiplication of x and y is equal to 0(0000). - In Fig. 1, the transmitter is operable to calculate the first through the fourth error code units r₀ to r₃ in accordance with
Equations 1 through 4 mentioned above. More specifically, the illustrated transmitter is successively supplied with an input signal of four bits, or each symbol unit in parallel through aninput terminal 101. Each symbol unit of the packet header is sent to the transmitter in the order of a₅, a₆ a₇, a₈, a₉ and a₁₀. - In the example being illustrated, the transmitter comprises first through
third multipliers 102 to 104 each of which carries out the multiplication between a couple of four bits, as mentioned above, and first throughfourth registers 106 to 109 of four bits each of which is connected to first through fourth Exclusive ORgates 111 to 114 connected to the first through thethird multipliers input terminal 101. - With this structure, the first signal unit a₅ of four bits is at first given as the input symbol unit to the
input terminal 101 and is sent through the fourthExclusive OR gate 114 to the first through thethird multipliers 102 to 104 to be latched to the first through thefourth registers 106 to 109. In this event, thefirst register 106 is loaded with a product of a₅.α⁶ while thesecond register 107 is loaded with a₅. Likewise, the third and thefourth registers third multipliers 102 to 104 through theinput terminal 101 and the fourthExclusive OR gate 114. As a result, the first through the fourth error code units r₀ to r₃ represented byEquations 1 to 4 are produced through first throughfourth output lines 116 to 119, respectively. Such production of the first through the fourth error code units r₀ to r₃ is carried out in accordance with the predetermined polynomial. In addition, themultipliers 102 to 104 are known in the art and will not be described in detail later. Thus, a combination of themultipliers 102 to 104, theregisters 106 to 109, and the Exclusive ORgates 111 to 114 serves to form the packet header and may be called a packet header forming circuit. Theoutput lines 116 to 119 may be referred to as a signal producing circuit for the packet header. - Temporarily referring to Fig 4, it is assumed that the first through the sixth signal units a₅ to a₁₀ and the first through the fourth error code units r₀ to r₃ are transmitted from the transmitter to the receiver and received as first through sixth reception signal units b₅ to b₁₀ and first through fourth reception error code units t₀ to t₃. In addition, the fifth through the sixth reception signal units b₅ to b₁₀ are decoded with reference to the first through the fourth reception error code units t₀ to t₃ into first through sixth decoded signal units which are depicted at b₅' to b₁₀' and which are subjected to error correction in the receiver illustrated in Fig. 2.
- Referring to Fig. 2 again and Fig. 5, description will be made about error correction of the packet header which is carried out in the receiver. In Fig. 2, the illustrated receiver is supplied with the packet header as a reception packet header and is specified by a decoder portion for decoding the packet header which is produced in the manner illustrated in Fig. 1. The reception packet header includes a reception packet header information signal and a reception error correcting code signal corresponding to the packet header information signal and the error correcting code signal. In Fig. 2, the decoder portion comprises a
syndrome calculator 21 and an error detector 22 both of which are structured by a hardware circuit and the remaining hardware circuit which is operable in accordance with a microprogram formed by a special-purpose assembler. - More specifically, the
syndrome calculator 21 is successively supplied with each of the first through the sixth reception signal units b₅ to b₁₀ and the first through the fourth reception error code units t₀ to t₃. - On the other hand, the first through the sixth reception signal units b₅ to b₁₀ are sent to a
reception register section 26 and memorized in first through sixth reception registers (depicted at b₅ to b₁₀) of thereception register section 26 each of which is composed of four bits. Thesyndrome calculator 21 is operable in a known manner to calculate first, second, third, and fourth syndromes S₀ to S₃ each of which is composed of four bits. Specifically, the illustratedsyndrome calculator 21 calculates first, second, third and fourth values d₀, d₁, d₂ , and d₃ given by:
d₀
d₁
d₂
d₃
-
- Herein, it is to be noted that logic circuits which carry out the calculations of
Equations 5 through 12 may be a combination of registers, multipliers, and Exclusive OR gates like in Fig. 1. Therefore, it is readily possible for those skilled in the art to design the syndrome calculator formed by such logic circuits. Taking the above into consideration, description will not be made about thesyndrome calculator 21 any longer. At any rate, each of the syndromes S₀ to S₃ is composed of four bits. - The first through the fourth syndromes S₀ to S₃ are delivered to the
error detector 23 on one hand and to first through fourth syndrome registers (depicted at S₀ to S₃) of thereception register section 26 on the other hand. - Supplied with the first through the fourth syndromes S₀ to S₃, the
error detector 23 detects from the first through the fourth syndromes S₀ to S₃ whether or not an error or errors are present in the packet header received and produces an error detection signal ED on detection of the error or errors. The error detection signal is sent to aprogram counter 27 and aprocess cycle indicator 28 to start them. As a result, theprogram counter 27 successively supplies a count signal to a read-only memory (ROM) 29 as an address signal. - Inasmuch as the read-
only memory 29 memorizes an error correcting program composed of a sequence of instructions. Each instruction is successively read out of the read-only memory 29 to be delivered to first throughfourth instruction decoders 31 to 34. The first through thefourth instruction decoders 31 to 34 supply decoded signals to atiming controller 36 controlled by theprocess cycle indicator 28 energized by theerror detector 23. Thefirst decoder 31 is operable to decode an order of each instruction while the second through thefourth decoders 32 to 34 serve to decode operands which will be depicted at X₁, X₂, and X₀ hereinafter. Thetiming controller 36 produces first, second, and third gate control signals which may be called A, B, and C gate control signals. Besides, thetiming controller 36 delivers a latch signal LA and a jump address signal JP to thereception register section 26 and theprogram counter 27, respectively. The jump address signal JP specifies an address to be jumped. Moreover, first and second constant signals CS₁ and CS₂ are also produced from thetiming controller 36 to represent first and second constants. A combination of theelements - In the illustrated example, the
reception register section 26 further comprises I, F, K, L, R₁, R₂, and R₃ registers which may be collectively called a register circuit and which are operable in a manner to be described later in addition to the registers S₀ to S₃ and b₅ to b₁₀. All of the registers S₀ to S₃, b₅ to b₁₀, I, F, K, L, and R₁ to R₃ are connected to first andsecond buses - For example, the first through the fourth syndrome registers S₀ to S₃ are connected to both the A and B buses through the gates and are initially loaded with initial values, as understood from third, fourth, and sixth columns of Table 1. The first and the second syndrome registers S₀ and S₁ are not connected to the
C bus 43 while the third and the fourth syndrome registers S₂ and S₃ are connected to theC bus 43. Anyway, the first through the fourth syndrome registers S₀ to S₃ serve to memorize the first through the fourth syndromes S₀ to S₃, respectively. Among others, the third and the fourth syndrome registers S₂ and S₃ are also used as work registers. - Likewise, the first through the sixth reception registers b₅ to b₁₀ are connected to the
A bus 41 through the A gates and to theC bus 43 but disconnected to theB bus 42. The reception registers b₅ to b₁₀ are operable to memorize the reception packet header or a corrected packet header. The I register is for memorizing an error position signal indicative of an error position while the F register serves as an index register when specific orders, such as LF and LFR, are issued and will become clear. In addition, the K and the L registers serve to memorize K and L constants which will be described later and which are calculated while the R₁ to R₃ registers serve as work registers. - Further referring to Fig. 2, the decoder portion comprises a calculation converting read-only memory (ROM) 46, an
access section 47 for accessing theROM 46, anExclusive OR section 48, aloading section 49, and acomparator section 50, all of which are formed by hardware circuits and which may be referred to as a processing circuit for processing the reception packet header. As illustrated in Fig. 2, theaccess section 47 and theExclusive OR section 48 are connected to the A and theB buses C bus 43 through the C gates C₁ and C₂, respectively, while theloading section 49 and thecomparator section 50 are connected to theA bus 41 through data lines and to theC bus 43 through the C gates C3 and C4. Such A, B, and C gates may be considered as a part of the processing circuit to selectively connect the registers and thehardware circuits 46 to 50. - Moreover, the first through the sixth decoded units b₅' to b₁₀' are produced from the first through the sixth reception registers b₅ to b₁₀ with the error or errors corrected.
- Thus, the illustrated decoder portion is divisible into logical calculation circuits, such as the
syndrome calculator 21 and theerror detector 23, and a microprogram-controlled circuit, such as 26, 27, 28, 29, 31 to 34, 36, 46, 47, 49, 49, and 50. This makes it possible to reduce a size of the decoder circuit. - In Table 2, orders and operands are enumerated which are issued from the microprogram memorized in the
ROM 29 to locate the errors and to correct them when the errors are detected by the error detector 23 (Fig. 2). As tabulated in Table 2, first through seventeenth orders, such as M, DM, B, and the like in the microprogram are exemplified and delivered to theaccess section 47, thecalculation converting RAM 46, theExclusive OR section 48, theloading section 49, and thecomparator section 50 in a manner to be described later. In the operands, the first through the seventeenth orders indicate operations shown in the columns of the meaning and the additional explanation and X₁, X₂, and X₀ represent values on the A bus, the B bus, and the C bus, respectively. - Referring to Fig. 5 together with Fig. 2, description will be made about operation of the error correction. Such error correction is started from a
first step 201 by the use of the microprogram memorized in theROM 29. Thefirst step 201 proceeds to at asecond step 202 at which Exclusive OR is calculated between a square value of the second syndrome S₁ and a product of the first syndrome S₀ and the third syndrome S₂ by the use of theExclusive OR section 48. Before such Exclusive OR calculation, the second syndrome S₁ is read out of the second syndrome register S₁ and is delivered to thecalculation converting RAM 46 to calculate the square of the second syndrome S₁ in accordance with the order of M. Likewise, the first and the third syndromes S₀ and S₂ are also read out of the first and the third syndrome registers S₀ and S₂ to calculate the product of both the syndromes. Thereafter, thecomparator section 50 compares a result of the Exclusive OR with zero to detect whether or not a single error exists in the reception packet header. If the result of the Exclusive OR is equal to zero, a single error or no error is present in the reception packet header, as known in the art. In this event, thesecond step 202 is followed by athird step 203 to carry out single error correction. Otherwise, a double error or a t-tuple error more than the double error takes place in the reception packet header. Operation is carried out so as to correct the double error in a manner to be described later. - Herein, it is to be noted that correction of a single and a double error in the Reed-Solomon code is carried out on the basis of a known procedure, although modification is somewhat made in procedure which will be described hereinafter, so as to readily process an error or errors.
- More specifically, let the result of the Exclusive OR in the
first step 201 be equal to zero and thesecond step 202 proceed to athird step 203. At thethird step 203, the second syndrome S₁ is divided by the first syndrome S₀ to obtain a result of division which is sent to the R₁ register (Fig. 2) and which is memorized as a first content represented by a vector representation. Such division is carried out by the use of theaccess section 47 and thecalculation converting RAM 46. Subsequently, the first content of the R₁ register is converted into a power of α, as depicted at αR1 in Fig. 5, and memorized as a second content in the R₁ register again. Inasmuch as the total symbol number is equal to 15 and can be represented by a polynomial which has a maximum order equal to the fourteenth order, as known in the art, the second content of the R₁ register is subtracted from a predetermined constant of 14 to indicate an error symbol position depicted at U. - Herein, it should be recollected that the significant information unit is arranged between the first and the sixth signal units a₅ and a₁₀ located at fifth through tenth symbol positions, as shown in Fig. 3 and that zeroth through fourth symbol positions are neglected. This shows that error correction may be carried out only between the fifth through the tenth symbol positions.
- Taking this into consideration, fourth and
fifth steps fifth steps comparator section 50 illustrated in Fig. 2. Under the circumstances, an error reception symbol positioned at the error symbol position U may be depicted at b(u) and should be corrected. - To this end, Exclusive OR is executed between the error reception symbol b(u) and the first syndrome S₀ by the
Exclusive OR section 48 to supply a result of the Exclusive OR to one of the first through the sixth reception registers b₅ to b₁₀ that corresponds to the error reception symbol b(u). In this case, an error symbol is corrected by the above-mentioned Exclusive OR into a correct symbol which is represented by b(i). - At a
sixth step 206, the error symbol position b(i) is rewritten by theloading section 49 to be corrected. Thus, correction of the single symbol error is carried out by the third through thesixth steps 203 to 206. - On the other hand, let the result of the Exclusive OR be not equal to zero at the
second step 202. In this event, thesecond step 202 is followed by operation of double error correction which is executed in a manner to be described hereinunder. The double error correction is started by setting the F and the I registers into zero and five, respectively. It is mentioned here that the F and the I registers are loaded with the number of the errors and an error symbol position, respectively. This means that the double error correction is started from the fifth symbol unit on the assumption that no error is detected. - Under the circumstances, operation is carried out at a
seventh step 207 which is for calculating Exclusive OR between a square of the second syndromes S₁ and a product of the second and the third syndromes S₁ and S₂. The Exclusive OR calculation is made by the use of theExclusive OR section 48 and a result of the Exclusive OR calculation is stored in the R₁ register as a first content or the R₁ register. A first product of the first and the fourth syndromes S₀ and S₃ is calculated together with a second product of the second and the third syndromes S₁ and S₃ by the use of theaccess section 47 and thecalculation converting ROM 46. The first and the second products are memorized into the R₂ and the R₃ registers. Exclusive OR calculation is carried out between the first and the second products by theExclusive OR section 48 to obtain a first result of the Exclusive OR calculation which is divided by the content of the R₁ register into a first result of division. The first result of division is held in the K register. Exclusive OR is carried out between a product of the second and the fourth syndromes S₁ and S₃ and a square of the third syndromes S₂ to calculate a second result of the Exclusive OR. The second result of the Exclusive OR is divided by the first content of the R₁ register into a second result of division sent to the K register. Such operation carried out at theseventh step 207 is made in accordance with algorithm determined in accordance with the Reed-Solomon code. - At an
eighth step 208, alpha (α) to the power stored in the I register is converted into a vector representation which is memorized in the R₂ register as a content of the R₂ register. In addition, Exclusive OR is carried out between a square of the content of the R₂ register and a product of a content of the K register and the content of the R₂ register to obtain a partial result of the Exclusive OR. Exclusive OR is further calculated between the partial result and a content of the L register to obtain a total result of the Exclusive OR. The total result is stored in the R₂ register. - Thereafter, the
eighth step 208 proceeds to aninth step 209 at which the total result calculated by theeighth step 208 is compared with zero by thecomparator section 50. If the total result is not equal to zero, theninth step 209 proceeds to atenth step 210 at which the content of the I register is compared with ten by thecomparator section 50 to carry out the above-mentioned processing about a next following one of the significant symbol units. From this fact, it is readily understood that the total result of the R₂ register becomes equal to zero only when an error is present and, otherwise, the total result does not become equal to zero. - When the content of the I register is not equal to ten, the
tenth step 210 is followed by aneleventh step 211 at which unity is added to the content of the I register to obtain (I+1) stored in the I register again. The eighth through theeleventh steps 208 to 211 are repeated until the content of the I register becomes equal to ten. - When the content of the I register becomes equal to ten at the
tenth step 210, thetenth step 210 jumps to atwelfth step 212 of detecting whether or not the content of the F register is equal to zero. No error is found out as regards the reception packet header when the content of the F register becomes equal to zero. In this event, error correction operation is finished without any correction of an error. - At the
ninth step 209, it is assumed that the total result of the R₂ register is equal to zero. In this event, theninth step 209 is succeeded by athirteenth step 213 at which unity is added to the content of the F register. This shows that an error is detected at a symbol unit indicated by the content of the I register. At afourteenth step 214, the content of the I register is subtracted from the predetermined number of 14 to specify an error symbol unit position which is held in the R registers. Thefourteenth step 214 is followed by a fifteenth step 215 which is for judging whether or not the content of the F register is equal to two. The fifteenth step 215 is executed by the use of thecomparator section 50. If the content of the F register is equal to unity, the fifteenth step 215 is succeeded by thetenth step 210 to locate an error symbol unit position in the manner mentioned before. - On the other hand, if the content of the F register is equal to two, processing is carried out for correcting a double error in accordance with a known algorithm determined in the Reed-Solomon code. Specifically, the content of the R register is subtracted from the predetermined number of 14 at a
sixteenth step 216 to obtain a result of subtraction which is held in the R₃ register. At aseventeenth step 217, a power representation of aR₃ is converted by the use of thecalculation converting ROM 46 into a vector representation of R₃ which may be called a vector content of R₃. Thereafter, the Exclusive OR is calculated between the second syndrome S₁ and (S₀xL)/R₃ to attain a result of the Exclusive OR which is stored in the R₃ register. A content of the R₃ register is divided by the content of the K register into a result of division which is held in the R₃ register. Exclusive OR is calculated between the result of the division and b(R(F)) and is sent to the b(R(f)) register which specifies an error symbol unit. Such operation is carried out in accordance with the algorithm determined for the Reed-Solomon code. At aneighteenth step 218, judgement is made whether or not the content of the F register is equal to unity. If the content of the F register is equal to unity, a content bi of the b(R(f)) register is rewritten or corrected at anineteenth step 219. Thus, a single error symbol is corrected at thenineteenth step 219. On the other hand, if the content of the F register is not equal to unity, the content of the I register is sent to the F register at atwentieth step 220 and returned back to thesixteenth step 216 to correct another error in a manner similar to that illustrated in conjunction with thesteps - As mentioned above, the packet header is formed in the transmitter by the Reed-Solomon code which is a combination of a significant information signal of 24 bits with an error correcting code of 16 bits. Such use of the Reed-Solomon code enables error correction of two half bytes in the receiver by the use of the microgram which defines procedure illustrated in Fig. 5. With this structure, it is possible to reduce a size of a hardware circuit and to shorten a processing time. In addition, it is possible to reliably transmit a data signal, a speech signal, and an image signal without necessity of distinction among them and without necessity of re-transmission.
- While this invention has thus far been described in conjunction with a preferred embodiment thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, a wide variety of the Reed-Solomon codes may be used for correcting the error or errors. In Fig. 2, the
calculation converting ROM 46 may be replaced by an RAM.
Claims (5)
- A transmitter for use in transmitting a packet which includes an input signal and a header information signal which precedes said input signal, said transmitter comprising:
packet header forming means responsive to said header information signal and operable in accordance with a predetermined algorithm determined for production of a Reed-Solomon code, for forming a packet header which is composed of said header information signal and an error correcting code signal for correcting said header information signal, said error correcting code signal being formed by the Reed-Solomon code; and
signal producing means for producing said packet header followed by said input signal to form said packet. - A receiver for use in combination with the transmitter claimed in Claim 1 to receive said packet as a reception packet including a reception packet header corresponding to said packet header and to produce a reception packet header information signal and a reception error correcting code signal corresponding to said packet header information and said error correcting code signal, said receiver comprising:
syndrome calculation means responsive to said reception packet header for calculating a plurality of syndromes on the basis of preselected formulae determined for the Reed-Solomon code;
error detecting means coupled to said syndrome calculating means for detecting occurrence of an error in said reception packet header by monitoring said syndromes to produce an error detection signal on detection of said error; and
error correcting means formed by a hardware circuit, energized by said error detection signal, and operable in accordance with a program determined for processing the Reed-Solomon code, for correcting said error in said reception packet header to produce the reception packet header information signal subjected to the error correction. - A receiver as claimed in Claim 2, said program being composed of a sequence of instructions, wherein said error correcting means comprises:
program means energized by said error detection signal for storing said program to successively produce each of said instructions;
register means responsive to said reception packet header for registering said reception packet header; and
processing means coupled to said program means and said registering means for processing said reception packet header in accordance with said program to correct said error in the reception packet header and to produce the reception packet header information signal. - A receiver as claimed in Claim 3, said instructions including a first instruction for converting calculations from one to another, a second instruction for carrying out Exclusive OR, and a third instruction for comparison, wherein said processing means comprises:
gate means coupled to said register means and said program means for selectively producing said reception error correcting code signal and said reception packet header information signal in accordance with each of said instructions;
calculation converting means coupled to said gate means on production of said first instruction for converting the calculations from one to another;
an Exclusive OR section coupled to said gate means on production of said second instruction for carrying out an Exclusive OR operation; and
a comparator section coupled to said gate means on production of said third instruction for carrying out a comparison operation. - An error correcting system for use in transmitting a packet from a transmitter to a receiver, said packet including an input signal and a header information signal which precedes said input signal and being received by said receiver as a reception packet including a reception header information signal corresponding to said header information signal, said transmitter comprising:
packet header forming means responsive to said header information signal and operable in accordance with a predetermined algorithm determined for production of a Reed-Solomon code, for forming a packet header which is composed of said header information signal and an error correcting code signal for correcting said header information signal, said error correcting code signal being formed by the Reed-Solomon code; and
signal producing means for producing said packet header followed by said input signal to form said packet;
said receiver being supplied with said packet header as the reception packet header which includes a reception error correcting code signal corresponding to said error correcting code signal in addition to said reception header information signal, said receiver comprising:
syndrome calculation means responsive to said reception packet header for calculating a plurality of syndromes on the basis of preselected formulae determined for the Reed-Solomon code;
error detecting means coupled to said syndrome calculating means for detecting occurrence of an error in said reception packet header by monitoring said syndromes to produce an error detection signal on detection of said error; and
error correcting means formed by a hardware circuit, energized by said error detection signal, and operable in accordance with a program determined for processing the Reed-Solomon code, for correcting said error in said reception packet header to produce the reception packet header information signal subjected to the error correction.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54749/90 | 1990-03-05 | ||
JP5474990 | 1990-03-05 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0445730A2 true EP0445730A2 (en) | 1991-09-11 |
EP0445730A3 EP0445730A3 (en) | 1992-12-09 |
EP0445730B1 EP0445730B1 (en) | 1997-06-11 |
Family
ID=12979418
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91103307A Expired - Lifetime EP0445730B1 (en) | 1990-03-05 | 1991-03-05 | Error correction system capable of correcting an error in a packet header by the use of a Reed-Solomon code |
Country Status (4)
Country | Link |
---|---|
US (1) | US5327438A (en) |
EP (1) | EP0445730B1 (en) |
CA (1) | CA2037527C (en) |
DE (1) | DE69126459T2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994000937A1 (en) * | 1992-06-23 | 1994-01-06 | Digital Equipment Corporation | Message in packet form with header constituted by routing information and a crc check sequence |
GB2313748A (en) * | 1996-05-31 | 1997-12-03 | Northern Telecom Ltd | Error detection/correction for ATM cells/frames |
US6560653B1 (en) | 1997-08-08 | 2003-05-06 | Telefonaktiebolaget Lm Ericsson (Publ) | System and method for processing a signalling message in an ATM network |
US6728921B1 (en) | 1996-05-31 | 2004-04-27 | Nortel Networks Limited | Cell based data transmission method |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0993143A (en) * | 1995-09-27 | 1997-04-04 | Victor Co Of Japan Ltd | Error check code generating method and device |
JPH09266460A (en) * | 1996-03-28 | 1997-10-07 | Sony Corp | Transmission reception system |
JPH1174868A (en) | 1996-09-02 | 1999-03-16 | Toshiba Corp | Information transmission method, coder/decoder in information transmission system adopting the method, coding multiplexer/decoding inverse multiplexer |
JP3449204B2 (en) | 1998-01-23 | 2003-09-22 | ソニー株式会社 | Control device, wireless transmission device, and wireless transmission method |
EP1059775A1 (en) * | 1999-06-09 | 2000-12-13 | Lucent Technologies Inc. | Error correction based on headers |
US6807648B1 (en) * | 1999-09-13 | 2004-10-19 | Verizon Laboratories Inc. | Variable-strength error correction in ad-hoc networks |
FR2852180B1 (en) * | 2003-03-07 | 2005-08-26 | Thales Sa | METHOD AND SYSTEM FOR DATA PROTECTION WITH HEADER IN A TRANSMISSION SYSTEM |
US7443785B2 (en) * | 2004-03-17 | 2008-10-28 | Sony Ericsson Mobile Communications Ab | Selective error correction for ad hoc networks having multiple communication modes |
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WO1985000714A1 (en) * | 1983-07-29 | 1985-02-14 | Telediffusion De France | System for the correction of errors of digital signals coded in reed-solomon code |
GB2216752A (en) * | 1988-03-02 | 1989-10-11 | Cyclotomics Inc | Forward error correction in packet switched communications |
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US4500989A (en) * | 1982-08-02 | 1985-02-19 | Dahod Ashraf M | Digital communication system |
GB2156555B (en) * | 1984-03-24 | 1988-03-09 | Philips Nv | Error correction of data symbols |
US4827478A (en) * | 1987-11-30 | 1989-05-02 | Tandem Computers Incorporated | Data integrity checking with fault tolerance |
US4979174A (en) * | 1988-12-29 | 1990-12-18 | At&T Bell Laboratories | Error correction and detection apparatus and method |
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1991
- 1991-03-04 CA CA002037527A patent/CA2037527C/en not_active Expired - Lifetime
- 1991-03-05 EP EP91103307A patent/EP0445730B1/en not_active Expired - Lifetime
- 1991-03-05 DE DE69126459T patent/DE69126459T2/en not_active Expired - Fee Related
-
1993
- 1993-10-07 US US08/133,267 patent/US5327438A/en not_active Expired - Lifetime
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WO1985000714A1 (en) * | 1983-07-29 | 1985-02-14 | Telediffusion De France | System for the correction of errors of digital signals coded in reed-solomon code |
GB2216752A (en) * | 1988-03-02 | 1989-10-11 | Cyclotomics Inc | Forward error correction in packet switched communications |
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Title |
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IEEE TRANSACTIONS ON COMMUNICATIONS vol. 35, no. 11, November 1987, NEW-YORK,US; pages 1113 - 1123 MORTIMER ET AL 'the design of a high-performance error-correcting coding scheme for the canadian broadcast telidon system based on reed-solomon codes' * |
IEEE TRANSACTIONS ON COMMUNICATIONS vol. 37, no. 12, December 1989, NEW-YORK,US; pages 1264 - 1274 PURSLEY 'delay and throughput for three transmission schemes in packet radio networks' * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994000937A1 (en) * | 1992-06-23 | 1994-01-06 | Digital Equipment Corporation | Message in packet form with header constituted by routing information and a crc check sequence |
US5954835A (en) * | 1992-06-23 | 1999-09-21 | Cabletron Systems, Inc. | Check sequence preservation |
US6425106B1 (en) | 1992-06-23 | 2002-07-23 | Enterasys Networks, Inc. | Extended ECC system |
GB2313748A (en) * | 1996-05-31 | 1997-12-03 | Northern Telecom Ltd | Error detection/correction for ATM cells/frames |
GB2313748B (en) * | 1996-05-31 | 2000-12-20 | Northern Telecom Ltd | Cell based data transmission method |
US6230297B1 (en) | 1996-05-31 | 2001-05-08 | Nortel Networks Limited | Cell based data transmission method |
US6728921B1 (en) | 1996-05-31 | 2004-04-27 | Nortel Networks Limited | Cell based data transmission method |
US6560653B1 (en) | 1997-08-08 | 2003-05-06 | Telefonaktiebolaget Lm Ericsson (Publ) | System and method for processing a signalling message in an ATM network |
Also Published As
Publication number | Publication date |
---|---|
CA2037527A1 (en) | 1991-09-06 |
EP0445730A3 (en) | 1992-12-09 |
EP0445730B1 (en) | 1997-06-11 |
CA2037527C (en) | 1999-05-25 |
DE69126459D1 (en) | 1997-07-17 |
DE69126459T2 (en) | 1997-10-09 |
US5327438A (en) | 1994-07-05 |
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