JP3286556B2 - Low-pass filter of PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a low-pass filter for a PLL circuit which contributes to shortening the time until the PLL circuit is stabilized.

[0002]

2. Description of the Related Art In general, there is known a PLL circuit in which the time from rising to stabilization is reduced, as shown in FIG. In FIG. 4, the oscillation output signal of the VCO 1 is frequency-divided by the programmable divider 2 at a variable frequency division ratio and applied to the phase comparison circuit 3. Further, a reference signal having a fixed frequency is generated from the reference oscillation circuit 4, divided by a fixed division ratio in the reference divider 5, and applied to the phase comparison circuit 3. The phase comparison circuit 3 detects whether the phase of the output signal of the programmable divider 2 is delayed or advanced compared to the output signal of the reference divider 5, and generates an output signal corresponding to the delay or advance. The output signal corresponding to the delay or advance is converted by the charge pump circuit 6 into a ternary signal of H level, L level or high impedance. The ternary signal is smoothed by a low-pass filter 9 including a resistor 7 and a capacitor 8, and a frequency control signal applied to the VCO 1 is generated. The oscillation frequency of the VCO 1 is
Are automatically adjusted so that the phases of the two input signals coincide with each other, so that an output signal having a stable frequency can be obtained from the VCO 1.

Incidentally, the circuit shown in FIG.
A charge-up amplifier 10 connected in parallel to the resistor 7, a constant current source 11 for generating an operation current of the charge-up amplifier 10,
Turns on the supply of the operating current to the charge-up amplifier 10.
A switch 12 for controlling off and an on / off control circuit for controlling on / off of the switch 12 are provided.

When the PLL circuit starts up, the on / off control circuit 13 turns on the switch 12, the output current of the constant current source 11 flows to the charge-up amplifier 10, and the charge-up amplifier 10 operates. Charge-up amplifier 1
0 supplies current to the capacitor 8 and the capacitor 8
To charge quickly. Therefore, the terminal voltage V1 of the capacitor 8 rapidly rises as shown in FIG. After a lapse of a predetermined time, the switch 12 is turned off by the output signal of the on / off control circuit 13, so that the operation of the charge-up amplifier 10 is stopped, the rapid charging of the capacitor 8 is completed, and the PLL circuit operates as described above. Start operation.

[0005]

Generally, a time constant determined by the resistor 7 and the capacitor 8 is set to be large in order to operate the PLL circuit stably. Therefore, after the rapid charging is completed, the capacitor 8 is charged with the time constant of the resistor 7 and the capacitor 8, so that the terminal voltage V1 of the capacitor 8 gradually rises as shown in FIG. It took some time for charging of 8 to be completed. Therefore, even if the capacitor 8 is rapidly charged to shorten the time from the rise to the stabilization of the PLL circuit, it takes a long time until the PLL circuit is finally stabilized, and the time reduction is actually improved. Did not.

[0006]

According to the present invention, in a PLL circuit, a low-pass filter for generating a frequency control signal for controlling an oscillation frequency of the VCO based on a phase difference between an output signal of the VCO and a reference signal. A time constant control circuit that generates a time constant control signal, a resistance circuit whose resistance value smoothly changes from small to large according to the time constant control signal, and one end connected to an output terminal of the resistance circuit. And a first capacitor connected thereto.

Further, the resistance circuit includes a differential circuit whose conductance changes smoothly from large to small in response to the time constant control signal. Further, the time constant control circuit includes a second capacitor, and generates a time constant control signal whose magnitude changes smoothly according to charging of the second capacitor.

According to the present invention, when the PLL circuit starts up, the resistance value of the resistance circuit smoothly changes from small to large according to the time constant control signal of the time constant control circuit. As a result, the resistance circuit and the first capacitor The time constant set by the above changes smoothly from small to large. Therefore, the first capacitor is charged rapidly at first, and the charging speed gradually decreases.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing an embodiment of the present invention. Reference numeral 14 denotes a differential circuit in which the output signal of a charge pump circuit 6 is smoothed together with a capacitor 8 and the conductance is changed by an operation current. Is a time constant control circuit for generating a time constant control signal for changing a time constant determined by the capacitor 8 and the resistance circuit 14, and 16 is a circuit for inverting the output signal of the time constant control circuit 15. , A current mirror circuit to be supplied to the differential circuit of the resistance circuit 14. In FIG. 1, the same circuits as those in the conventional example of FIG. 4 are denoted by the same reference numerals.

In FIG. 1, when the PLL circuit is activated,
A time constant control signal a is generated from the time constant control circuit 15, and the time constant control signal a decreases as time passes as shown in FIG. The time constant control signal a is supplied as an operating current I1 to the differential circuit 14a of the resistance circuit 14 via the current mirror circuit 16. Since the conductance of the differential circuit 14 is proportional to the operating current I1, when the operating current I1 decreases over time, the conductance of the differential circuit 14a decreases smoothly. Therefore, due to the decrease of the time constant control signal a, the resistance value of the resistance circuit 14 smoothly increases with time as shown in FIG. Here, the resistance value of the resistor circuit 14 is R1, and the capacitance of the capacitor 8 is C1.
If it is set to 1, this time constant τ1 becomes R1 × C1. P
When the LL circuit starts up, τ1 is initially small, and then
Since the resistance value R1 of the resistance circuit 14 increases smoothly, the time constant τ1 increases smoothly with time.

Next, the change of the terminal voltage V1 of the capacitor 8 according to the change of the time constant will be described. First, PL
Immediately after the rise of the L circuit, since the time constant τ1 is small, the current supplied to the capacitor 8 is large, and the capacitor 8 is rapidly charged. Therefore, the voltage V1 rises rapidly. Thereafter, the time constant τ1 gradually increases, the capacitor 8 is charged according to the time constant τ1 corresponding to the elapsed time, and the terminal voltage V1 of the capacitor 8 also increases. During this time, since the time constant τ1 increases, the rise of the voltage V1 also gradually becomes gentle. Time elapses and the time constant τ
When 1 is sufficiently large, the rise of the voltage V1 is slowed down, but the charges are sufficiently charged with the respective time constants.
The charging of the condenser 8 is completed in a short time. Therefore, P
The LL circuit can be stabilized in a short time from the rise.

FIG. 2 shows the resistance circuit 14 and the time constant control circuit 1.
FIG. 17 is a circuit diagram showing a specific example of the transistor 5; 17 is a transistor to which the output signal of the charge pump circuit 6 is applied to the base; 18 is a transistor 18 via resistors 19 and 20
Transistors 21 and 22 are connected to the collectors of transistors 17 and 18, respectively, and are diode-connected transistors 23 and 2
Reference numeral 4 denotes a transistor to which the voltage Va is applied to the base and which is connected to the collectors of the transistors 21 and 22, respectively; 25 and 26, transistors which are differentially connected and whose bases are connected to the collectors of the transistors 17 and 18; Transistors 28 and 29 for the buffer connected to the collector of the transistor 26 are transistors 17 and 18 and transistors 25 and 26
, 30 and 31 are differentially connected transistors, 32
Is a capacitor charged by the output current of the constant current source 33, and 34 is a current mirror circuit for inverting the collector current of the transistor 29.

The operation of the circuit shown in FIG. 2 will be described with reference to transfer functions. The output signal of the charge pump circuit 6 is applied to the base of the transistor 17, and the transistors 17 and 18
Are differentially connected, the collector currents of the transistors 17 and 18 are generated according to the base voltage difference. Since the output signal is fed back to the base of the transistor 18, the base voltages of the transistors 17 and 18 are set to Vi, respectively.
Assuming that n and Vout are R and the resistance values of the resistors 19 and 20 are R, the current Δi1 flowing through the resistors 19 and 20 is

[0014]

(Equation 1)

## EQU1 ## The emitter resistances of the transistors 17 and 18 are sufficiently smaller than the resistances 19 and 20, and can be ignored. According to equation (1), Δi1 is generated according to the base voltage difference between the transistors 17 and 18 and flows to the transistors 21 and 23 and the transistors 22 and 24 via the transistors 17 and 18. here,
Since the emitter resistances of the transistors 21 to 24 are set equal, the value of the emitter resistance is set to re1.
Difference ΔV1 between collector voltages of transistors 17 and 18
Is

[0016]

(Equation 2)

## EQU1 ## Further, transistors 17 and 1
The collector voltage of 8 is applied to the bases of the transistors 25 and 26, and a collector current is generated from the transistors 25 and 26 according to the difference between the base voltages. In particular, if the emitter resistance of the transistors 25 and 26 is re2, the current flowing from the collector of the transistor 26 to the capacitor 8 is i2

[0018]

(Equation 3)

## EQU1 ## This current i2 is supplied to the capacitor 8, and the capacitor 8 is charged and discharged. The terminal voltage of the capacitor 8 corresponding to the charge / discharge is transmitted to the next stage VCO 1 via the transistor 26 as the output voltage Vout. When the capacitance of the capacitor 8 is C and the terminal voltage of the capacitor 8 is Vout, the current i2 is

[0020]

(Equation 4)

Can be expressed as follows. From Equations (3) and (4), the relationship between the input and output signals is shown.

[0022]

(Equation 5)

And the time constant τ1 is

[0024]

(Equation 6)

## EQU1 ## The circuit of FIG.
F and can serve as a loop filter in the PLL. Next, the operation of the PLL circuit at the time of rising will be described. The power supply voltage Vc is applied to the circuit of FIG.
When c1 and Vcc2 are turned on, first, the constant current source 33
The capacitor 32 is charged by the output current, and the terminal voltage Vs of the capacitor 32 rises as shown in FIG. Due to the rise of the voltage Vs, the base voltage of the transistor 31 has a relationship as shown in FIG. 3E with respect to the reference voltage Vref applied to the base of the transistor 30. Transistors 30 and 31 are differentially connected, and a collector current is generated according to the difference between their base voltages. Therefore, the collector current of transistor 30 gradually decreases with time, and the output current a of current mirror circuit 34 becomes Fig. 3 (b)
And so on. The output current a is further inverted by the current mirror circuit 16, and a part of the emitter current of the transistors 25 and 26 is drawn into the current mirror circuit 16. The fixed operating current I28 from the transistor 29 and the output current Ia of the current mirror circuit 16 flow through the transistors 25 and 26. Therefore, as the output current a decreases, the current drawn into the current mirror circuit 16 also decreases.
The current flowing through transistors 25 and 26 also decreases.

By the way, when α is a constant, the emitter resistance re2 of the transistors 25 and 26 is:

[0027]

(Equation 7)

The emitter resistance re2 is inversely proportional to the current Ia. Therefore, the emitter resistance re2 increases in accordance with the decrease in the output current Ia. From the equation (6), it is clear that the time constant τ1 is proportional to the emitter resistance re2. Therefore, the time constant τ1 is proportional to the current Ia.
Therefore, when the PLL circuit starts up, the emitter resistances of the transistors 25 and 26 increase with the elapse of time, and accordingly, the time constant τ1 smoothly increases as shown in FIG.

If the capacitance of the capacitor 31 is changed to change the rise of the voltage VS with the lapse of time, the decrease of the output current Ia of the current mirror circuit 16 with the lapse of time changes. Therefore, the time constant τ1 corresponding to the lapse of time is changed. And the time for completing the charging of the capacitor 8 also changes. Therefore, by changing the capacity of the capacitor 31, the time from the rise of the PLL circuit to the stabilization can be freely set.

[0030]

According to the present invention, when the PLL circuit starts up, the resistance value of the resistance circuit smoothly changes from small to large by the time constant control signal of the time constant control circuit. Since the time constant set by one capacitor changes smoothly from small to large, the first capacitor constituting the low-pass filter of the PLL circuit is rapidly charged at first, and the charging speed is gradually reduced, and the first capacitor is sufficiently charged. One capacitor can be charged. At this time, the first capacitor is sufficiently charged with the charging ability determined by the time constant at that time while the time constant is smoothly increased, so that the time from the start of the PLL circuit to the completion of charging can be reduced. .

Further, since the resistance circuit is constituted by a differential circuit having a variable conductance, a low-pass filter suitable for integration can be provided. Further, the resistance value of the resistor circuit changes according to the charge amount of the second capacitor, and the rising time of the terminal voltage of the capacitor changes by changing the capacity of the second capacitor. Therefore, the charging time of the first capacitor changes, and the PLL circuit changes. The time from the rise to the stabilization can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a specific circuit example of a resistor circuit 14 and a time constant control circuit 15 of FIG.

FIG. 3 is a characteristic diagram showing output characteristics of FIG. 1 and a conventional example.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 VCO 2 Programmable divider 3 Phase comparison circuit 4 Reference oscillation circuit 5 Reference divider 6 Charge pump circuit 8 Capacitor 14 Resistance circuit 15 Time constant control circuit 16 Current mirror circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/23 H03H 11/00-11/54

Claims (2)

(57) [Claims] 1. A low-pass filter for generating a frequency control signal for controlling an oscillation frequency of a VCO based on a phase difference between an output signal of the VCO and a reference signal, the PLL circuit comprising: , A first differential circuit whose conductance smoothly changes from large to small in accordance with the time constant control signal, and a PLL circuit that stabilizes the conductance of the first differential circuit. And a second differential circuit that sets a predetermined conductance as a loop filter when the first capacitor is connected to an output terminal of the resistor circuit. A low-pass filter of the PLL circuit to perform. 2. The time constant control circuit according to claim 1, wherein the time constant control circuit includes a second capacitor, and generates a time constant control signal whose magnitude smoothly changes in accordance with charging of the second capacitor. Low pass filter for PLL circuit.