JP2923198B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer utilizing a phase-locked loop, and more particularly to a frequency synthesizer which can be used for a local oscillator circuit of a mobile radio device which requires high-speed response at the time of frequency switching and signal purity. .

[0002]

2. Description of the Related Art FIG. 2 shows a connection diagram when a general phase locked loop is applied to a frequency synthesizer.
Mainly, the role of the loop filter 6 will be described. The output of the reference oscillator 3 is supplied to a first frequency divider 4 whose frequency division ratio is normally fixed.
, And is input to the phase comparator 1. Voltage controlled oscillator 2
Is input to the phase comparator 1 through the second frequency divider 5 whose frequency division ratio can be set by the frequency division signal from the terminal T2. Basically, there are various types of circuit types for the phase comparator which is a multiplier. In recent years, a digital phase comparator which is frequently used outputs a pulse signal and the pulse width is input to the phase comparator 1. It changes according to the phase difference. Since the loop filter 6 smoothes the output of the phase comparator into a DC voltage and controls the frequency of the voltage controlled oscillator 2, it is basically a low-pass filter, and more specifically, a first-order lag filter. , A lag-lead filter, an active filter, or a secondary filter obtained by combining them.

(Cited literature "Understanding PLL application techniques" Japan Broadcast Publishing Association)

[0004]

SUMMARY OF THE INVENTION A low-pass filter comprises:
The output always has a delay with respect to the input change. In general, if the filter effect is strengthened by lowering the cutoff frequency, the delay increases. Conversely, in order to speed up the response, the filter effect must be reduced by increasing the cutoff frequency.
This means that in a frequency synthesizer using a phase-locked loop in which the low-pass filter is used as a loop filter, even if the frequency division ratio changes and the output of the phase comparator changes, the frequency of the voltage controlled oscillator changes. It takes a certain period of time to stabilize, and if the filter effect is reduced to increase the response speed, the noise component superimposed on the DC control voltage or the high-frequency component of the pulse signal increases, and the output signal purity of the oscillator increases. It contained the conflicting problem of falling.

FIG. 5 shows an embodiment of a loop filter according to the prior art. A resistor R1 and a capacitor C are shown in FIG.
1, a first low-pass filter, and resistors R2, R3,
Since the second low-pass filter composed of the capacitors C2 and C3 is directly connected and all the elements are linear and constant, there is a limit in sufficiently responding to the above purpose.

As one method of solving this, for example, an attempt has been made to connect an electronic switch in parallel with the resistor R2 in FIG. 5 and switch the cutoff frequency by turning it on and off. However, there is a problem in that a shock noise is generated due to the parasitic capacitance or the like, and the oscillation frequency fluctuates.

[0007]

The object of the present invention is to insert two diodes connected in parallel with opposite polarities as non-linear circuits between the stages of the first and second low-pass filters.

[0008]

The present invention applies the fact that the impedance of a diode greatly changes depending on the magnitude of its forward bias current, and the loop is switched between a dynamic state of a phase-locked loop, that is, a frequency switching, and a static state, that is, a phase locked state. It is intended to cope with the above-mentioned problem by changing the filter constant large and smoothly. That is, when the phase is locked, the average output voltage of the phase comparator and the input voltage of the voltage controlled oscillator are almost equal, and almost no current flows, so that the impedances of the two diodes are both very high. This particularly increases the time constant of the second filter provided downstream, lowers the cutoff frequency, and greatly contributes to the smoothing of the pulse component and the noise component output from the phase comparator. Next, at the time of frequency switching, since the phase comparator operates to change the frequency of the voltage controlled oscillator, a DC potential difference occurs before and after the loop filter, and one of the diodes becomes forward-biased, and the impedance decreases. This makes it possible to rapidly charge and discharge the capacitor of the second filter to realize a high-speed response of the phase locked loop.

[0009]

FIG. 1 shows an embodiment of the present invention. The output voltage of the phase comparator 1 is subjected to first-order smoothing by a first low-pass filter 20 including resistors R1 and R2 and a capacitor C1.
Next, the signal enters a second low-pass filter 21 including a circuit composed of PN junction diodes D1 and D2 connected in parallel in opposite directions and a resistor R3 and a capacitor C2 connected thereto. FIG. 3 shows an equivalent circuit when the impedance of the diode in FIG. 1 is ZD.

The input circuit of the voltage-controlled oscillator 2 to be driven is generally composed of a variable capacitance diode or the like.
DC resistance is very high. Therefore, the current passing through the diodes D1 and D2 during the phase lock is extremely small. That is, the two diodes are almost off, and the impedance ZD is very high. This means that the time constant of only the second low-pass filter provided as shown in FIG. 3 indicates that the product of the sum of the resistance R3 and the impedance ZD of the diode and the capacitor C2 (R3 + ZD) .C
2, which means that the cutoff frequency is lowered and the filter effect is enhanced. Next, at the time of frequency switching, the output voltage of the phase comparator 1 changes and the diode D1
Alternatively, if a current flows through D2 and the impedance at this time is ZD ', then ZD'<< ZD, the time constant of the second low-pass filter is reduced, and the charging and discharging of the capacitor is rapid, and a high-speed response is achieved. You. In addition, the voltage between the anode and cathode of the diode from the time of frequency switching to the transition to the locked state gradually decreases from the initial large value to almost zero, so that no shock noise is given to the loop, and the oscillation frequency is reduced. There is no shaking.

FIG. 4 shows an embodiment in which transistors Tr1 and Tr2 having collectors and bases directly connected are used instead of the diodes D1 and D2 in the embodiment shown in FIG. Therefore, the operation can achieve the same purpose as the embodiment of FIG.

FIG. 5 shows another embodiment of the present invention, in which a diode connection D between the first and second filters is provided.
1 and D2 are almost the same as those in FIG. 1, but the first low-pass filter provided before is a lag filter including a resistor R1 and a capacitor C1, and the second low-pass filter provided after is a signal having a signal. A parallel circuit of a resistor R2 and a capacitor C2 and a capacitor C3 in series therewith are connected between the path and the ground to further speed up the charging and discharging of the capacitor of the second low-pass filter at the time of frequency switching. However, the basic operation is the same as that of the embodiment of FIG. 1, and the object of the present invention can be achieved. The resistor R3 connected in parallel with the diodes D1 and D2 is inserted as an auxiliary in order to limit an excessive rise of the impedance when the diode is off. As described above, it is apparent that any type of first low-pass filter and second low-pass filter can be applied as long as the loop is stable.

FIG. 7 shows a configuration of a time-division duplex digital transceiver using the output of the frequency synthesizer according to the present invention as a local oscillation signal. The reception signal is an antenna 9, a switch SW1, a low noise amplifier 10, a reception signal. The signal is converted into a sound by a speaker 18 via a mixer 12, a reception IF amplifier 14, and a signal processing unit 17. The audio signal from the microphone 19 is transmitted from the antenna 9 via the signal processing unit 17, the transmission IF amplifier 15, the transmission mixer 13, the transmission power amplifier 11, and the switch SW1. Here, the switch SW1 performs an operation of switching between the reception signal and the transmission signal at high speed.
F and the transmission IF are different, the frequency synthesizer 16
Needs to switch the local oscillation frequency in synchronization with the switch SW1. The present invention can serve such a purpose.

[0014]

As described above, the high-speed response and signal purity of the phase-locked loop can be achieved by smoothly transitioning between the state close to the diode interruption and the forward bias state according to the phase lock and the switching. Can be achieved at the same time.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a loop filter according to the present invention.

FIG. 2 is a diagram showing connection of a general frequency synthesizer.

FIG. 3 is a diagram showing an equivalent circuit of the loop filter according to the present invention.

FIG. 4 is a diagram showing another embodiment of the loop filter according to the present invention.

FIG. 5 is a diagram showing another embodiment of the loop filter according to the present invention.

FIG. 6 is a diagram showing one embodiment of a loop filter according to the related art.

FIG. 7 is a system diagram showing a time-division duplex digital radio transceiver using a PLL synthesizer according to the present invention.

[Explanation of symbols]

D1, D2: diode, Tr1, Tr2: transistor, R1, R2, R3: resistor, C1, C2: capacitor, T1: frequency-divided signal input terminal, T2: output terminal, ZD ...
Diode impedance, SW1 antenna switch, 1 phase comparator, 2 voltage-controlled oscillator, 3 reference oscillator, 4 first divider, 5 second divider, 6 loop filter, 9 antenna , 10 low noise amplifier, 11 transmission power amplifier, 12 reception mixer, 13 transmission mixer,
14: reception IF amplifier, 15: transmission IF amplifier, 16 ...
Frequency synthesizer, 17 signal processing unit, 18 speaker, 19 microphone, 20 first low-pass filter, 21
... Second low-pass filter.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuo Akaike 3-14-20 Higashinakano, Nakano-ku, Tokyo Kokusai Denki Co., Ltd. (56) References JP-A-62-286319 (JP, A) JP-A-61 -290821 (JP, A) JP-A-61-52016 (JP, A) JP-A-50-97253 (JP, A) JP-A-63-26031 (JP, A) (58) Fields investigated (Int. . ^6, DB name) H03L 7/06 - 7/23

Claims (2)

(57) [Claims] A reference signal and an output signal of a voltage controlled oscillator;
Alternatively, a phase comparator for comparing the phase with an output signal of a frequency divider obtained by dividing the frequency, a loop filter for smoothing its output and using it as a control signal of a voltage controlled oscillator, and a voltage control whose frequency is changed by the control signal In a phase locked loop including an oscillator, the loop filter includes: a first low-pass filter including a resistor R1 and a capacitor C1; and a capacitor C3 connected in series with a resistor R2 and a capacitor C2 connected in parallel. A second low-pass filter, two diodes disposed between the first and second filters and connected in parallel with opposite polarities to each other, and connected in parallel to the two diodes, A resistor R3 for limiting an excessive rise in impedance when the diode is turned off, and when the phase is locked, the average output voltage of the phase comparator and the voltage Making the input voltages of the transmitters substantially equal, flowing very little current, making the impedances of the two diodes extremely high, and increasing the time constant of a second filter provided after the two diodes; Lowering the cutoff frequency of the second filter, smoothing the pulse component and the noise component output from the phase comparator, and at the time of frequency switching, the phase comparator changes the frequency of the voltage controlled oscillator, Causes a DC potential difference before and after, and one of the diodes becomes forward-biased, lowers the impedance formed by the two diodes, rapidly charges and discharges the capacitor of the second filter, and responds quickly to the phase locked loop. A phase-locked loop characterized by: 2. A radio transceiver, wherein an output of a frequency synthesizer using the phase locked loop according to claim 1 is used as a local oscillation signal for frequency conversion.