JP3285240B2 - Arbitration circuit for 2-port data guarantee - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit for guaranteeing 2-port data.

[0002] The write side and the read side are one data
Example of write side in system sharing registers
For example, write 16-bit data, and read
If the data is read in bytes and lower bytes,
And 16-bit data whose lower byte is different
It is necessary to perform arbitration so as not to read out. Conventionally, an arrangement having the configuration shown in FIG. 4 is provided as one provided with such an arbitration circuit for guaranteeing data. 4 is a 16-bit A port (write-side port),
FIG. 5C shows a system in which two ports of an 8-bit B port (read-side port) share one data register. In this system, an AWAIT signal for making a temporary stop request to the A port shown in FIG. The contention arbitration circuit 2 'outputs two suspension request signals including a BWAIT signal for performing a suspension request for the B port shown in FIG. 6 (c). The arbitration by these WAIT signals is based on the assumption that the temporary stop function of the microcomputer is used.

In this example, when the register write clock WT of the A port is input as shown in FIG. 5B during the reading of the B port, the contention arbitration circuit 2 'outputs a flag FLAG (FIG. 5A )), The AWAIT signal is output during the input period of the data write clock WT and until the reading of the B port is completed and the flag FLAG falls, and a temporary stop request is issued to the A port.

On the other hand, while port A is writing to data register 1, read clock RD of port B is
As shown in FIG. 6D, when the read is performed by being given to the data register 1, the contention arbitration circuit 2 '
From the rising of the flag FLAG shown in FIG.
The BWAIT signal shown in FIG. 6C is generated until the input of the write clock WT of the A port shown in FIG. Note that the read clock RD on the front side corresponds to reading of the lower byte data _DB1 ,
The read clock RD on the rear side corresponds to reading of the upper byte data _DB2 .

[0005]

When a microcomputer is used for both ports as described above, two ports are used.
Both microcomputers need to have a WAIT function, and a microcomputer without a WAIT function cannot simply be used. In addition, when one port is not a microcomputer, there is a problem that it is difficult to use the WAIT function to generate a temporary stop state.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object the purpose of defining a write port and a read port.
Write port uses one data register and writes
When reading data by dividing into upper byte and lower byte
If the upper byte and the lower byte are different bit data
Data sharing system that performs arbitration so that
It is an object of the present invention to provide an arbitration circuit of a two-port data guarantee that enables an interface independent of the WAIT function and can realize an efficient asynchronous data sharing system.

[0007]

Means for Solving the Problems The present invention, write side and
Data sharing where the reading side shares one data register
Arbitration circuit for 2-port data assurance used in existing systems
In the above, input from the read side to the data register
A flag input in synchronization with the read signal
Data write clock and reference clock
As the input signal, and the data write clock
The first flag for access detection that stores the flag
The flip-flop of
Data write clock and register write clock.
A second flip-flop for arbitration that outputs a
The output of the inverted output terminal of the first flip-flop;
The register write clock from the second flip-flop
The read side is locked based on the lock and the flag.
A gate that generates an arbitration signal for a pause request
The read signal from the read side is written.
Active before the data write clock from the
When the drive is in the
The first flip-flop by the data write clock.
The tip stores the flag and the
The output of the inverted output terminal of the first flip-flop is
Set the flip-flop to the reset state and enter the above flag.
When the force is released, the second flip-flop is reset.
Release the set state and use the reference clock to
The second flip-flop,
Register write clock to the above data register
Output to the write-side data register
The clock reads from the data register on the read side.
When it is active before the output signal
Is the data output from the second flip-flop.
Data write clock and the read side from the read side.
The above flag input together with the output signal
The output of the inverting output terminal of the first flip-flop
And outputting a signal of the temporary stop request .

[0008]

According to the present invention, a pause request signal is generated only for the read port, and it is not necessary to generate a pause request signal for the write port.
An interface independent of functions is possible, and an efficient asynchronous data sharing system can be realized.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit according to an embodiment of the present invention. A register block 1 is shared by two ports of a 16-bit A port (write-side port) and an 8-bit B port (read-side port). writes the 16-bit write data D _a for the a port register write clock RGWT, read signal and the lower / upper selection signal S
With C, the lower / upper byte data _DB1 / _DB2 is read. Here, in the present embodiment, the register write clock RGWT is created by the arbitration circuit 2 based on the data write clock WT of the A port, the reference clock, and the flag FLAG indicating reading on the B port side.

The arbitration circuit 2 includes two flip-flops F
F ₁ , FF _2, and a NAND gate ND. One flip-flop FF ₁ stores a flag FLAG from the B port (hereinafter referred to as a latch) using a data write clock WT as a clock, and outputs an inverted Q output. the output end being adapted to provide a reset signal of the flip-flop FF _2, the data write clock WT of the a port falls latches the flag fLAG, i.e. detects the flag fLAG, the writing of the a port, The reading order of the B port is detected.

[0011] The other flip-flop FF ₂ is a data write clock W for the A port by the reference clock CLK
T is latched, and the data write clock R
The data is output as a GWT. NAND gate ND is an inverted signal of the Q output of the flip-flop FF _1, a signal inverting the Q output of the flip-flop FF _2, it takes a negative logical product of the flag FLAG, temporarily the output of the B port side The stop request signal WAIT is output.

Next, the operation of this embodiment will be described with reference to the timing charts shown in FIGS. First, FIG.
As shown in the figure, the read signal RD is output and the lower byte data D _B1 and the upper byte data D are output from the data register 1.
_{When B2} is being read out in FIG.
The LAG is provided to the arbitration circuit 2 from the B port side as shown in FIG. Next, as shown in FIG.
When the port data write clock WT falls,
Since the flag FLAG is already at “H”,
Tsu flip-flop FF ₂ by the inverted Q output of the flop FF ₁
Is reset.

Therefore, the flip-flop FF ₂ has a Q output
Is "L", that is, as shown in FIG.
RGWT is set to “L”. Next, the flag FL
When AG is released and becomes “L”, flip-flop F
F ₁ is reset, whereby the inverted Q output to "H"
And the reset of flip-flop FF ₂ is released
You. However, at this time, the port A data write clock
Since the WT is already in the “H” state, the output state of the Q
State, register write clock RGWT is maintained at “L”
are doing. Then, the reference clock shown in FIG.
In CLK falling edge of the flip-flop FF ₂ is Day
Latches the “H” of the data write clock WT and outputs the Q output
Invert, that is, change the register write clock RGWT to "
H ”. This register write clock RGW
Writing data D _A from the A port at the rising edge of T is performed by the data register 1.

Next, when the port A side is
A case where reading is performed on the port side will be described. First, as shown in FIG. 3 (f), when the data write clock WT of the A port is given to the arbitration circuit 2 _first , the flip-flop FF1 is reset,
Flip-flop FF ₂ is made remains the reset state is released. The flip-flop FF ₂ latches the data write clock WT at the fall of the reference clock CLK shown in FIG. 3 (g) to output the register write clock RGWT shown in FIG. 3 (e), the data write clock WT is " Tachinobo register write clock RGWT by the latch when you return to the H "" from "L
Rising the write data D _A for the A port to the data register 1.

And a register write clock RGWT
When the signal is "L", the read signal RD is output from the B side as shown in FIG.
When the flag FLAG is input to the arbitration circuit 2 as shown in FIG. 3C, the output of "H" from the NAND gate ND of the arbitration circuit 2, that is, the WAIT signal shown in FIG. Is output to the B port side and this WAI
The reading state of the B port is stopped while the T signal is being output, that is, until the register writing is completed. And after rising register write clock RGWT, becomes WAIT signal is "H", B port is released from the pause state, the lower byte data D _B1 as shown in FIG. 3 (a), usually the upper byte data D _B2 Is read.

[0016]

Since the present invention is configured as described above, it is not necessary to generate a pause request signal only for the read port and to generate a pause request signal for the write port. Therefore, an interface independent of the WAIT function is possible, and an efficient asynchronous data sharing system can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the above operation.

FIG. 3 is a timing chart for explaining the above operation.

FIG. 4 is a circuit configuration diagram of a conventional example.

FIG. 5 is a timing chart for explaining the above operation.

FIG. 6 is a timing chart for explaining the above operation.

[Description of Signs] 1 Data register 2 Arbitration circuit FF ₁ First flip-flop FF ₂ Second flip-flop ND NAND gate WT Data write clock RGWT register write clock CLK Reference clock WAIT pause request signal RD Read signal SC Lower / upper selection signal D _A write data D _B1 lower byte data D _B2 upper byte data fLAG flag

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Claims (1)

(57) [Claims] 1. A data recording system in which a writing side and a reading side have one data record.
2 points used for data sharing system sharing
In the arbitration circuit for guaranteeing the read data, the read data input from the read side to the data register is read.
The flag which is input in synchronization with the read signal and the data write
Input signal with three signals of
And the data write clock as a clock,
First flip-flop for detecting lag and storing access
And the data write clock by the reference clock.
For arbitration to store and output register write clock
A second flip -flop, an output of an inverted output terminal of the first flip-flop,
Writing the register from the second flip-flop
The read side based on the clock and the flag
A gate that generates an arbitration signal for a pause request.
For example, the readout signal from the readout side or write side
Active before the above data write clock
Data from the writer,
The first flip-flop according to a write clock
Stores the flag and the first
The second flip-flop is output by the output of the inverting output terminal of the flip-flop.
The flip-flop is reset, and the input of the flag
When released, the second flip-flop is reset.
Release the data state and write the data
And the second flip-flop is stored.
Output a register write clock to the above data register.
And the write clock to the write-side data register is
From the read signal to the data register on the read side
When the active state is activated first, the second
The data write clock output from the flip-flop
Lock and the read signal from the read side.
And the first flip at this time.
Paused by the output of the flip-flop output terminal
An arbitration circuit for two-port data assurance, which outputs a request signal .