JP3277085B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, a liquid crystal display device, particularly a TFT as a switching element, has been used as a light-weight, thin, low-power display device.
(Thin Film Transistor) active matrix type liquid crystal display device using opportunities are increasing,
With the expansion of applications, further lower power consumption is required.

Referring to FIG. 1, the liquid crystal display device includes a liquid crystal display panel 82, a data signal line driving circuit 83, a scanning signal line driving circuit 84, a common electrode driving circuit 85, a control circuit 86, and a power supply circuit 87. It is comprised including. The liquid crystal display panel 82 is formed by sandwiching a liquid crystal layer between a pair of translucent substrates, and an electrode is provided on each translucent substrate, and display is performed by applying a voltage to a liquid crystal substance. . When a direct current is applied to the liquid crystal material, the liquid crystal material is degraded. Therefore, in a liquid crystal display device, an AC drive is generally performed. For example, by applying a voltage of the opposite polarity to each scanning signal line in the liquid crystal display panel 82 and applying a voltage of the opposite polarity to the voltage applied to the scanning signal lines to the common electrode, deterioration of display quality can be prevented. I have. LCD panel 82
Is an electrically capacitive load, and a charge / discharge current flows each time the polarity of the voltage to be charged is reversed.

FIG. 8 is a circuit diagram of a common electrode buffer circuit 36 which is a typical conventional example. The common electrode buffer circuit 36 is included in the common electrode drive circuit 85 and generates a common electrode drive signal to be supplied to the common electrode included in the liquid crystal display panel 82. The common electrode buffer circuit 36 includes transistors 40 to 43 and resistors 44 to 47. The transistors 40 and 43 are PNP transistors, and the transistors 41 and 42 are NPN transistors.

The base B of the transistor 40 and the base B of the transistor 41 are connected in common, and the conduction and cutoff of the transistors 40 and 41 are controlled via a signal line 48. The emitter E of the transistor 40 is connected to the + power supply via the resistor 44, and the collector C is connected to the-power supply. The emitter E of the transistor 41 is connected to a negative power supply via a resistor 45, and the collector C is connected to a positive power supply. The emitter E of the transistor 42 and the emitter E of the transistor 43 are connected in common, and a current is supplied to the outside through a signal line 49 as a common electrode drive signal. The base B of the transistor 42 is the transistor 4
The collector C is connected to a + power supply via a resistor 46. Base B of transistor 43
Is connected to the emitter E of the transistor 41, and the collector C is connected to the negative power supply via the resistor 47. The transistors 40 and 41 control whether the common electrode buffer circuit 36 performs charging or discharging. Resistance 4
6 and 47 prevent a current exceeding the rating from flowing through the transistors 42 and 43.

The resistors 44 and 45 are transistors 40 and 41
The base current supplied to the transistors 42 and 43 is determined according to the values of the resistors 44 and 45,
The amount of current that the common electrode buffer circuit 36 can supply is determined by the base current. In the common electrode buffer circuit 36, since the transistors 40 and 41 are transistors of different types, only one of the transistors is turned on by a control signal supplied through the signal line 48 to generate a common electrode drive signal. .

When the transistor 40 is conducting,
Transistor 41 is off. Transistor 40
Conducts, a current flows through the resistor 44, and one of the currents flows to the − power supply and the other is input to the base B of the transistor 42. Therefore, transistor 42
Is conducted, and a current input to the collector C of the transistor 42 via the resistor 46 is output from the emitter E of the transistor 42 via the signal line 49 to the outside. Also,
When the transistor 41 is on, the transistor 40 is off. When the transistor 41 conducts, a current flows from the positive power supply to the negative power supply via the transistor 41 and the resistor 45. for that reason,
The transistor 43 is turned on, and the signal line 4
9, a current flows through the transistor 43, and further flows through the transistor 43 and the resistor 47 to the negative power supply.

FIG. 9 is a timing chart showing a common electrode drive signal and a display signal superimposed. Time t
Period T91 from time 91 to time t92, period T92 from time t92 to time t93, time t93 to time t9
Periods T93 up to 4 are each one horizontal scanning period. It can be seen that the polarity of the common electrode drive signal and the display signal is inverted every period, and so-called AC drive is performed. In the period T91, the voltage difference between the common electrode drive signal and the display signal is large, and a large charge / discharge current is required. However, in the period T92, the voltage difference is small, and a small charge / discharge current is not required.

[0009]

The resistance value of the common electrode buffer circuit 36 configured as described above is determined so that the maximum current can always be supplied to the common electrode. The maximum amount of current is always supplied every time. Therefore, as described above, the maximum current amount is provided even in the case where the voltage difference between the adjacent horizontal scanning periods is small and the charging / discharging current is small, and power is wasted much.

Japanese Unexamined Utility Model Publication No. 63-191718 discloses a technique for a current amplifying circuit that changes the amount of current supplied based on a signal supplied from the outside. In the current amplifying circuit, power consumption is suppressed by selecting two current amplifying units having different operation ranges according to the level of the input alternating signal. In the current amplifier circuit, since only two current amplifiers are switched, it is not possible to cope with a fine level difference.

An object of the present invention is to provide a liquid crystal display device in which the rate of power loss is reduced and power consumption is suppressed.

[0012]

According to the present invention, a plurality of picture element electrodes arranged in a matrix, a plurality of switching elements individually connected to each picture element electrode, and a column of picture element electrodes are provided. A plurality of data signal lines to which a display signal supplied to a pixel electrode through the switching element is provided; and a scanning signal provided to each row of the pixel electrode to conduct / block the switching element. A plurality of scanning signal lines,
A liquid crystal display panel including one common electrode disposed with a liquid crystal layer interposed between the plurality of picture element electrodes; and a scanning signal line for every predetermined horizontal scanning period within a predetermined vertical scanning period. A scan signal line driving means for sequentially supplying a plurality of scan signal lines, and a display signal in which the polarity is inverted with respect to a predetermined reference potential as a center value for each horizontal scanning period based on an externally applied video signal. A data signal line driving means for supplying a display signal to each data signal line connected to the switching element to which the scanning signal is applied, and for each horizontal scanning period, inverting the polarity with a predetermined reference potential as a central value, And a common electrode driving unit that supplies a common electrode driving signal having a polarity opposite to that of the display signal to a common electrode, wherein the common electrode driving unit is supplied from outside. Current value setting means for generating and outputting a setting signal based on a video signal of one horizontal scanning period, and varying a current value supplied to the common electrode based on the setting signal provided from the current value setting means. The current value setting means, when the difference between the common electrode drive signal and the display signal is large, a large charge / discharge current flows, and when the difference is small, the small charge / discharge current The liquid crystal display device is characterized in that the setting signal is set so as to flow. Also, in the invention, it is preferable that the current value setting means sets a current value in a period delayed by one horizontal scanning period from the input of the video signal by an integration output output from an integration circuit based on the video signal. Features. Further, the present invention is characterized in that the current value setting means adjusts the amount of current supplied from the buffer circuit by using pattern data quantified by adding the digital data as the video signals.

[0013]

According to the present invention, the liquid crystal display device comprises a plurality of picture element electrodes arranged in a matrix, a plurality of switching elements individually connected to each picture element electrode, and a column of picture element electrodes. A plurality of data signal lines to which a display signal supplied to a pixel electrode via the switching element is supplied, and a scanning signal provided for each row of the pixel electrode for conducting / blocking the switching element. For a liquid crystal display panel including a plurality of supplied scanning signal lines and one common electrode disposed with a liquid crystal layer interposed between the plurality of picture element electrodes, a scanning signal line driving unit is provided in advance. Within a predetermined vertical scanning period, a scanning signal is supplied line-sequentially to a plurality of scanning signal lines for each predetermined horizontal scanning period, and the switching elements are turned on. The data signal line driving means generates a display signal in which the polarity is inverted with a predetermined reference potential as a central value for each horizontal scanning period based on an externally applied video signal, and the switching element to which the scanning signal is applied. The display signal is supplied to each of the data signal lines connected to. The common electrode driving means performs display by inverting the polarity with a predetermined reference potential as a central value every horizontal scanning period and supplying a common electrode driving signal having a polarity opposite to the display signal to the common electrode.

The common electrode drive signal is provided from a buffer circuit capable of changing a current value. The buffer circuit changes the current value based on a setting signal generated by the current value setting means based on an externally applied video signal for one horizontal scanning period. Therefore, the current value supplied from the common electrode driving means to the common electrode varies depending on the video signal in one horizontal scanning period.

[0015]

FIG. 1 is a block diagram showing the structure of a liquid crystal display device 81 according to a first embodiment of the present invention. The liquid crystal display device 81 includes a liquid crystal display panel 82, a data signal line driving circuit 83, a scanning signal line driving circuit 84, a common electrode driving circuit 85, a control circuit 86, and a power supply circuit 87. .

The liquid crystal display panel 82 is an active matrix type color liquid crystal display panel using TFTs.
This is a normally white mode liquid crystal display panel in which the screen becomes bright when no voltage is applied to the liquid crystal. The liquid crystal display panel 82 is configured by interposing a liquid crystal layer between a pair of substrate members. One of the pair of substrate members is formed of a plurality of data signal lines s1, s2, s3,..., Sm on one surface of a light-transmitting substrate made of glass, plastic, or the like. , A plurality of scanning signal lines g1, g2, g3,.
), And transistors k11, k12, k13,
, Knm (when a generic name is used, a reference symbol k is used) and a plurality of picture element electrodes Z11, Z12, Z13, ..., Znm (when a generic name is used, a reference symbol z is used).

In the vertical scanning period, the scanning signal lines g which are line-sequentially selected every horizontal scanning period are arranged in parallel at a constant interval, and the potentials based on the corresponding video signals are supplied in the horizontal scanning period. Data signal line s
Are arranged in parallel at regular intervals so as to be orthogonal to the scanning signal lines g. A transistor k, which is a switching element, is formed near the intersection of the data signal line s and the scanning signal line g. For example, the drain D of the transistor k1 is connected to the pixel electrode Z11, the gate G is connected to the scanning signal line g1, and the source S is connected to the data signal line s1. An area formed by the data signal line s and the scanning signal line g is one pixel. A red, green or blue color filter is formed in the pixel. Red-green,
Each pixel of blue forms one display unit. As described above, the alignment film is formed on one entire surface of the one substrate member on which the signal lines and the like are formed.

In the other substrate member, a common electrode is formed on one surface of a light-transmitting substrate made of glass, plastic, or the like so as to face all the pixel electrodes Z, and an alignment film covers the entire surface. I have. Each substrate member is disposed so that the alignment films face each other. In the liquid crystal display panel 82, each pixel is shown as a capacitor formed by a pixel electrode, a liquid crystal layer, and a common electrode.

The data signal line driving circuit 83 is connected to the data signal line s, and is supplied from a power supply circuit 87 by a later-described horizontal synchronizing signal HS, a clock signal CL, and a display signal supplied from the control circuit 86. The applied potential is applied to the data signal line s. During the horizontal scanning period determined by the horizontal synchronization signal HS, the clock signal CL
, A driving potential corresponding to the display signal is output to all data signal lines s.

The scanning signal line driving circuit 84 includes a scanning signal line g.
And a vertical synchronizing signal VS, which will be described later, and a horizontal synchronizing signal HS supplied from the control circuit 86.
The selection potential is applied line-sequentially to the scanning signal line g in the vertical scanning period determined by the vertical synchronization signal VS by the clock signal CL and each potential supplied from the power supply circuit 87, and the selection potential is not applied. A non-selection potential is applied to the scanning signal line g.

The common electrode drive circuit 85 includes a common electrode buffer circuit 91. Common electrode drive circuit 8
5 supplies a predetermined level of electric potential supplied from the power supply circuit 87 to the common electrode as a common electrode drive signal with inverted polarity every horizontal scanning period based on a control signal supplied from the control circuit 86. The common electrode buffer circuit 91 will be described later.

The control circuit 86 includes a display pattern discriminating circuit 9
6 is included. The control circuit 86 transmits the vertical synchronizing signal VS, the horizontal synchronizing signal HS, and the clock signal CL to the data signal line driving circuit 83 and the scanning signal line driving circuit 8, respectively.
4 and the common electrode drive circuit 85. Further, it converts an analog video signal supplied from the outside to create a display signal and supplies it to the data signal line drive circuit 83. Further, display pattern data D0, D1, D2 generated by the display pattern discriminating circuit 96 based on the video signal.
(The reference numeral D is used when collectively referred to) is supplied to the common electrode drive circuit 85. The power supply circuit 87 supplies a predetermined level of potential to each drive circuit as described above.

FIG. 2 is a circuit diagram of the common electrode buffer circuit 91 included in the common electrode driving circuit 85. The common electrode buffer circuit 91 is configured to include transistors 10 to 13, resistors 14 to 23, and switches 24 to 29.
A power supply, display pattern data D supplied from the control circuit 86, and a control signal supplied from the control circuit 86 via the signal line 30 generate a common electrode drive signal for the common electrode via the signal line 31. Variable supply of current. Assuming that the resistance values of the resistors 14 and 19 are R0, the resistance values of the resistors 15 and 20 are R1, and the resistance values of the resistors 16 and 21 are R2, the respective resistance values are determined so as to satisfy R0 <R1, R0 + R1 <R2. The transistors 10 and 13 are PNP transistors, and the transistors 11 and 12 are NPN transistors.

The base B of the transistor 10 and the base B of the transistor 11 are commonly connected, and the conduction and cutoff of the transistors 10 and 11 are controlled via the signal line 30. The resistors 14, 15, 16, 17 are connected to the emitter E of the transistor 10 in order from the + power supply side. Switches 24, 25, and 26 are provided in parallel with the resistors 14, 15, and 16, respectively. The collector C of the transistor 10 is connected to the negative power supply. The switch 24 is controlled by a signal D0, and operates by negative logic that is turned on when the signal D0 is at an L level and turned off when the signal D0 is at an H level. Similarly, switch 25 is controlled by signal D1, and switch 26 is controlled by signal D2 and operates by negative logic.

A resistor 18, 19, 20, 2 is connected to the emitter E of the transistor 11 in order from the emitter E to the -power supply side.
1 is connected. Switches 27, 28, and 29 are provided in parallel with the resistors 19, 20, and 21, respectively. The switch 27 is controlled by the display pattern data D0, and the switch 28 is controlled by the display pattern data D1.
The switch 29 is controlled by the display pattern data D2, and operates by negative logic like the switch 24.

The resistors 14 to 17 and the resistors 18 to 21 are emitter resistors of the transistors 10 and 11, and a base current to be supplied to the transistors 12 and 13 is determined according to the number of conducting resistors. The amount of current that the circuit 91 can supply is determined. In the common electrode buffer circuit 91, since the transistors 10 and 11 are transistors of different types, only one of them is turned on by the control signal generation pulse CP supplied by the signal line 30.

FIG. 3 is a block diagram showing a configuration of the display pattern determining circuit 96. Display pattern determination circuit 96
Are the integration circuits 60 to 62 and the sample hold (S /
H) Circuits 63 to 65 and A / D (analog / digital)
It is configured to include conversion circuits 66 to 68 and an adder 70. The display pattern determining circuit 96 converts the video signal into an R (red) video signal, a G (green) video signal, and a B (blue) video signal.
It is divided into video signals and processed. The R video signal is processed by the integration circuit 60, the S / H circuit 63, and the A / D conversion circuit 66. Similarly, the G video signal is supplied to the integrating circuit 61 and the S / S
Processed by the H circuit 64 and the A / D conversion circuit 67,
The B video signal is processed by the integration circuit 62, the S / H circuit 63, and the A / D conversion circuit 68.

The operation of the display pattern discriminating circuit 96 is shown in FIG.
This will be described with reference to the timing chart shown in FIG. In FIG. 4, the video signal shown in FIG. 4 (1), the integrated output shown in FIG. 4 (2), and the S / H output shown in FIG. Indicated. The video signal shown in FIG. 4A is input to the integration circuit 60 from time t0. The integration circuit 60 outputs an integration output shown in FIG. 4B based on the video signal. Time t
A period T1 from 0 to time t1 is one horizontal scanning period, and an actual video signal is input in a period T5 from time t6 to time t7.

The S / H output shown in FIG.
Are sampled by the S / H circuit 63 and held until time t1. FIG.
The S / H output shown in (3) is A / D converted by being input to the A / D conversion circuit 66, and the A / D conversion is performed as shown in FIG.
Signals RD0 to RD2 and GD0 shown in (5) and (6)
GD2, BD0 to BD2. Signals RD0, RD
1 and RD2 are at the H level. Signal R
D is input to the adder 70 together with similarly generated signals GD and BD. Each of the signals shown in FIGS. 4 (4), (5), and (6) has three similar pulses.

The adder 70 adds each signal, and outputs the upper 3 bits of the result as shown in FIGS.
Output as the display pattern data D0, D1, D2 shown in (9). The display pattern data D is input to the corresponding one of the switches 27 to 29 during a period T2 from time t1 to time t2 which is delayed by one horizontal scanning period from the input of the video signal. Actually, when the data signal line s is driven by the data signal line driving circuit 83, a display signal obtained by inverting the level of the video signal shown in FIG. 4A is used. Time t, which is one horizontal scanning period
On the basis of the video signal shown in the period T1 from 0 to time t1 and the period T2 from time t1 to time t2 having the same length, whitish display is performed on the liquid crystal display panel 82. Since the display panel 82 is a normally white liquid crystal display panel, little voltage is applied to the data signal line s in order to perform whitish display. Further, the screen display becomes dark based on the video signal shown in the period T3 from time t2 to time t3, and the screen display becomes an intermediate brightness based on the video signal shown in the period T4 from time t3 to time t4. .

In accordance with the video signal inputted in the period T3, the voltage of the integrated output in the period becomes low, so that the S / H output becomes low, and all the signals after A / D conversion become L level. I have. As a result of adding these signals, the display pattern data D output in the period T4 is all at L level. Further, in the period T4, the input video signal is a signal for setting the screen to an intermediate brightness, so that the S / H output becomes a medium voltage,
The signals RD0 and RD are converted by A / D conversion.
1 goes high, and the signal RD2 goes low.
The display pattern data D, which is the result of adding each signal,
The display pattern data D0 and D1 go high, the display pattern data D2 goes low, and are output after time t4.

FIG. 5 is a timing chart including signals input to the common electrode buffer circuit 91. FIG.
The control signal shown in (1) becomes H level during a period T21 from time t21 to time t22, becomes L level during a period T22 from time t22 to time t23,
23 during the period T23 from time t24 to time t24, and becomes L during the period T24 from time t24 to time t25.
The level and the H level and the L level are alternately taken for each horizontal scanning period, and the transistors 10 and 11 shown in FIG. 2 are turned on alternately. The display pattern data D0, D1, and D2 shown in FIGS. 5 (2), (3), and (4) are signals output from the display pattern determination circuit 96 from time t0 to time t5 in FIG. By inputting the control signal and the display pattern data D to the common electrode buffer circuit 91, the common electrode signal shown in FIG. 5 (5) is created. The display signal shown in FIG. 5 (6) is a signal obtained by inverting the video signal shown in FIG. 4 (1).

Considering that the common electrode signal and the display signal are superimposed on each other, a large charge / discharge current flows when the difference between the signals is large. However, in the periods T21 and T22, the difference between the signals is small, so The difference between the charged AC voltages is small, and the charge / discharge current is small. The display pattern data based on the video signals are all at the H level,
4 to 29 are all open. Therefore, the base current to the transistors 12 and 13 that determines the amount of current supplied from the common electrode buffer circuit 91 is suppressed, and the amount of current supplied from the common electrode buffer circuit 91 decreases.

In the period T23, the difference between the signals is large, and a large charge / discharge current is required. The display pattern data D determined based on the video signal is all at L level, the switches 24 to 29 are all closed, the base current to the transistors 12 and 13 is increased, and the current supplied from the common electrode buffer circuit 91 is increased. The amount increases.

In the period T24, the difference between the signals is medium, and the charge / discharge current is not required as much as in the period T23. Therefore, the display pattern data D is as shown in FIG.
The display pattern data D0 and D1 shown in (3) become H level, the display pattern data D2 becomes L level, the switches 24, 25, 27 and 28 are opened, and the switch 2
6, 29 are closed. At this time, the amount of current supplied from the common electrode buffer circuit 91 is determined by the base current flowing to the transistors 12 and 13.

As described above, according to the present embodiment, the amount of current supplied to the common electrode is changed based on a video signal for performing video display. When the voltage difference is large, a large charge / discharge current is supplied, and when the AC voltage difference is small, the amount of the charge / discharge current is suppressed. And the power consumption of the entire liquid crystal display device 81 can be suppressed.

A liquid crystal display device 9 according to a second embodiment of the present invention.
In No. 9, since the video signal supplied to display on the liquid crystal display panel 82 is digital data, the first
An adder 76 shown in FIG. 6 is provided instead of the display pattern determination circuit 96 shown in the embodiment. Liquid crystal display 9
In FIG. 9, the same components as those of the liquid crystal display device 81 shown in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The adder 76 receives digital signals RD0-RD2, GD0-GD2, which are digital data, respectively.
BD0 to BD2 are added and quantified, and the upper 3 bits are output as display pattern data D2, D1, D0 in order from the most significant bit.

In this embodiment, the video signal is composed of 3-bit data for each pixel of the corresponding color, the R video signal is the signals RD0, RD1, RD2, the G video signal is the signals GD0, GD1, GD2, B The video signal is signal BD0,
It is composed of BD1 and BD2.

FIG. 7 is a timing chart of each signal in the adder 76. In FIG. 7, the R video signal,
The G video signal and the B video signal are described as the same signal. Based on each signal shown in a period T41 from time t41 to time t42, which is one horizontal scanning period, and a period T42 from time t42 to time t43, which has the same length, the liquid crystal display panel 82 has a whitish display. Is performed, and since the liquid crystal display panel 82 is a normally white liquid crystal display panel, a small voltage is applied to the data signal line s in order to perform whitish display. Further, based on each signal shown in the period T43 from the time t43 to the time t44, the screen display becomes dark and the time t44
The screen display has an intermediate brightness based on each signal shown in a period T44 from to time t45. The signals RD0, GD0, BD0 shown in FIG. 7A, the signals RD1, GD1, BD1 shown in FIG. 7B, and the signal R shown in FIG.
D2, GD2, and BD2 are input to the adder 76 and added together, and in each horizontal scanning period, FIGS. 7 (4), (5), and (6).
Are output as display pattern data D0, D1, and D2, respectively. The display pattern data D based on each signal input in the period T41 is output in the period T42.

In the periods T41 and T42, as a result of adding the signals, the display pattern data D output in the periods T42 and T43 are both at the H level.
Therefore, the switches 24 to 29 in the common electrode buffer circuit 91 are all turned off. In the period T43, the display pattern data D0, D1, and D2 output in the period T44 based on each input signal are all at the L level, and therefore, the switches 24 to 29 in the common electrode buffer circuit 91 are all turned on. Become.
Based on the data input in the period T44, the display pattern data D0 and D1 go to the H level and the display pattern data D2 goes to the L level in the period T45 from the time t45 to the time t46.
5 or the switches 27 and 28 are turned off, and the switch 26 or the switch 29 is turned on.

As described above, according to the present embodiment, in the common electrode driving circuit 85 which drives the common electrode by inverting the polarity every horizontal scanning period, the output from the adder 76 is based on the digital video signal. Since the amount of current supplied from the common electrode buffer circuit 91 is adjusted by the displayed display pattern data D, the amount of current supplied from the common electrode driving circuit 85 to the common electrode is adjusted to the image in one horizontal scanning period. The change can be made based on the signal, the waste of power consumption in the common electrode buffer circuit 91 can be reduced, and the power consumption in the liquid crystal display device 99 can be suppressed.

In each of the embodiments, a normally white liquid crystal display panel is used as the liquid crystal display panel 82. However, when a normally black liquid crystal display panel is used, the switch of the buffer circuit 91 for the common electrode is used. The same effect as that of the present embodiment can be obtained by operating the operation logics 24 to 29 with positive logic.

[0044]

As described above, according to the present invention, in the common electrode driving means for driving the common electrode by inverting the polarity every horizontal scanning period, the buffer circuit is provided based on the video signal in one horizontal scanning period. Since the amount of current supplied to the common electrode from is adjusted, the waste of power consumption in the buffer circuit of the common electrode driving means can be reduced, and the power consumption in the liquid crystal display device can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device 81 according to a first embodiment of the present invention.

2 is a circuit diagram of a common electrode buffer circuit 91 included in a common electrode driving circuit 85. FIG.

FIG. 3 is a block diagram illustrating a configuration of a display pattern determination circuit 96.

FIG. 4 is a timing chart of each signal in a display pattern determination circuit 96.

FIG. 5 is a timing chart including a signal input to the common electrode buffer circuit 91;

FIG. 6 is a block diagram of an adder included in a liquid crystal display device according to a second embodiment of the present invention.

7 is a timing chart of each signal in the adder 76. FIG.

FIG. 8 is a circuit diagram of a common electrode buffer circuit 36 which is a typical conventional example.

FIG. 9 is a timing chart showing a common electrode drive signal and a display signal superimposed.

[Explanation of symbols]

 81, 99 Liquid crystal display device 82 Liquid crystal display panel 83 Data signal line drive circuit 84 Scanning signal line drive circuit 85 Common electrode drive circuit 86 Control circuit 87 Power supply circuit 91 Common electrode buffer circuit 96 Display pattern determination circuit

Claims (3)

(57) [Claims] 1. A plurality of picture element electrodes arranged in a matrix,
A plurality of switching elements individually connected to each pixel electrode; and a plurality of data signal lines provided for each column of the pixel electrodes and supplied with display signals supplied to the pixel electrodes via the switching elements. Is provided for each row of the pixel electrode,
A liquid crystal display panel comprising: a plurality of scanning signal lines to which a scanning signal for turning on / off the switching element is supplied; and one common electrode disposed with a liquid crystal layer interposed between the plurality of picture element electrodes. A scanning signal line driving means for supplying a scanning signal line-sequentially to a plurality of scanning signal lines in a predetermined vertical scanning period within a predetermined vertical scanning period, and a horizontal scanning based on an externally supplied video signal. Data signal line driving means for generating a display signal in which the polarity is inverted with a predetermined reference potential as a central value for each period, and supplying the display signal to each of the data signal lines connected to the switching element to which the scanning signal is applied. A common electrode for inverting the polarity with a predetermined reference potential as the center value and supplying a common electrode drive signal having a polarity opposite to the display signal to the common electrode for each horizontal scanning period. A liquid crystal display device comprising: a current value setting means for generating and outputting a setting signal based on an externally applied video signal for one horizontal scanning period; A buffer circuit that varies a current value to be supplied to the common electrode based on the setting signal given by the means, wherein the current value setting means is configured to output a signal when a difference between the common electrode drive signal and the display signal is large. The liquid crystal display device is characterized in that the setting signal is set so that a large charge / discharge current flows and, when the difference is small, a small charge / discharge current flows. 2. The method according to claim 1, wherein the current value setting means sets a current value in a period delayed by one horizontal scanning period from the input of the video signal by an integrated output output from an integration circuit based on the video signal. 2. The liquid crystal display device according to claim 1, wherein: 3. The current value setting means adjusts an amount of current supplied from the buffer circuit according to pattern data quantified by adding digital data as the video signals. The liquid crystal display device as described in the above.