JP3274563B2 - Image playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a discrete cosine transform (D
The present invention relates to an apparatus that reproduces an image code that has been compression-encoded by an encoding method (such as JPEG or MPEG) based on CT (hereinafter, referred to as DCT).

[0002]

2. Description of the Related Art When an image is digitized and recorded on a recording medium such as a CD-ROM or a hard disk, the data amount is enormous, so that it is usually recorded by compression encoding.

[0003] There is an encoding method based on DCT which is often used in the compression encoding method.
PEG (Joint Photographic Ex)
Part Group) or MPEG (Moving P
This is adopted in an encoding system which is an international standard such as the “Ictories Expert Group”.

[0004] Reproduction of an image code according to a conventional DCT-based coding method will be described with reference to the drawings using MPEG as an example. FIG. 16 is a view for explaining reproduction of an image code conforming to MPEG. As shown in FIG. 16, the code is read, and the header analysis 201 analyzes the type of the code. In MPEG, an I picture which is an intra-frame code, a P picture which is an inter-frame code only in the forward direction,
It is divided into three types of B pictures, which are front and rear bidirectional interframe codes.

[0005] In the case of an I picture, a variable length Huffman code that has been highly efficiently compressed by the VLD 202 is decoded, and Q- ¹
3, the image data is decompressed, the IDCT 204 calculates the pixel values of the block by the inverse DCT process, and the image is expanded.

In the case of a P picture, the picture is decoded by the VLD 202, dequantized by the Q ^-1 203, and
Then, the difference value of the block is calculated by the inverse DCT process, and the difference value is added to the motion-compensated block of the previous frame stored in the previous frame 205 by the previous prediction 207 to expand the image.

In the case of a B picture, the picture is decoded by the VLD 202, dequantized by Q ^-1 203, and
Calculates the difference value of the block by the inverse DCT process, and calculates the previous frame 205 by the two predictions 208 or the rear prediction 209.
The image is decompressed by adding a difference value to the motion-compensated block of the previous frame and the motion-compensated block of the subsequent frame stored in the subsequent frame 206.

[0008] As described above, any apparatus can reproduce the MPEG code if it is a reproducer based on the international standard MPEG. However, processing such as inverse DCT and VLD imposes a heavy burden on the CPU, and high-speed reproduction cannot be performed without a high-speed CPU. For example, JPEG or MPEG
In order to perform the processing of 15 frames / second by a reproducing apparatus such as the above, it is necessary to perform the reproducing processing of one frame in about 66 milliseconds. If it takes 30 ms to decode the Huffman code, 10 ms to dequantize, 20 ms to inverse DCT, and 20 ms to display, it takes 80 ms to process the whole. It takes 14 milliseconds to reproduce an image of one frame.

Therefore, in order to reduce the load on the CPU, a part of the encoding method is changed to calculate the difference between neighboring pixels instead of the DCT calculation, omit the quantization, and replace the variable-length code with a 4-bit code. It is conceivable that high-speed reproduction can be performed even by a low-speed CPU by performing encoding using a bit unit code.

As this conventional example, Japanese Patent Application Laid-Open No. 63-95791 is known.
However, in this method, CP is obtained by distributing variable-length data so that the data lengths of blocks are equal.
U can be played without burden.

In Japanese Patent Application Laid-Open No. 4-56492, when the coefficients of one block after DCT conversion are all 0, the block is regarded as an invalid block and only the information indicating the invalid block is transmitted as a separate signal, thereby reducing the processing amount. ing.

In order to reduce the load on the CPU,
A method of controlling the amount of compression code at the time of encoding is also conceivable. As a conventional example, there is JP-A-4-329089. In this method, code amount control is performed according to the information amount of each block divided into small areas in a frame, and the code amount and the step size assigned to each block are controlled. Is set to an optimal state, thereby controlling the code amount.

[0013]

However, in the above-mentioned image compression in which a part of the encoding system is changed, compatibility with the international standard encoding system cannot be obtained, so that a dedicated reproducing device is required. There is.

Further, in image compression for controlling the amount of compression code, it is necessary to repeat compression a plurality of times, so that it takes time to create a compression code. Also, since the code amount control is not performed in accordance with the processing capability of the reproducing device, a reproducing device having a low processing speed cannot perform real-time reproduction. Further, since the compression code amount is determined, there is a problem that even a high-speed reproducing device can reproduce only a code having a predetermined image quality.

An object of the present invention is to provide an image reproducing apparatus and an image reproducing method which can reproduce DCT-based codes at a high speed with a simple configuration without impairing the image quality as much as possible according to the capability of the reproducing apparatus. Is to provide.

[0016]

According to the present invention, an image is divided into small blocks, a discrete cosine transform is performed for each block, and the result of the transform is quantized to obtain a highly efficient encoded frame. Generates a code, divides the image into small blocks, and performs motion compensation by searching for the block that minimizes the difference between the current frame and the frames before and after it for each block, and performs motion compensation with the block of the current frame. The difference between the blocks of the frame is taken, the discrete cosine transform is performed on the difference block, the transform result is quantized to generate a highly efficient coded inter-frame code , and the intra-frame code is generated.
In an image playback device that plays back a moving image that has been compression- encoded with an inter-frame code , the code is analyzed to determine whether or not the code has fixed parameters, and the parameters are fixed.
If the code is the same, an image reproducing apparatus having means for performing high-speed reproduction is obtained.

Further, according to the present invention, a high-speed reproduction
In this case, an image reproducing apparatus having means for enlarging and displaying a reproduced image is obtained.

According to the present invention, there is further provided an image reproducing apparatus having means for performing an expansion process using only an I picture which is an intra-frame code in the case of high-speed reproduction. .

Further, according to the present invention, the slice width of an I-picture which is an intra-frame code at the time of high-speed reproduction is further improved.
An image reproducing apparatus having means for performing a decompression process in which is fixed .

According to the present invention, there is further provided an image reproducing apparatus for calculating an inverse discrete cosine transform by regarding a specific high-frequency component in a block as 0 in the case of high-speed reproduction. Is obtained.

Further, according to the present invention, a high-speed reproduction
In this case, an image reproducing apparatus having means for decoding only a fixed-length code is obtained.

Further, according to the present invention, it is possible to obtain an image reproducing apparatus in which the above-mentioned units are combined.

[0023]

According to the present invention, high-speed reproduction can be performed without impairing the image quality as much as possible in accordance with the processing capacity of the reproducing apparatus. Also,
Since it is compatible with the international standard encoding method, no special playback device is required.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a block diagram of an image reproducing apparatus showing one embodiment of the present invention. 1 includes a header analysis 111, a VLD 112, a Q ^-1 113, and an inverse DC.
It comprises T114, previous frame 115, rear frame 116, front prediction 117, both predictions 118 and rear prediction 119. The header analysis 111 is a sequence header analysis 1
24, GOP header analysis 125, and picture header analysis 1
26 and a slice header analysis 127. The image reproducing device reads the code and performs header analysis 111.
At that time, it is determined whether the code is a code with a fixed parameter, and if so, high-speed reproduction is performed. In the case of high-speed reproduction, only the I picture, the fixed slice width, and the escape code are regarded as the only codes, and the VLD2 (120) decodes the code that has been subjected to high-efficiency compression, inversely quantizes it with Q2 ^-1 121, and performs inverse DCT2 ( At 122), an inverse DCT is performed, and the image to be reproduced is enlarged and displayed at 123. In the case of non-high-speed reproduction, three types of codes are decompressed: an I picture which is an intra-frame code, a P picture which is an inter-frame code only in the forward direction, and a B picture which is a bi-directional inter-frame code.

In the case of an I picture, the picture is decoded by the VLD 112, dequantized by the Q ⁻¹ 113, and inverted by the inverse DCT 114.
The value of the pixel of the block is calculated by the CT process, and the image is expanded.

In the case of a P picture, the picture is decoded by the VLD 112, dequantized by the Q ^-1 113, and
Then, the difference value of the block is calculated by the inverse DCT process, and the difference value is added to the motion-compensated block of the previous frame stored in the previous frame 115 by the previous prediction 117 to expand the image.

In the case of a B picture, the picture is decoded by the VLD 112, dequantized by the Q ^-1 113, and
Calculates the difference value of the block by the inverse DCT processing, and calculates the difference between the previous frame 115 and the
Then, the difference value is added to the motion-compensated block of the previous frame and the motion-compensated block of the subsequent frame stored in the subsequent frame 116, and the image is expanded.

FIG. 2 shows a hierarchical diagram of a code format conforming to MPEG. MPEG codes have several hierarchical structures as shown in FIG. The top layer is a video sequence, and includes a plurality of GOPs (Grou).
p Of Picture). The GOP is composed of a plurality of pictures, and one picture indicates one image. A picture is composed of a plurality of slices divided into arbitrary regions. A slice is composed of a plurality of macroblocks arranged in left-to-right or top-to-bottom order. The micro block is a luminance component (Y1, Y2, Y3, Y4) obtained by further dividing the 16 × 16 dot block into 8 × 8 dot blocks, and a color difference component (C) of an 8 × 8 dot block in an area matching the luminance component.
b, Cr). An 8 × 8 dot block is the minimum unit of encoding.

FIG. 3 shows a configuration diagram of a code format conforming to MPEG. As shown in FIG. 3, the MPEG code includes (1) a sequence header and (2) G
An OP (Group Of Picture) header,
(3) picture header, (4) slice header,
It consists of (5) a macro block header and (6) a code of a block.

UserData is included in the sequence header.
As shown in (11), there is a user data area that can be freely defined by the user, and a flag indicating that the parameter is fixed is stored in that area. The user data (1
1) is composed of an identifier “Custom” (12) indicating a code compressed with a fixed parameter and a fixed parameter flag (13). The fixed parameter flag (13) includes a bit indicating that the data is expanded upon decompression,
A bit indicating that only the I picture is fixed, a bit indicating that the slice width is fixed at the picture size, a bit indicating that high frequency components are cut,
Consists of bits indicating that only the escape code is fixed.

Next, an image reproducing process in the image reproducing apparatus of the present embodiment having the above configuration will be described.

FIG. 4 is a diagram for explaining the enlargement of the image reproducing apparatus. FIG. 4 shows an example in which an image of 2 × 2 pixels is enlarged twice vertically and twice horizontally. FIG. 4A shows the value of each pixel of 2 × 2 pixels, and FIG. 4C shows the value of each pixel of 4 × 4 pixels after being enlarged twice vertically and twice horizontally. FIG.
(B) shows a process of converting one pixel into four pixels. In the example of FIG. 4, one pixel is taken out from (A) and converted into four pixels as shown in (B), which is twice as long and two times as wide.
The image is written on the image (C) that is enlarged twice. For example,
The pixel (29) at the upper right of (A) is converted to P
1 (29), P2 (29), P3 (29) and P4 (2
9), and the data is written in the corresponding area of (C).

In the example shown in FIG. 4, the pixel value is not corrected (desired) in order to improve the image quality when the image is enlarged twice vertically and twice horizontally, but the dithering process may be performed. In this case, for example, in FIG. 4B, P1 = P0 + a, P2 =
P0 + b, P3 = P0 + c, P4 = P0 + d (a, b,
(c and d are arbitrary integers), and 4 times magnification is performed. Also,
The magnification is twice as high and twice as wide, but may be an integer multiple of 3 or more.

FIG. 5 is a flowchart for explaining the operation of FIG. As shown in FIG. 5, the enlargement is performed by reading one pixel from the image before the enlargement (step 1), and replacing the read one pixel (P0) with four pixels (P1 = P0, P2 =
P0, P3 = P0, P4 = P0) are converted (step 2), and the converted four pixels are written in the enlarged image (step 3). Next, it is determined whether or not all the pixels have been processed (step 4). If not, the process returns to step 1; otherwise, the process ends.

By expanding and displaying the image thus expanded, the expansion time can be reduced. For example, vertical 2
When the magnification is doubled and doubled horizontally, the extension time can be reduced to 1/4.

Most of the enlargement processing is memory read / write. Decompression processing includes not only read / write of a memory, but also multiplication by inverse DCT or inverse quantization, and bit shift processing by decoding variable-length code. Since the read / write of the memory has a smaller load on the CPU than the multiplication and the bit shift, even when the enlargement processing is included, the processing can be performed at a higher speed when the enlargement is performed than when the enlargement is not performed.

FIG. 6 is a view for explaining processing when the picture configuration is fixed. In MPEG, there are three pictures: an I picture (intra-frame code), a P picture (forward prediction code), and a B picture (bidirectional prediction code). FIG. 6A shows an I picture, a P picture, and a B picture. (B) shows a picture configuration fixed to only I pictures. In the case of a P picture, it is necessary to perform pre-prediction with reference to the picture of the previous picture,
Further, in the case of a B picture, it is necessary to perform post-prediction or both predictions with reference to the image of the previous frame or the image of the subsequent frame, so that it takes longer processing time than in the case of an I picture. FIG.
In the example of (A), the first frame is an I picture and there is no reference frame. The second frame and the second frame are B pictures, and post-prediction or both predictions are performed with reference to the image of the first frame as the previous frame and the image of the fourth frame as the subsequent frame. Four frames are P-pictures, and pre-prediction is performed with reference to the image of the first frame which is the previous frame. In the example of FIG. 6B, since all the first to fourth frames are I-pictures, there is no need to perform pre-prediction, post-prediction, or both predictions.

FIG. 7 is a flowchart for explaining the operation of FIG. FIG. 7A shows a case of processing a picture configuration consisting of an I picture, a P picture, and a B picture, FIG. 7B shows a case of processing a picture configuration fixed to only an I picture, and FIG. The processing for determining which of A) and (B) is to be processed is shown. In picture processing 1 shown in FIG. 7A, the picture type is read from the picture header (step 10), the picture type is determined (step 11), and in the case of an I picture, the I picture is processed (step 10). Step 12). If the picture is a P picture, the P picture is processed (step 13). B
In the case of a picture, processing of a B picture is performed (step 1).
3). Picture processing 2 shown in FIG. 7B performs processing of an I picture (step 15). In the picture header analysis shown in FIG. 7C, it is determined whether or not the parameters are fixed (step 16). If not, picture processing 1 is performed (step 17). If so, picture processing 2 is performed (step 18).

By fixing the picture structure to only I-pictures in this way, it is possible to omit the process of reading and determining the picture type from the picture header, and to perform the pre-prediction of P-picture processing, the post-prediction of B-picture processing, and the like. Since both predictions can be omitted, processing can be performed at high speed.

FIG. 8 is a diagram for explaining the processing when the slice width is fixed. In MPEG, one frame of image is
It is divided into several areas in units of 6 × 16 pixels. A slice header is inserted at the head of the code of the divided area to indicate which area of the image is. FIG.
8A shows a case where the slice width is not fixed, and FIG. 8B shows a case where the slice width is fixed to the picture size. FIG. 8A shows an image in five regions (1).
To 5). A slice header is inserted at the head of the code of each area from 1 to 5. In FIG. 8B, since the slice width is fixed to the picture size, the area is not divided. Therefore, there is only one slice header.

FIG. 9 is a flowchart for explaining the operation of FIG. 9A shows a process when the slice width is not fixed, FIG. 9B shows a process when the slice width is fixed to the picture size, and FIG. 9C shows a process when the slice width is fixed.
And (B) to determine which one to process. In the slice processing 1 shown in FIG. 9A, a slice header is read (step 20), a macroblock is processed (step 21), and it is determined whether or not the next header is a slice header (step 22). If so, return to step 20. If not, it is determined whether or not the processing for all macroblocks has been completed (step 23). If not, the process returns to step 21, and if so, the processing is terminated. Slice processing 2 shown in FIG. 9B reads the slice header (step 2).
4) Perform processing of the macroblock (step 25),
It is determined whether or not the processing of all macroblocks has been completed (step 26). If not, the process returns to step 24, and if so, the process ends. In the slice header analysis shown in FIG. 9C, it is determined whether or not the parameters are fixed (step 27). If not, slice processing 1 is performed (step 28). If so, slice processing 2 is performed (step 29).

By fixing the slice width to the picture size in this way, the number of processes for reading and analyzing the slice header can be reduced, so that high-speed processing can be performed.

FIG. 10 shows the inverse DC
It is a figure explaining the processing at the time of performing T. FIG. 10A shows a case where the high-frequency component is not regarded as 0, and FIG.
(B) of 0 indicates a case where the high frequency component is regarded as 0. FIG. 10A shows a scan order (low-frequency to high-frequency) of frequency components of 8 × 8 blocks (zigzag scan).
Is shown. FIG. 10B also shows a zigzag scan, in which all high-frequency components after the 22nd are regarded as zero. In the case of a natural image, image information concentrates on low-frequency components, so that even if high-frequency components are regarded as 0, the image quality does not significantly deteriorate and cannot be seen.

FIG. 11 is a flowchart for explaining the operation in the case where the inverse DCT is performed without regarding the high-frequency component as 0. The inverse DCT shown in FIG. 11 stores 0 in a variable y (step 30) and stores 0 in a variable v (step 3).
1) 0 is stored in a variable dd (step 32), and 0 is stored in a variable u (step 33). Next, a buffer of an 8 × 8 block buffer that performs inverse DCT on the variable dd
(Y, u) and the coefficient of the inverse DCT, cos ((2v +
1) The product of uπ) / 2 is added (step 34). Next, 1 is added to the variable u (step 35), and it is determined whether or not the value of the variable u is smaller than 8 (step 36). If so, the process returns to step 34. Otherwise, the value of the variable dd is stored in t (v, y) of the temporary storage buffer (step 37). Next, 1 is added to the variable v (step 38), and it is determined whether or not the value of the variable v is smaller than 8 (step 39). If so, the process returns to step 32. Next, 1 is added to the variable y (step 4
0), it is determined whether the value of the variable y is smaller than 8 (step 41), and if so, the process returns to step 31.
Otherwise, 0 is stored in the variable y (step 4).
2). Next, 0 is stored in the variable x (step 43), 0 is stored in the variable dd (step 44), and 0 is stored in the variable u (step 45). Next, t (y,
u) and the product of cos ((2x + 1) uπ) / 2 are added (step 46). Next, 1 is added to the variable u (step 47), and it is determined whether or not the value of the variable u is smaller than 8 (step 48). If so, the process returns to step 46. Otherwise, the variable d is added to Buffer (x, y).
The value of d is stored (step 49), then 1 is added to the variable x (step 50), and it is determined whether or not the value of the variable x is smaller than 8 (step 51). Return to 44. Next, 1 is added to the variable y (step 52), and it is determined whether or not the value of the variable y is smaller than 8 (step 53). If so, the process returns to step 44. If not, the process ends.

FIG. 12 is a flowchart for explaining the operation in the case where the inverse DCT is performed with the high-frequency component regarded as 0. FIG. 12 is an example in which the 22nd and subsequent frequency components are regarded as 0. The inverse DCT2 shown in FIG. 12 stores 0 as a variable y (step 60). 0 is stored in the variable v (step 61), and 0 is stored in the variable dd (step 6).
2) 0 is stored in the variable u (step 63). Next, the buffer B of the 8 × 8 block that performs the inverse DCT on the variable dd
uffer (y, u) and the inverse DCT coefficient cos
Add the product of ((2v + 1) uπ) / 2 (step 6
4). Next, 1 is added to the variable u (step 65), and it is determined whether or not the value of the variable u is smaller than the value of umax (y) (step 66).
Return to Otherwise, the temporary storage buffer t
The value of the variable dd is stored in (v, y) (Step 6)
7). Next, 1 is added to the variable v (step 68), and it is determined whether or not the value of the variable v is smaller than 8 (step 6).
9) If yes, return to step 62. Next, 1 is added to the variable y (step 70), and it is determined whether or not the value of the variable y is smaller than 6 (step 71). If so, the process returns to step 61. Otherwise the variable y
Is stored in step (step 72). Next, 0 is stored in the variable x (step 73), 0 is stored in the variable dd (step 74), and 0 is stored in the variable u (step 7).
5). Next, t (y, u) and cos ((2x +
1) The product of uπ) / 2 is added (step 76). Next, 1 is added to the variable u (step 77), it is determined whether the value of the variable u is smaller than 6 (step 78), and if so, the process returns to step 76. Otherwise, B
The value of the variable dd is stored in buffer (x, y) (step 79). Next, 1 is added to the variable x (step 8
0), it is determined whether the value of the variable x is smaller than 8 (step 81), and if so, the process returns to step 74.
Next, 1 is added to the variable y (step 82), and it is determined whether or not the value of the variable y is smaller than 8 (step 83).
If so, return to step 74. If not, the process ends.

In the example shown in FIG. 12, the 22nd and subsequent bits are regarded as 0, but a value of 1 to 64 may be used according to the processing capacity of the reproducing apparatus.

As described above, the number of multiplications when the high-frequency component is not regarded as 0 is 8 × 8 × 8 × 2 = 1024, and 2
When the second and subsequent frequency components are regarded as 0, the number of multiplications is 8 × (6 + 5 + 4 + 3 + 2 + 1) × 6 + 6 × 8 × 8 =
510 times, the high frequency component is regarded as 0, and the inverse DC
Performing T allows faster processing.

FIG. 13 is a configuration diagram of the escape code.
MPEG has a fixed bit length escape code, which is (1) a code (00) indicating that it is an escape code.
0001), (2) run length (number of invalid coefficients), and (3) level (effective coefficient value: -128 to +128).

FIG. 14 is a table showing examples of ordinary codes and escape codes. As shown in FIG.
The escape code is a variable-length code of up to 17 bits, but all escape codes are fixed-length codes of 20 bits.

FIG. 15 is a flowchart for explaining the operation of the VLD. FIG. 15A shows a process in the case of a normal code, and FIG. 15B shows a process in a case where only an escape code is fixed. The VLD shown in FIG. 15A takes out 8 bits of the code (step 9).
0), the type of code is determined from the 8-bit value (step 91), and it is determined whether the code is 8 bits or less (step 92). If not, the process proceeds to step 94. If not, the necessary number of bits are further extracted (step 93), the number of bits of the code is added to the pointer of the code buffer (step 94), and the run length and level corresponding to the code are extracted (step 95). , The run length and the level are returned (step 96). VLD2 shown in FIG. 15B takes out 8 bits of the code (step 9).
7), the level is extracted from bit0 to bit7 (step 98), the run length is extracted from bit8 to bit13 (step 99), 20 bits are added to the pointer of the code buffer (step 100), and the run length and level are returned. (Step 101).

As described above, in the case of a normal code, it is necessary to check the number of code bits, and to perform processing according to the value. However, in the case of an escape code only, since the fixed length is 20 bits, it is necessary to check the number of code bits. And can be processed at high speed.

[0052]

As described above, according to the present invention, since the parameters can be expanded while the parameters are fixed, high-speed reproduction can be performed without impairing the image quality as much as possible according to the processing power of the reproducing machine. In addition, since it is compatible with an encoding system which is an international standard, a dedicated reproducing device is not required.

[Brief description of the drawings]

FIG. 1 is a flowchart of a moving image reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a hierarchy diagram of MPEG codes.

FIG. 3 is a configuration diagram of an MPEG code.

FIG. 4 is a diagram illustrating an enlargement process according to the present invention.

FIG. 5 is a flowchart illustrating an operation of an enlargement process according to the present invention.

FIG. 6 is a diagram illustrating a process of fixing a picture configuration according to the present invention.

FIG. 7 is a flowchart showing an operation of picture processing according to the present invention.

FIG. 8 is a diagram for explaining processing in which the slice width is fixed according to the present invention.

FIG. 9 is a flowchart showing the operation of the slice processing of the present invention.

FIG. 10 is a diagram illustrating a process of the present invention in which a high-frequency component is regarded as 0.

FIG. 11 is a flowchart showing the operation of the inverse DCT.

FIG. 12 is a flowchart showing the operation of the inverse DCT of the present invention.

FIG. 13 is a configuration diagram of an escape code.

FIG. 14 is a table showing examples of ordinary codes and escape codes.

FIG. 15 is a flowchart showing the operation of the VLD of the present invention.

FIG. 16 is a flowchart of a conventional moving image reproducing apparatus.

[Explanation of symbols]

111 header analysis 112 VLD 113 Q- ¹ 114 inverse DCT 115 previous frame 116 rear frame 117 pre-prediction 118 bi-prediction 119 post-prediction 120 VLD2 121 Q2 ^-1 122 reverse DCT2 123 enlargement 124 sequence header analysis 125 GOP header analysis 126 picture header analysis 127 Slice header analysis

Claims (6)

(57) [Claims] 1. An image is divided into small blocks, a discrete cosine transform is performed for each block, and the result of the transform is quantized to generate a highly efficient coded intra-frame code. By dividing, for each block, motion compensation is performed by searching for a block having the smallest difference between the current frame and the frames before and after the current frame, and taking the difference between the block of the current frame and the block of the motion-compensated frame, A discrete cosine transform is performed on the difference block, the result of the transform is quantized, a high-efficiency coded inter-frame code is generated, and a moving image compressed and coded by the intra-frame code and the inter-frame code is reproduced. The image reproducing apparatus includes means for analyzing a code to determine whether the code is a code with fixed parameters, and performing high-speed reproduction when the code is a code with fixed parameters. An image reproducing apparatus characterized by the above-mentioned. 2. The image reproducing apparatus according to claim 1, further comprising means for enlarging and displaying the reproduced image in the case of high-speed reproduction. An image reproducing apparatus according to 3. The method of claim 1, further, I pin is intraframe when high-speed reproduction
An image reproducing apparatus comprising means for performing a decompression process only by a cuter . 4. The image reproducing apparatus according to claim 1, further comprising an intra-frame code for high-speed reproduction.
An image reproducing apparatus comprising: means for performing expansion processing with a fixed slice width . An image reproducing apparatus according to 5. The method of claim 1, further in the case of high speed reproduction, a specific high frequency in the block
An image reproducing apparatus comprising: means for calculating an inverse discrete cosine transform by regarding a wave component as 0. 6. The image reproducing apparatus according to claim 1, further comprising means for decoding only a fixed-length code in the case of high-speed reproduction.