JP3273244B2 - High-density multi-chip module and method for manufacturing the same - Google Patents

High-density multi-chip module and method for manufacturing the same

Info

Publication number
JP3273244B2
JP3273244B2 JP10303698A JP10303698A JP3273244B2 JP 3273244 B2 JP3273244 B2 JP 3273244B2 JP 10303698 A JP10303698 A JP 10303698A JP 10303698 A JP10303698 A JP 10303698A JP 3273244 B2 JP3273244 B2 JP 3273244B2
Authority
JP
Japan
Prior art keywords
chip
sub
substrate
semiconductor chip
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10303698A
Other languages
Japanese (ja)
Other versions
JPH11297927A (en
Inventor
真 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Aviation Electronics Industry Ltd
Original Assignee
Japan Aviation Electronics Industry Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Aviation Electronics Industry Ltd filed Critical Japan Aviation Electronics Industry Ltd
Priority to JP10303698A priority Critical patent/JP3273244B2/en
Publication of JPH11297927A publication Critical patent/JPH11297927A/en
Application granted granted Critical
Publication of JP3273244B2 publication Critical patent/JP3273244B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、高密度マルチチ
ップモジュールにおよびその製造方法関し、特にマルチ
チップモジュールを構成するに際して一般的に使用され
ている半導体チップをそのまま使用して積層高密度化す
る高密度マルチチップモジュールおよびその製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density multi-chip module and a method of manufacturing the same, and more particularly, to a high-density multi-chip module by directly using a semiconductor chip generally used in forming a multi-chip module. The present invention relates to a high-density multi-chip module and a method for manufacturing the same.

【0002】[0002]

【従来の技術】マルチチップモジュール(以下、MC
M、と略記する)の従来例を図5を参照して説明する。
図5において、1および2は共に半導体チップを示す。
これら半導体チップには11により示されるバンプが多
数形成されている。3はMCM基板であり、多数の半導
体チップ1および半導体チップ2が実装形成される。M
CM基板3の下面には12により示されるボールグリッ
ドアレイ(以下、BGA、と略記する)のボールが取り
付け固定されている。
2. Description of the Related Art A multi-chip module (hereinafter, MC)
M) is described with reference to FIG.
In FIG. 5, 1 and 2 both indicate semiconductor chips.
Many bumps indicated by 11 are formed on these semiconductor chips. Reference numeral 3 denotes an MCM substrate on which a large number of semiconductor chips 1 and 2 are mounted. M
Balls of a ball grid array (hereinafter abbreviated as BGA) indicated by 12 are attached and fixed to the lower surface of the CM substrate 3.

【0003】ここで、図5のMCMにおいては、各半導
体チップ1および2はフリップチップボンディング(以
下、FC接続、と略記する)或いはワイヤボンディング
(以下、WB接続、と略記する)によりMCM基板3に
個別に実装されている。図示される例は、半導体チップ
に多数形成されるバンプ11を介してMCM基板3にF
C接続される例である。4は封止樹脂であり、FC接続
されたところを封止している。
In the MCM shown in FIG. 5, each of the semiconductor chips 1 and 2 is connected to an MCM substrate 3 by flip chip bonding (hereinafter abbreviated as FC connection) or wire bonding (hereinafter abbreviated as WB connection). Has been implemented separately. In the illustrated example, the FCM is applied to the MCM substrate 3 via bumps 11 formed on a large number of semiconductor chips.
This is an example of C connection. Reference numeral 4 denotes a sealing resin, which seals a portion connected to the FC.

【0004】[0004]

【発明が解決しようとする課題】以上のMCMにおいて
は、各半導体チップ1および半導体チップ2は互いに或
る距離を有してMCM基板3に2次元的に配置実装され
ている。ここで、MCMを更に小型化しようとしても、
半導体チップの配置を2次元的に実施することに依って
は自ずと限界がある。幸いにして、MCMの厚み方向或
いは高さ方向については、他の表面実装部品に未だに高
さの比較的大きい部品が使用されているところから、半
導体チップ1および2をMCM基板3に3次元的に積み
上げて行く余地が残されている。
In the above-described MCM, the semiconductor chips 1 and the semiconductor chips 2 are two-dimensionally arranged and mounted on the MCM substrate 3 at a certain distance from each other. Here, even if we try to further downsize the MCM,
There is naturally a limit depending on the two-dimensional arrangement of semiconductor chips. Fortunately, in the thickness direction or height direction of the MCM, the semiconductor chips 1 and 2 are three-dimensionally mounted on the MCM substrate 3 because components having relatively large heights are still used for other surface mount components. There is still room to build up.

【0005】半導体チップ1および2をMCM基板3に
3次元的に実装する例としては、チップオンチップと称
される方法が実施されている。このチップオンチップ方
法を実施する場合、半導体チップ1および2とMCM基
板3との間の電気機械的接続にはFC接続およびWB接
続が併用されている。ところが、ここにおいて使用され
る半導体チップは最初からチップオンチップを前提にし
て構成された専用の形状構造を有する特殊な半導体チッ
プである。この特殊な半導体チップは、高密度実装を実
現することの他に、異種プロセスの半導体チップをモジ
ュール化する場合に使用されると共に、半導体チップを
小さくしてMCMの歩留まりを向上しようとする場合に
も使用される。この半導体チップは以上の通り形状構造
が特殊な半導体チップであるところから、これをそのま
ま使用して3次元方向に積み上げて高密度実装すること
に適用することはできない。
As an example of mounting the semiconductor chips 1 and 2 on the MCM substrate 3 three-dimensionally, a method called chip-on-chip is implemented. When implementing this chip-on-chip method, FC connection and WB connection are used together for the electromechanical connection between the semiconductor chips 1 and 2 and the MCM substrate 3. However, the semiconductor chip used here is a special semiconductor chip having a dedicated shape structure configured on the assumption of a chip-on-chip from the beginning. This special semiconductor chip is used not only for realizing high-density mounting, but also for modularizing semiconductor chips of different processes, and when trying to improve the yield of MCM by reducing the size of the semiconductor chip. Is also used. As described above, this semiconductor chip is a semiconductor chip having a special shape and structure. Therefore, it cannot be used as it is and stacked in a three-dimensional direction for high-density mounting.

【0006】この発明は、半導体チップを3次元方向に
積み上げて高密度実装するに適した専用半導体チップを
開発する必要なしに一般的に使用されている半導体チッ
プをそのまま使用して積層高密度化して上述の問題を解
消した高密度マルチチップモジュールおよびその製造方
法を提供するものである。
According to the present invention, there is no need to develop a dedicated semiconductor chip suitable for high-density mounting by stacking semiconductor chips in a three-dimensional direction. It is another object of the present invention to provide a high-density multi-chip module which solves the above-mentioned problems and a method for manufacturing the same.

【0007】[0007]

【課題を解決するための手段】請求項1:半導体チップ
1、2をMCM基板3に実装するMCMにおいて、非回
路面相互間を接合して一体化した半導体チップ1、2を
具備し、MCM基板3に電気機械的に接続されるサブ基
板5を具備し、一体化した半導体チップ1、2の内の一
方の半導体チップ1をMCM基板3にフリップチップ接
続すると共に他方の半導体チップ2をサブ基板5にワイ
ヤボンディング接続した高密度マルチチップモジュール
を構成した。
According to the present invention, there is provided an MCM in which semiconductor chips are mounted on an MCM substrate, the semiconductor chip having a non-circuit surface bonded to each other and integrated. A sub-substrate 5 is connected to the substrate 3 by electromechanical control. One of the integrated semiconductor chips 1 and 2 is flip-chip connected to the MCM substrate 3 and the other semiconductor chip 2 is A high-density multichip module connected to the substrate 5 by wire bonding was constructed.

【0008】そして、請求項2:請求項1に記載される
高密度マルチチップモジュールにおいて、一方の半導体
チップ1にバンプ11を形成し、サブ基板5の上下面に
サブ基板パッド52を形成し、MCM基板3の上面にサ
ブ基板半田付け用パッド9およびフリップチップ接続パ
ッド10を形成し、サブ基板5下面のサブ基板パッド5
2をサブ基板半田付け用パッド9に接続すると共にバン
プ11をフリップチップ接続パッド10に接続し、他方
の半導体チップ2をサブ基板5上面のサブ基板パッド5
2にワイヤ14を介して接続した高密度マルチチップモ
ジュールを構成した。
Claim 2: In the high-density multi-chip module according to claim 1, bumps 11 are formed on one semiconductor chip 1, and sub-substrate pads 52 are formed on the upper and lower surfaces of the sub-substrate 5. Sub-substrate soldering pads 9 and flip chip connection pads 10 are formed on the upper surface of the MCM substrate 3, and the sub-substrate pads 5 on the lower surface of the sub-substrate 5 are formed.
2 is connected to the sub-board soldering pad 9, the bump 11 is connected to the flip-chip connection pad 10, and the other semiconductor chip 2 is connected to the sub-board pad 5 on the upper surface of the sub-board 5.
2 was connected via a wire 14 to form a high-density multi-chip module.

【0009】また、請求項3:請求項1に記載される高
密度マルチチップモジュールにおいて、フリップチップ
接続部分を熱硬化性合成樹脂より成る封止樹脂により封
止した高密度マルチチップモジュールを構成した。ここ
で、請求項4:一方の半導体チップ1にはFC接続用の
バンプ11を形成し、一方の半導体チップ1と他方の半
導体チップ2とを相互接合することにより一体化し、M
CM基板3の内の一体化された半導体チップがFC接続
される領域に封止樹脂4を予め塗布すると共にサブ基板
5が半田付けされるサブ基板半田付け用パッド9にフラ
ックスを塗布しておき、一体化された半導体チップをM
CM基板3に対しFC接続し、MCM基板3をワイヤボ
ンダのステージ7に載置し、ここで、ステージ7の温度
をサブ基板5に形成されるBGAボール12を溶融する
温度である180℃〜250℃まで上昇させ、BGAボ
ール12を溶融してサブ基板5のサブ基板パッド52を
MCM基板3のサブ基板半田付け用パッド9に半田付け
し、次いで、ステージ7の温度を溶融BGAボール12
が硬化すると共にWB接続を実施する温度である120
℃〜150℃の間に降下、保持して半導体チップ2をサ
ブ基板5のサブ基板パッド52にWB接続する高密度マ
ルチチップモジュール製造方法を構成した。
In a third aspect of the present invention, the high-density multi-chip module has a flip-chip connection portion sealed with a sealing resin made of a thermosetting synthetic resin. . Here, claim 4: a bump 11 for FC connection is formed on one of the semiconductor chips 1, and the one semiconductor chip 1 and the other semiconductor chip 2 are integrated by mutually joining them,
A sealing resin 4 is applied in advance to a region of the CM substrate 3 where the integrated semiconductor chip is to be FC-connected, and a flux is applied to a sub-substrate soldering pad 9 to which the sub-substrate 5 is soldered. , The integrated semiconductor chip is M
An FC connection is made to the CM substrate 3 and the MCM substrate 3 is placed on the stage 7 of the wire bonder. Here, the temperature of the stage 7 is set to a temperature at which the BGA balls 12 formed on the sub-substrate 5 are melted at 180 ° C. to 250 ° C. C., the BGA ball 12 is melted, and the sub-substrate pad 52 of the sub-substrate 5 is soldered to the sub-substrate soldering pad 9 of the MCM substrate 3.
Is the temperature at which the WB connection is performed and the WB connection is performed.
A method for manufacturing a high-density multi-chip module in which the semiconductor chip 2 is dropped and held between 150 ° C. and 150 ° C. and WB-connected to the sub-substrate pad 52 of the sub-substrate 5 was constructed.

【0010】そして、請求項5:請求項4に記載される
高密度マルチチップモジュール製造方法において、一体
化された半導体チップをMCM基板3に対してFC接続
するに際してFC接続される領域に塗布された封止樹脂
4を未硬化の状態にしておく高密度マルチチップモジュ
ール製造方法を構成した。
According to a fifth aspect of the present invention, in the method of manufacturing a high-density multi-chip module according to the fourth aspect, when the integrated semiconductor chip is FC-connected to the MCM substrate 3, the integrated semiconductor chip is applied to a region to be FC-connected. A method for manufacturing a high-density multi-chip module in which the sealing resin 4 is left uncured is configured.

【0011】[0011]

【発明の実施の形態】この発明の実施の形態を図1ない
し図3を参照して説明する。図1はこの発明によるMC
Mを示し、図1(a)は上から視たところを示す図であ
り、図1(b)は図1(a)における上下方向の断面を
示す図である。図1において、1および2は共に半導体
チップを示す。これら半導体チップには11により示さ
れるバンプが多数形成されている。3はMCM基板であ
り、多数の半導体チップ1および半導体チップ2が実装
形成される。MCM基板3の下面には12により示され
るBGAボールが取り付け固定されている。このMCM
においては、各半導体チップ1および半導体チップ2は
FC接続或いはWB接続によりMCM基板3に実装され
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an MC according to the present invention.
M is shown, FIG. 1 (a) is a view from above, and FIG. 1 (b) is a view showing a vertical cross section in FIG. 1 (a). In FIG. 1, 1 and 2 both indicate semiconductor chips. Many bumps indicated by 11 are formed on these semiconductor chips. Reference numeral 3 denotes an MCM substrate on which a large number of semiconductor chips 1 and semiconductor chips 2 are mounted. BGA balls indicated by 12 are attached and fixed to the lower surface of the MCM substrate 3. This MCM
In, each semiconductor chip 1 and semiconductor chip 2 are mounted on the MCM board 3 by FC connection or WB connection.

【0012】ここで、半導体チップ1および半導体チッ
プ2は、バンプ11その他の回路構成部材が形成されて
いない非回路面同志をダイボンディング樹脂8により相
互接合一体化されている。5はサブ基板であり、その中
央部には51により示されるチップ挿入開孔が形成され
ている。52はサブ基板5の上面および下面に形成され
るサブ基板パッドである。サブ基板5は下面に形成され
るサブ基板パッド52をMCM基板3の上面に形成され
るサブ基板半田付け用パッド9に半田付けすることによ
り電気機械的に結合されている。13はサブ基板半田付
け部である。
Here, the semiconductor chip 1 and the semiconductor chip 2 are integrally joined to each other by a die bonding resin 8 between non-circuit surfaces on which the bumps 11 and other circuit components are not formed. Reference numeral 5 denotes a sub-substrate, and a chip insertion opening indicated by 51 is formed in the center thereof. Reference numeral 52 denotes a sub-substrate pad formed on the upper and lower surfaces of the sub-substrate 5. The sub-board 5 is electromechanically coupled by soldering a sub-board pad 52 formed on the lower surface to a sub-board soldering pad 9 formed on the upper surface of the MCM substrate 3. Reference numeral 13 denotes a sub-board soldering portion.

【0013】図1において、半導体チップ1は、多数形
成される自身のバンプ11をMCM基板3上面に多数形
成されるフリップチップ接続パッド10に半田付けする
ことによりMCM基板3にFC接続される。このFC接
続部分は熱硬化性合成樹脂より成る封止樹脂4により封
止されている。半導体チップ2はワイヤ14を介してサ
ブ基板5の上面に形成されるサブ基板パッド52にWB
接続されている。6はこのWB接続部分を封止する熱硬
化性合成樹脂より成る封止樹脂を示す。半導体チップ2
は、以上の通りにして、ワイヤ14、サブ基板5、サブ
基板半田付け部13を介してMCM基板3に電気的に接
続されることになる。
In FIG. 1, the semiconductor chip 1 is FC-connected to the MCM substrate 3 by soldering a large number of its own bumps 11 to flip chip connection pads 10 formed on the upper surface of the MCM substrate 3. This FC connection portion is sealed with a sealing resin 4 made of a thermosetting synthetic resin. The semiconductor chip 2 is connected to the sub-substrate pad 52 formed on the upper surface of the sub-substrate 5 via the wire 14 by WB.
It is connected. Reference numeral 6 denotes a sealing resin made of a thermosetting synthetic resin for sealing the WB connection portion. Semiconductor chip 2
Is electrically connected to the MCM board 3 via the wire 14, the sub-board 5, and the sub-board soldering section 13 as described above.

【0014】次に、図1のMCMの製造工程を図2ない
し図4を参照して説明する。図2(a)を参照するに、
先ず、半導体チップ1にFC接続用のバンプ11を形成
する。次いで、半導体チップ1と半導体チップ2とをそ
の非回路面にダイボンディング樹脂8を施して相互接合
することにより一体化する。図2(b)を参照するに、
MCM基板3の内の一体化された半導体チップ1と半導
体チップ2がFC接続されるフリップチップ接続パッド
10が形成される領域に封止樹脂4を予め塗布すると共
に、サブ基板5が半田付けされるサブ基板半田付け用パ
ッド9にフラックスを塗布しておく。
Next, a manufacturing process of the MCM shown in FIG. 1 will be described with reference to FIGS. Referring to FIG. 2A,
First, the bumps 11 for FC connection are formed on the semiconductor chip 1. Next, the semiconductor chip 1 and the semiconductor chip 2 are integrated by applying a die bonding resin 8 to the non-circuit surface thereof and joining them together. Referring to FIG. 2B,
The sealing resin 4 is applied in advance to a region of the MCM substrate 3 where a flip chip connection pad 10 to which the integrated semiconductor chip 1 and semiconductor chip 2 are connected by FC is formed, and the sub-substrate 5 is soldered. The sub-substrate soldering pad 9 is coated with a flux.

【0015】図3(a)および図3(b)を参照する
に、接合して一体化された半導体チップ1と半導体チッ
プ2を、MCM基板3に対して半導体チップ1のバンプ
11が形成された面を下にしてFC接続する。この場
合、FC接続部分に予め塗布しておいた封止樹脂4の硬
化が終了しない内にMCM基板3に対する一体化された
半導体チップの加圧および半田付け部分の加熱を終了す
る。図3(b)はFC接続部分が封止樹脂4により適正
に封止された状態を示す。
Referring to FIG. 3A and FIG. 3B, the semiconductor chip 1 and the semiconductor chip 2 which are joined and integrated are formed, and bumps 11 of the semiconductor chip 1 are formed on the MCM substrate 3. FC connection with the side facing down. In this case, the pressurization of the integrated semiconductor chip on the MCM substrate 3 and the heating of the soldered portion are completed before the curing of the sealing resin 4 previously applied to the FC connection portion is not completed. FIG. 3B shows a state where the FC connection portion is properly sealed with the sealing resin 4.

【0016】図3(c)を参照するに、サブ基板5の下
面に形成されるサブ基板パッド52にはBGAボール1
2が付与されている。サブ基板5のBGAボール12を
MCM基板3のサブ基板半田付け用パッド9に対応位置
決めした状態に、サブ基板5をMCM基板3に搭載す
る。この仮搭載状態は、サブ基板5のBGAボール12
がフラックスの粘着性によりサブ基板半田付け用パッド
9に保持されることにより保たれている。
Referring to FIG. 3C, a BGA ball 1 is provided on a sub-substrate pad 52 formed on the lower surface of the sub-substrate 5.
2 is given. The sub-board 5 is mounted on the MCM board 3 with the BGA balls 12 of the sub-board 5 positioned so as to correspond to the sub-board soldering pads 9 of the MCM board 3. This temporary mounting state is determined by the BGA balls 12 on the sub-board 5.
Is held by the sub-substrate soldering pad 9 due to the adhesiveness of the flux.

【0017】図4を参照するに、一体化された半導体チ
ップ1および半導体チップ2が固定されると共にサブ基
板5が仮搭載されたMCM基板3をワイヤボンダのステ
ージ7に載置する。ここで、ステージ7の温度をサブ基
板5のBGAボール12を溶融してBGA半田付けを実
施する温度である180℃〜250℃まで上昇させ、B
GAボール12を溶融してサブ基板5のサブ基板パッド
52をMCM基板3のサブ基板半田付け用パッド9に半
田付けする。その後、ステージ7の温度を溶融BGAボ
ール12が硬化すると共にWB接続を実施することがで
きる温度である120℃〜150℃の間に降下させ、サ
ブ基板5に形成されるサブ基板パッド52の表面温度を
120℃〜150℃の間に保持する。この温度範囲にお
いて半導体チップ2をワイヤ14を介してサブ基板5の
サブ基板パッド52にWB接続する。引き続いて、ステ
ージ7上においてMCM基板3が加熱され、硬化が完了
していないFC接続部分の封止樹脂4の硬化を完了させ
る。
Referring to FIG. 4, the MCM substrate 3 on which the integrated semiconductor chip 1 and semiconductor chip 2 are fixed and the sub-substrate 5 is temporarily mounted is placed on the stage 7 of the wire bonder. Here, the temperature of the stage 7 is raised to 180 ° C. to 250 ° C., which is the temperature at which the BGA balls 12 of the sub-substrate 5 are melted and BGA soldering is performed.
The GA ball 12 is melted, and the sub-substrate pad 52 of the sub-substrate 5 is soldered to the sub-substrate soldering pad 9 of the MCM substrate 3. Thereafter, the temperature of the stage 7 is lowered to a temperature at which the molten BGA ball 12 is hardened and the WB connection can be performed at 120 ° C. to 150 ° C., and the surface of the sub-substrate pad 52 formed on the sub-substrate 5 The temperature is maintained between 120C and 150C. In this temperature range, the semiconductor chip 2 is WB-connected to the sub-substrate pad 52 of the sub-substrate 5 via the wire 14. Subsequently, the MCM substrate 3 is heated on the stage 7 to complete the curing of the sealing resin 4 at the FC connection portion where the curing is not completed.

【0018】最後に、WB接続部分に封止樹脂6を適用
してこれを硬化し、更にMCM基板3の下面にBGAボ
ール12の形成を行って全製造工程を終了する。なお、
半導体チップ1のバンプ11とMCM基板3のフリップ
チップ接続パッド10とは、封止樹脂4が硬化するに際
して生ずる収縮力により互いに引き付けられて確実に電
気接続する。
Finally, the sealing resin 6 is applied to the WB connection portion and cured, and the BGA balls 12 are formed on the lower surface of the MCM substrate 3 to complete the entire manufacturing process. In addition,
Flip of bump 11 of semiconductor chip 1 and MCM substrate 3
The chip connection pads 10 are attracted to each other by a contraction force generated when the sealing resin 4 is hardened, and are reliably connected electrically.

【0019】以上の通り、非回路面を接合することによ
り相互に一体化された半導体チップをFC接続およびW
B接続を併用することによりMCM基板に対して3次元
的に実装することができる。そして、ワイヤボンダのス
テージ7上においてFC接続の封止樹脂4の硬化を終了
させてサブ基板5のBGA半田付けを実施した後、WB
接続を実施することにより次の通りの効果を奏するに到
る。即ち、従来のMCM製造工程においては半導体チッ
プをMCM基板に仮実装してから封止樹脂の硬化が完了
するまで加圧加熱状態を保持している。ところが、この
発明に依れば、ワイヤボンダのステージ上においてサブ
基板のBGAボール半田付けおよびWB接続を実施して
いる間にFC接続部分の封止樹脂4の硬化が並列的に行
われる。また、ワイヤボンダのステージ7の温度を降下
させることによりサブ基板5のBGAボール12の半田
付け直後のMCM基板3の上面に対してワイヤ14のW
B接続を実施することができる。
As described above, the semiconductor chips integrated by joining the non-circuit surfaces are connected to each other by FC connection and W connection.
By using the B connection together, it can be mounted three-dimensionally on the MCM substrate. Then, the hardening of the sealing resin 4 for FC connection is completed on the stage 7 of the wire bonder, and BGA soldering of the sub-board 5 is performed.
By performing the connection, the following effects can be obtained. That is, in the conventional MCM manufacturing process, the semiconductor chip is temporarily mounted on the MCM substrate and then kept under pressure and heat until the curing of the sealing resin is completed. However, according to the present invention, while the BGA ball soldering of the sub-board and the WB connection are performed on the stage of the wire bonder, the curing of the sealing resin 4 at the FC connection portion is performed in parallel. Further, by lowering the temperature of the stage 7 of the wire bonder, the W of the wire 14 with respect to the upper surface of the MCM substrate 3 immediately after the soldering of the BGA ball 12 of the sub-substrate 5 is performed.
A B connection can be implemented.

【0020】[0020]

【発明の効果】以上の通りであって、この発明に依れ
ば、非回路面を接合することにより相互に一体化された
半導体チップをFC接続およびWB接続を併用すること
によりMCM基板に対して3次元的に実装することがで
き、結局、半導体チップの1チップ分のエリアに2チッ
プを実装することができるに到る。
As described above, according to the present invention, the semiconductor chip integrated by joining non-circuit surfaces to the MCM substrate by using both FC connection and WB connection. In this way, two chips can be mounted in one chip area of the semiconductor chip.

【0021】そして、ワイヤボンダのステージ上におい
てサブ基板のBGAボール半田付けおよびWB接続を実
施している間にFC接続部分の未硬化状態にあった封止
樹脂の硬化が並列的に行われることにより、一体化され
た半導体チップをWB接続とFC接続を併用してMCM
基板3に実装する工程数、或いは実装するに要する時間
を大きく短縮することができる。
Then, while the BGA ball soldering of the sub-board and the WB connection are being performed on the stage of the wire bonder, the uncured sealing resin of the FC connection portion is cured in parallel. , MCM using integrated WB connection and FC connection
The number of steps for mounting on the substrate 3 or the time required for mounting can be greatly reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施例を説明する図。FIG. 1 illustrates an embodiment.

【図2】製造工程を説明する図。FIG. 2 illustrates a manufacturing process.

【図3】図2の続き。FIG. 3 is a continuation of FIG. 2;

【図4】図3の続き。FIG. 4 is a continuation of FIG. 3;

【図5】従来例を説明する図。FIG. 5 is a diagram illustrating a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 半導体チップ 3 MCM基板 4 封止樹脂 5 サブ基板 6 封止樹脂 7 ワイヤボンダステージ 8 ダイボンディング樹脂 9 サブ基板半田付け用パッド 10 フリップチップ接続パッド 11 バンプ 12 BGAボール 13 サブ基板半田付け部 14 ワイヤ 51 チップ挿入開孔 52 サブ基板パッド DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Semiconductor chip 3 MCM board 4 Sealing resin 5 Sub board 6 Sealing resin 7 Wire bonder stage 8 Die bonding resin 9 Sub board soldering pad 10 Flip chip connection pad 11 Bump 12 BGA ball 13 Sub board soldering part 14 Wire 51 Chip insertion opening 52 Sub board pad

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体チップをマルチチップモジュール
基板に実装するマルチチップモジュールにおいて、 非回路面相互間を接合して一体化した半導体チップを具
備し、マルチチップモジュール 基板に電気機械的に接続される
サブ基板を具備し、 一体化した半導体チップの内の一方の半導体チップを
ルチチップモジュール基板にフリップチップ接続すると
共に他方の半導体チップをサブ基板にワイヤボンディン
グ接続したことを特徴とする高密度マルチチップモジュ
ール。
1. A multi-chip module for mounting a semiconductor chip on a multi-chip module <br/> substrate, comprising a semiconductor chip that is integrated by bonding between non-circuit face each other, a multi-chip module substrate electromechanical comprising a sub-substrate connected to, Ma one semiconductor chip of the integrated semiconductor chip
Ruchi chip density multi-chip module, characterized in that the other semiconductor chip wire bonded connection to the sub-substrate together with the module substrate is flip-chip connected.
【請求項2】 請求項1に記載される高密度マルチチッ
プモジュールにおいて、 一方の半導体チップにバンプを形成し、 サブ基板の上下面にサブ基板パッドを形成し、マルチチップモジュール 基板の上面にサブ基板半田付け
用パッドおよびフリップチップ接続パッドを形成し、 サブ基板下面のサブ基板パッドをサブ基板半田付け用パ
ッドに接続すると共にバンプをフリップチップ接続パッ
ドに接続し、 他方の半導体チップをサブ基板上面のサブ基板パッドに
ワイヤを介して接続したことを特徴とする高密度マルチ
チップモジュール。
2. The high-density multi-chip module according to claim 1, wherein a bump is formed on one of the semiconductor chips, a sub-substrate pad is formed on upper and lower surfaces of the sub-substrate, and a sub-substrate is formed on the upper surface of the multi-chip module substrate. Form the board soldering pad and flip chip connection pad, connect the sub board pad on the bottom of the sub board to the sub board soldering pad, connect the bump to the flip chip connection pad, and connect the other semiconductor chip to the top of the sub board A high-density multi-chip module connected to the sub-substrate pad via a wire.
【請求項3】 請求項1に記載される高密度マルチチッ
プモジュールにおいて、 フリップチップ接続部分およびワイヤボンディング接続
部分を熱硬化性合成樹脂より成る封止樹脂により封止し
たことを特徴とする高密度マルチチップモジュール。
3. The high-density multi-chip module according to claim 1, wherein the flip-chip connection portion and the wire bonding connection portion are sealed with a sealing resin made of a thermosetting synthetic resin. Multi-chip module.
【請求項4】 一方の半導体チップにフリップチップ
続用のバンプを形成し、 一方の半導体チップと他方の半導体チップとを相互接合
することにより一体化し、マルチチップモジュール 基板の内の一体化された半導体
チップがフリップチップ接続される領域に封止樹脂を予
め塗布すると共にサブ基板が半田付けされるサブ基板半
田付け用パッドにフラックスを塗布しておき、 一体化された半導体チップをマルチチップモジュール
板に対してフリップチップ接続し、マルチチップモジュール 基板をワイヤボンダのステージ
に載置し、 ここで、ステージの温度をサブ基板に形成されるボール
グリッドアレイのボールを溶融する温度である180℃
〜250℃まで上昇させ、ボールグリッドアレイのボー
ルを溶融してサブ基板のサブ基板パッドをマルチチップ
モジュール基板のサブ基板半田付け用パッドに半田付け
し、 次いで、ステージの温度を溶融ボールグリッドアレイの
ボールが硬化すると共にワイヤボンディング接続を実施
する温度である120℃〜150℃の間に降下、保持し
て半導体チップをサブ基板のサブ基板パッドにワイヤボ
ンディング接続することを特徴とする高密度マルチチッ
プモジュール製造方法。
4. A flip chip connecting bump is formed on one of the semiconductor chips, and the one semiconductor chip and the other semiconductor chip are interconnected to be integrated to form a single chip . A sealing resin is applied in advance to a region where the integrated semiconductor chip is to be flip-chip connected, and a flux is applied to a sub-board soldering pad to which the sub-substrate is to be soldered. the flip-chip connected to the multi-chip module group <br/> plate, placing the multi-chip module substrate on the stage of the wire bonder, where the ball is formed the temperature of the stage to the sub-substrate
180 ° C, the temperature at which the grid array balls are melted
To 250 ° C, melt the ball of the ball grid array and multi-chip
Soldering to the sub-board soldering pads of the module substrate, and then setting the stage temperature to between 120 ° C. and 150 ° C., which is the temperature at which the balls of the molten ball grid array are hardened and the wire bonding connection is performed. Waiyabo descent, holding the semiconductor chip on the sub-board sub-board pad
A method for manufacturing a high-density multi-chip module, comprising:
【請求項5】 請求項4に記載される高密度マルチチッ
プモジュール製造方法において、 一体化された半導体チップをマルチチップモジュール
板に対してフリップチップ接続するに際してフリップチ
ップ接続される領域に塗布された封止樹脂を未硬化の状
態にしておくことを特徴とする高密度マルチチップモジ
ュール製造方法。
5. A high-density multi-chip module manufacturing method described in claim 4, Furippuchi upon flip-chip connecting the integrated semiconductor chip for multi-chip module group <br/> plate
A method for manufacturing a high-density multi-chip module, wherein an encapsulating resin applied to a region to be connected to a chip is left uncured.
JP10303698A 1998-04-14 1998-04-14 High-density multi-chip module and method for manufacturing the same Expired - Fee Related JP3273244B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10303698A JP3273244B2 (en) 1998-04-14 1998-04-14 High-density multi-chip module and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10303698A JP3273244B2 (en) 1998-04-14 1998-04-14 High-density multi-chip module and method for manufacturing the same

Publications (2)

Publication Number Publication Date
JPH11297927A JPH11297927A (en) 1999-10-29
JP3273244B2 true JP3273244B2 (en) 2002-04-08

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ID=14343443

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Country Link
JP (1) JP3273244B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3566957B2 (en) 2002-12-24 2004-09-15 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
JP5068990B2 (en) * 2006-12-26 2012-11-07 新光電気工業株式会社 Electronic component built-in board
JP2010203890A (en) * 2009-03-03 2010-09-16 Tokyo Cathode Laboratory Co Ltd Probe card and method for manufacturing the same
US9484327B2 (en) * 2013-03-15 2016-11-01 Qualcomm Incorporated Package-on-package structure with reduced height
WO2023089988A1 (en) * 2021-11-22 2023-05-25 株式会社村田製作所 Module

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