JP3270245B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an interlayer insulating film between wiring layers and a method of forming the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have become multi-layered. For example, an interlayer insulating film is formed on a first wiring layer of a semiconductor substrate, and a second wiring layer is formed on the surface of the interlayer insulating film. There are many semiconductor devices having a structure that performs the following. As an example of a semiconductor device having such a structure, a DRAM (Dynami
c Random Access Memory)
This will be described below with reference to the drawings.

As shown in FIG. 4, one element portion of a DRAM is formed in an element isolation layer 112 formed on the surface of a P-type silicon substrate 111 and in an element region surrounded by the element isolation layer 112 in an island shape. An oxide film 113 on the substrate surface, a capacitor electrode 114 of a P-doped polycrystalline silicon film formed on the surface of the oxide film 113 and the surface of the element isolation layer 112, and an oxide film adjacent to the The word line 115 of the transistor formed on the surface of the film 113 and the substrate 1
11 has N ⁺ diffusion layers 116 and 117 formed using a capacitor electrode 114 and a word line 115 as a mask.

Further, a BPSG film having a thickness of 4000 Å formed with an interlayer insulating film formed of a substrate and a first wiring layer.
(Borophospho Silicate Glass) film 118 and BPSG
A contact hole 119 formed in the film 118 and a W film 120 embedded in the contact hole 119
And an Al—Si film 121 formed as a first wiring layer on the entire surface of the BPSG film 23.

[0005] On the surface of the Al-Si film 121, as an interlayer insulating film 125, a plasma TEOS (Tetra Ethoxy Silane) film 122 having a film thickness of 3000 Å and a film thickness 1 formed on the surface of the plasma TEOS film 122.
It has an SOG (Spin-on Glass) film 123 of μm, and a 3000 Å-thick plasma TEOS film 124 formed on the surface of the SOG film 123. The SOG film 123 is formed between the plasma TEOS films 122 and 124 in order to improve the flatness of the interlayer insulating film.

A contact hole 126 is formed in the interlayer insulating film 125 with the Al-Si film 121, which is the first wiring layer previously formed, and is formed on the entire surface of the interlayer insulating film 125 as a second wiring layer. An Al-Si film 127 having a thickness of 1 μm is formed. As described above, a conventional interlayer insulating film between wiring layers has a laminated structure using a plasma TEOS film and an SOG film.

However, the above-mentioned manufacturing method has the following problems. First, as shown in the cross-sectional view of FIG.
Since the plasma TEOS film is formed by a reaction gas flowing into the reaction tube, it generates a large amount of Si-based dust and the like in addition to the formation of the TEOS film. This dust deteriorates the flatness of the interlayer insulating film itself. Therefore, for example, when dust 152 adheres to the surface of the interlayer insulating film 151, the second wiring layer 1 formed by the evaporation method
53 may be disconnected.

As shown in the perspective view of the wiring layer in FIG. 5B, the plasma TEOS film between the first Al-Si film wiring layer 162 formed adjacently on the BPSG film 161 is formed. Is formed and dust 1
When 63 enters, the withstand voltage between the wiring layers 162 decreases, which may cause dielectric breakdown between the wiring layers.

[0009]

As described above, in the conventional method for forming a multilayer wiring layer, a large amount of dust is generated when a plasma TEOS film to be formed as an interlayer insulating film is formed, and this dust causes the interlayer insulating film to be damaged. There is a problem that the flatness of the film is deteriorated and the wiring layer formed on the surface of the interlayer insulating film is disconnected. If this dust enters between adjacent wiring layers that should be insulated,
There is a problem of causing dielectric breakdown between wiring layers.

In the present invention, in consideration of the above-mentioned problems, a film which is formed as an interlayer insulating film is a film which generates a small amount of dust and can obtain sufficient flatness for forming a multilayer wiring layer. Accordingly, an object of the present invention is to improve the reliability of a semiconductor device in a multilayer wiring technique.

[0011]

In order to achieve the above-mentioned object, in the present invention, an amorphous silicon film to which O and B are added as a first layer is used as an interlayer insulating film on a wiring layer. An SOG film is used as a second interlayer insulating film on the surface of the amorphous silicon film. On the surface of the SOG film, an amorphous silicon film to which O and B are added is used as a third interlayer insulating film as in the first layer. A wiring layer is formed on the surface of the three-layered interlayer insulating film to form a multilayer wiring layer of the semiconductor device.

[0012]

According to the present invention, a large amount of dust is generated when an interlayer insulating film is formed by using an amorphous silicon film to which O and B are added in an upper layer portion and a lower layer portion as an interlayer insulating film. In addition, problems such as dielectric breakdown between wiring layers and disconnection of wiring layers can be solved. Further, the coverage of the interlayer insulating film can be improved, and breakage or destruction of the interlayer insulating film or the wiring layer can be prevented. Therefore, the reliability of the multilayer wiring layer of the semiconductor device can be improved.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the embodiment of the present invention, together with the manufacturing method,
This will be described below with reference to the drawings. In this embodiment, as an example of a semiconductor device using a multilayer wiring structure, a DRAM is used.
A method of forming an interlayer insulating film between the multilayer wiring layers will be described.

As shown in FIG. 1A, one element portion between the wiring layers of the DRAM is surrounded by an element isolation layer 12 formed on the surface of a P-type silicon substrate 11 and an island shape by the element isolation layer 12. And a P-doped 4000 Å thick oxide film 13 formed on the substrate surface and formed on the surface of the oxide film 13 and on the surface of the element isolation layer 12 in the region where the oxide film 13 is formed. A capacitor electrode 14 made of a crystalline silicon film, a transistor word line 15 formed adjacent thereto, and an N ⁺ formed in the substrate 11 using the capacitor electrode 14 and the word line 15 as a mask.
Diffusion layers 16 and 17.

On the semiconductor substrate, a BP having a thickness of 4000 Å is used as an interlayer insulating film between the substrate and the wiring layer.
SG film 18, contact hole 19 formed in BPSG film 18, and W embedded in the contact hole
An Al-Si film 21 having a thickness of 4000 angstroms is formed as a first wiring layer on the surface of the film 20 and the BPSG film.

FIG. 1B shows a method of forming an interlayer insulating film according to the present invention. First, an 3000-Å-thick amorphous silicon film 22 (hereinafter simply referred to as an amorphous silicon film) to which O and B are added is formed on the surface of an Al—Si film 21 as a first wiring layer. This amorphous silicon film 22
Is LPCVD (Low Pressure Chemical Vapor Depos)
0.1 torr maintained at 300 ° C by the
r ₂ reaction chamber, Si ₂ H ₆ gas 100 cc / min,
B ₂ H ₆ gas 20cc / min, O ₂ gas 16 cc / m
In is formed by flowing in respectively. Since the interlayer insulating film is formed after the formation of the first wiring layer, it must be formed at a temperature lower than the melting point of the wiring layer. For this reason,
B ₂ H ₆ gas flows into the reaction tube to promote thermal decomposition of the Si ₂ H ₆ gas at a low temperature. As a result, B is added to the amorphous silicon film 22. O is added to improve the breakdown voltage of the interlayer insulating film.

Next, a 1 μm thick SOG film 23 is formed on the surface of the amorphous silicon film 22. This SO
The G film 23 is formed for improving the flatness, and is formed by the same forming method as that of the related art.

Next, on the surface of the SOG film 23, an amorphous silicon film 2 having a thickness of 3000 Å is formed again.
4 is formed. The formation method is the same as that of the above-mentioned amorphous silicon film 22. Thus, an interlayer insulating film 25 is formed on the first wiring layer.

Subsequently, as shown in FIG. 1C, a contact hole 26 for making contact with the Al-Si film 21 which is the first wiring layer formed earlier is formed in the interlayer insulating film 25. . Next, an Al—Si film 27 having a thickness of 1 μm is formed as a second wiring layer by filling the entire surface of the interlayer insulating film 25 and the contact holes 26. With the above steps, the manufacturing process of the multilayer wiring layer of the DRAM is completed.

The method of forming an amorphous silicon film shown in the above embodiment is not limited to the above-mentioned gas inflow amount, but can be formed with different inflow amounts. For example, when the inflow amount of the O ₂ gas is changed, the sheet resistance of the amorphous silicon film changes. Therefore, the film formation speed, sheet resistance, and the like can be changed by changing the inflow amount of the inflow gas when forming the amorphous silicon film.

FIG. 2 shows the sheet resistance of the amorphous silicon film when the amorphous silicon film is formed by changing the inflow amount of the O ₂ gas. In this case, the pressure in the reaction tube is 0.1 torr and the temperature is 300 ° C. The flow rate of the Si ₂ H ₆ gas is 100 cc / mi.
n, the flow rate of the B ₂ H ₆ gas is 20 cc / min. According to this, it is understood that the sheet resistance increases as the flow rate of the O ₂ gas increases.

FIG. 3 shows the effect of the present invention. In FIG. 3A, on the surface of an amorphous silicon film formed on the surface of a 6-inch substrate by the manufacturing method of the present invention, and on the surface of a plasma TEOS film formed on the surface of a 6-inch substrate by the conventional manufacturing method. The results of measuring the number of dust particles having a diameter of 0.3 μm or more per substrate are shown. Here, the horizontal axis indicates the number of substrates from the furnace port, and shows the case where the processing was performed with 100 substrates in four lots. According to this, the number of dusts is 70 to 80 in the case of the conventional manufacturing method, but is at most about 20 in the case of the present invention, and the number of dusts adhering to the substrate is greatly reduced. You can see that it is. FIG. 3 (b)
3 shows the relationship between the failure rates due to the occurrence of dielectric breakdown between the wiring layers when the distance between the adjacent first-layer wiring layers is changed. Here, for comparison, the relationship between the defect rate due to the occurrence of dielectric breakdown between wiring layers of the plasma TEOS film formed by the conventional manufacturing method is also shown.
The wiring width is constant at 0.7 μm. According to this, in the case of the conventional manufacturing method, when the distance between the wiring layers is short, the defect rate may be high, but in the case of the present invention, no defect occurs even when the distance between the wiring layers is short. You can see that.

FIG. 3 (c) shows the relationship between the failure rate due to the occurrence of disconnection when the wiring width of the second wiring layer is changed. Here, for comparison, the occurrence of disconnection of the wiring layer of the plasma TEOS film formed by the conventional manufacturing method is described.
The relationship between the defect rates is also shown. The distance between the wiring layers is constant at 0.8 μm. According to this, in the case of the conventional manufacturing method, the defect rate increases when the width of the wiring layer is short, but it can be seen that the defect according to the present invention does not occur even when the wiring width is short.

As described above, by forming an amorphous silicon film to which O and B are added instead of the plasma TEOS film conventionally formed as an interlayer insulating film,
Dust, which has been a problem in the past, can be reduced while maintaining a high resistance value, and problems such as dielectric breakdown between wiring layers and disconnection of wiring layers can be solved.

In the above embodiment, an example of a method of forming a multi-layer wiring layer of a DRAM has been described. It is possible.

[0026]

According to the present invention, by forming an amorphous silicon film to which O and B are added as an interlayer insulating film, it is possible to reduce dust which has conventionally been a problem while maintaining a high resistance value. Thus, problems such as dielectric breakdown between wiring layers and disconnection of wiring layers can be solved, reliability of a semiconductor device with respect to a multilayer wiring layer can be improved, and multilayer wiring can be promoted.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing method and a structure according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing the effect of the embodiment of the present invention.

FIG. 4 is a sectional view showing a conventional structure.

FIG. 5 is an explanatory view showing a conventional problem.

[Explanation of symbols]

11, 111 P-type silicon substrate 12, 112 Element isolation layer 13, 113 Oxide film 14, 114 Capacitor electrode 15, 115 Word line 16, 17, 116, 117 N ⁺ diffusion layer 18, 118, 161 BPSG film 19, 26 119, 126 Contact holes 20, 120 W film 21, 27, 121, 127 Al-Si film 22, 24 Amorphous silicon film 23, 123 SOG film 25, 125, 151 Interlayer insulating film 122, 124 Plasma TEOS film 152, 163 Dust 153 Second Al-Si film wiring layer 162 First Al-Si film wiring layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-250655 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21 / 768

Claims (4)

(57) [Claims] 1. A semiconductor device having at least two or more wiring layers and an interlayer insulating film formed between the wiring layers, wherein the interlayer insulating film is formed of oxygen and boron formed in a lower layer. A first amorphous silicon film containing an element, a SOG (Spin-on Glass) film formed on the first amorphous silicon film, and oxygen and boron elements formed on the SOG film And a second amorphous silicon film containing: 2. A first wiring layer formed on a semiconductor substrate; a first amorphous silicon film containing oxygen and boron elements formed on a surface of the first wiring layer; SOG formed on amorphous silicon film surface
(Spin-on Glass) film, a second amorphous silicon film containing oxygen and boron elements formed on the surface of the SOG film, and a second amorphous silicon film formed on the surface of the second amorphous silicon film A semiconductor device comprising: a second conductive layer. Forming a first amorphous silicon film containing an element of oxygen and boron on a surface of a first wiring layer formed on a semiconductor substrate; and a surface of the first amorphous silicon film. SOG (Spin-on
A step of forming a second amorphous silicon film containing oxygen and boron elements on the surface of the SOG film; and a second step of forming a second amorphous silicon film on the surface of the second amorphous silicon film. Forming a conductive layer. 4. The method of manufacturing a semiconductor device according to claim 3, wherein said first and second amorphous silicon films are formed in a reaction tube.
A method for manufacturing a semiconductor device, comprising forming a semiconductor device by flowing i ₂ H ₆ gas, B ₂ H ₆ gas, and O ₂ gas.