JP3266810B2 - Multi-stage voltage doubler rectifier circuit - Google Patents

Multi-stage voltage doubler rectifier circuit

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Publication number
JP3266810B2
JP3266810B2 JP27864996A JP27864996A JP3266810B2 JP 3266810 B2 JP3266810 B2 JP 3266810B2 JP 27864996 A JP27864996 A JP 27864996A JP 27864996 A JP27864996 A JP 27864996A JP 3266810 B2 JP3266810 B2 JP 3266810B2
Authority
JP
Japan
Prior art keywords
column
rectifier circuit
doubler rectifier
voltage doubler
capacitors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP27864996A
Other languages
Japanese (ja)
Other versions
JPH10108466A (en
Inventor
泰男 長谷川
善博 毛塚
徳次 松沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP27864996A priority Critical patent/JP3266810B2/en
Publication of JPH10108466A publication Critical patent/JPH10108466A/en
Application granted granted Critical
Publication of JP3266810B2 publication Critical patent/JP3266810B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】 本発明は多段倍電圧整流回路に
関するものであり,特にイメージインテンシファイア管
や静電塗装用のガン等に内蔵される形状の多段倍電圧整
流回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multistage voltage doubler rectifier circuit, and more particularly to a multistage voltage doubler rectifier circuit built in an image intensifier tube or a gun for electrostatic coating.

【0002】[0002]

【従来技術】 イメージインテンシファイア管に用いら
れる10kV〜30kV程度の直流高電圧発生装置は,電圧は高
いが電流はほとんどゼロである。また静電塗装用の60kV
〜80kV程度の直流高電圧発生装置は,電圧は高いが電流
は数十マイクロアンペアであり,消費エネルギーとして
はいずれも小さいものである。そのため回路構成として
は,20kHz ないし100kHzの高周波を多段倍電圧整流回路
で整流して小型軽量になるように構成する。そして高電
圧構成部品については,合成樹脂絶縁材でモールドする
ことにより小型軽量にしている。このような構成で直接
目的の装置に取り付ける程度に小型軽量化することが可
能である。
2. Description of the Related Art A DC high voltage generator of about 10 kV to 30 kV used for an image intensifier tube has a high voltage but almost no current. 60kV for electrostatic painting
DC high voltage generators of ~ 80 kV have high voltage but current of several tens of microamps, and consume little energy. For this reason, the circuit configuration is designed so that high frequencies of 20 kHz to 100 kHz are rectified by a multistage voltage doubler rectifier circuit to reduce the size and weight. High-voltage components are compact and lightweight by being molded with a synthetic resin insulating material. With such a configuration, it is possible to reduce the size and weight so as to be directly attached to the target device.

【0003】 例えば実公昭50−22059号には,
静電塗装用の塗装ガンとして,多段倍圧整流器を内蔵さ
せて,これに高周波電圧を供給して,その高圧出力を荷
電電極に接続する考案が示されている。また,1968
年発行のフランス国特許公報第1,542,090号に
も同様の発明が示されている。なお,この原出願は,1
966年ドイツ連邦共和国にL54968で出願されて
いる。さらに,実公昭59−36282号には,塗装ガ
ン内部に,多段倍圧整流器と中高圧の高周波を発生する
変換回路とを内蔵させて,これに直流低電圧を供給する
装置が提案されている。しかし,いずれも高電圧部の絶
縁構成については,詳細には提案または開示されてはい
ない。
For example, in Japanese Utility Model Publication No. 50-22059,
As a coating gun for electrostatic coating, there is disclosed a device in which a multi-stage voltage doubler rectifier is incorporated, a high frequency voltage is supplied to the rectifier, and the high voltage output is connected to a charging electrode. Also, 1968
A similar invention is also shown in French Patent Publication No. 1,542,090 issued year. The original application is 1
Filed in Germany in 966 with L54968. Furthermore, Japanese Utility Model Publication No. 59-36282 proposes a device in which a multistage voltage doubler rectifier and a conversion circuit for generating a high voltage of a medium to high voltage are built in a coating gun, and a DC low voltage is supplied to the device. . However, none of them has proposed or disclosed the insulation configuration of the high-voltage section in detail.

【0004】 一般には直流高電圧発生装置の絶縁構成
の要件としては,まず第1に合成樹脂材でモールドする
場合に周囲のゼロ電位点との必要な絶縁層の厚さを保つ
ことと,第2に各部品間の絶縁沿面距離を保つことの2
つを満たすことが必要である。しかるに,目的の装置に
内蔵する形の多段倍電圧整流回路の場合には,第1の要
件は装置の側で必要な絶縁層を確保でき得るので,第2
の要件である絶縁沿面距離を保つことだけが条件とな
る。なお,第1の要件について装置の側で絶縁構成する
にしても,多段倍電圧整流回路自身の総容積と外周を小
さくすることは,装置全体の絶縁材料の必要量を減らす
のに効果的である。
In general, the requirements for the insulation configuration of a DC high-voltage generator include: first, when molding with a synthetic resin material, the thickness of an insulation layer required for the surrounding zero potential point must be maintained; 2 of keeping the insulation creepage distance between each part
It is necessary to meet one. However, in the case of a multistage voltage doubler rectifier built in a target device, the first requirement is that a necessary insulating layer can be secured on the device side.
The only condition is to keep the insulation creepage distance, which is the requirement of Even if the first requirement is insulated on the device side, reducing the total volume and outer circumference of the multistage voltage doubler rectifier itself is effective in reducing the required amount of insulating material of the entire device. is there.

【0005】[0005]

【発明が解決しようとする課題】 本発明は,多段倍電
圧整流回路において,必要な部品相互間の離隔距離を確
保しつつ総容積と外周を最小にする構造を得ることを課
題とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-stage voltage doubler rectifier circuit having a structure that minimizes the total volume and outer circumference while ensuring a necessary separation distance between components.

【0006】[0006]

【問題を解決するための手段】 前述のような問題を解
決するため、この発明は、高周波高電圧を受けて直流高
電圧を発生する多段倍電圧整流回路であって、n個(n
は自然数)のコンデンサからなる押し上げコラムと、n
個のコンデンサからなる平滑コラムと、同一方向に互い
に直列接続された2n個の整流ダイオードとからなる多
段倍電圧整流回路において、前記押し上げコラムと平滑
コラムの各コンデンサは段数が増加する方向にそれぞれ
一列に対向して配設され、前記整流ダイオードは前記押
し上げコラムと前記平滑コラムそれぞれのコンデンサの
間に位置するように配置され、前記押し上げコラムと前
記平滑コラムそれぞれの各コンデンサのリード線は互い
に他方の前記コラムとは反対側となる外側に延出され、
前記それぞれのコラムのコンデンサのリード線と前記整
流ダイオードとの接続は、対向する前記コラムの各コン
デンサの外側で行われる多段倍電圧整流回路を提供する
ものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention relates to a multi-stage voltage doubler rectifier circuit which receives a high frequency high voltage and generates a DC high voltage, and comprises n (n)
Is a natural number) capacitor and n
In a multi-stage voltage doubler rectifier circuit comprising a smoothing column composed of a plurality of capacitors and 2n rectifier diodes connected in series to each other in the same direction, each of the capacitors of the push-up column and the smoothing column is arranged in a row in the direction of increasing the number of stages. The rectifier diode is disposed so as to be located between the capacitors of the push-up column and the smoothing column, and the lead wires of the capacitors of the push-up column and the smoothing column are connected to each other. It is extended to the outside opposite to the column,
The connection between the lead wires of the capacitors of the respective columns and the rectifier diodes provides a multi-stage voltage doubler rectifier circuit performed outside the respective capacitors of the opposing columns.

【0007】[0007]

【実施例】 図1は本発明に一実施例である出力60k
Vの多段倍電圧整流回路の回路図を示し,約50kHz で波
高値3kV 程度の高周波を入力端子41,42から受けて,1
0段の多段倍電圧整流回路4によって直流−60kVの
直流高電圧を高電圧出力端子43に発生する。
FIG. 1 shows an output 60k according to an embodiment of the present invention.
Fig. 3 shows a circuit diagram of a multistage voltage doubler rectifier circuit of V. When a high frequency of about 3 kHz at about 50 kHz is received from input terminals 41 and 42,
A zero-stage multi-stage voltage doubler rectifier circuit 4 generates a DC high voltage of DC-60 kV at a high voltage output terminal 43.

【0008】 多段倍電圧整流回路4の構成部品は,コ
ンデンサC1,C2...,C10からなる平滑コラムと,コンデン
サK1,K2...,K10からなる押し上げコラムと,ダイオード
D1,D2...,D20とからなる。コンデンサはいずれも小さい
円板状のセラミックコンデンサで,各リード線は各円板
状のそれぞれ両面に一方向に引き出されている。
The components of the multi-stage voltage doubler rectifier circuit 4 include a smoothing column including capacitors C1, C2,..., C10, a push-up column including capacitors K1, K2,.
D1, D2 ..., D20. Each of the capacitors is a small disk-shaped ceramic capacitor, and each lead wire is drawn out in one direction to both surfaces of each disk.

【0009】 図2は本発明に係る多段倍電圧整流回路
の配置図であって,入力端子41,42 に近い側のほぼ2段
目までを図示してある。そして(a) には上方からの見た
図を,(b) には入力端子41,42 の側から見た図を,(c)
には押し上げコラムのコンデンサK1,K2...,K10の側から
見た図をそれぞれ示してある。
FIG. 2 is a layout diagram of the multi-stage voltage doubler rectifier circuit according to the present invention, and shows up to almost the second stage near the input terminals 41 and 42. (A) shows the view from above, (b) the view from the input terminals 41 and 42, (c)
, K10, K2,..., K10 of the push-up column are shown from the side.

【0010】 図2(a) に示すように,平滑コラムのコ
ンデンサC1,C2...と押し上げコラムのコンデンサK1,K
2...はそれぞれxの幅で互いに平行に対向して配設され
る。このときいずれのコンデンサC1,C2...K1,K2...のリ
ード線も,これら対向する幅xの外側に向けて引き出さ
れる。コンデンサC1については,P点では入力端子41と
ダイオードD1のカソードとが接続される。またR点では
コンデンサC1の一端とダイオードD2のアノードとダイオ
ードD3のカソードとが接続される。(ダイオードD2につ
いては図2(b) (c) をも参照する。)
As shown in FIG. 2A, capacitors C1, C2,... Of the smoothing columns and capacitors K1, K
Are arranged to face each other in parallel with a width of x. At this time, the leads of any of the capacitors C1, C2 ... K1, K2 ... are drawn out to the outside of the opposed width x. At the point P, the input terminal 41 of the capacitor C1 is connected to the cathode of the diode D1. At point R, one end of the capacitor C1, the anode of the diode D2, and the cathode of the diode D3 are connected. (See also FIGS. 2 (b) and (c) for diode D2.)

【0011】 押し上げコラムについても同様である。
コンデンサK1については,その一端は入力端子42に接続
され,もう一端はQ点でダイオードD1のアノードとダイ
オードD2のカソードとコンデンサK2の一端とが接続され
る。またS点ではコンデンサK2の一端とダイオードD3の
アノードとダイオードD4のカソードとが接続される。
The same applies to the push-up column.
One end of the capacitor K1 is connected to the input terminal 42, and the other end is connected at point Q to the anode of the diode D1, the cathode of the diode D2, and one end of the capacitor K2. At the point S, one end of the capacitor K2 is connected to the anode of the diode D3 and the cathode of the diode D4.

【0012】 このように構成された多段倍電圧整流回
路4においては,各コンデンサのリード線は,平滑コラ
ムのコンデンサC1,C2...と押し上げコラムのコンデンサ
K1,K2...いずれも対向する幅xの外側に向けて引き出さ
れて,その外側の場所P,Q,R,S等においてのみ電
気的接続がされるため,全ての部品の相互絶縁は特別に
行うことなく,自動的に絶縁条件が満足されることにな
る。
In the multi-stage voltage doubler rectifier circuit 4 configured as described above, the leads of each capacitor are connected to the capacitors C1, C2,.
K1, K2 ... are all drawn out toward the outside of the opposite width x, and electrical connection is made only at the outside locations P, Q, R, S, etc. The insulation conditions are automatically satisfied without any special action.

【0013】 以上,電気的接続についての必要条件の
説明を行ったが,物理的配置については,図2(c) に側
面を示すように対向するダイオードD1,D2の幅寸法yを
小さくするように,各部品を相互にずらせたり,斜めに
したりして寸法yを小さくすることができる。
Although the necessary conditions for the electrical connection have been described above, the physical arrangement is such that the width y of the opposing diodes D1 and D2 is reduced as shown in the side view of FIG. In addition, the size y can be reduced by shifting or skewing the parts.

【0014】 押し上げコラムと平滑コラムとの相互距
離が確保されると,等価的相互静電容量もある程度減少
する。この相互静電容量は,多段倍電圧整流回路の昇圧
効率を抑制する作用があり,できるだけ小さくすること
が望ましいのであるが,本発明による多段倍電圧整流回
路では,その値を抑えるのに有効である。
When the mutual distance between the push-up column and the smooth column is ensured, the equivalent mutual capacitance is reduced to some extent. This mutual capacitance has an effect of suppressing the boosting efficiency of the multi-stage voltage doubler rectifier circuit, and it is desirable that the mutual capacitance be as small as possible. However, in the multi-stage voltage doubler rectifier circuit according to the present invention, it is effective to suppress the value. is there.

【0015】 なお以上の製造過程において,電気部品
の半田付けについては,尖りがないように丸い仕上がり
にする。また,どの工程においても部品には作業員の手
の油脂,ほこり,水分などが付着しないように注意した
り,樹脂モールド絶縁する直前には清浄工程,乾燥工程
を施す必要がある。これらの工程において本発明の構造
では,接続部が外側に位置するため容易に正確な作業が
できる。
In the above-described manufacturing process, the soldering of the electric components is made round so as not to have sharp edges. In any process, it is necessary to take care that no oil, grease, dust, moisture, etc. adhere to the parts of the parts, and to perform a cleaning process and a drying process immediately before insulating the resin mold. In these steps, in the structure of the present invention, since the connection portion is located outside, accurate work can be easily performed.

【0016】[0016]

【発明の効果】 本発明は以上述べたような特徴を有し
ており,多段倍電圧整流回路の各接続部が構成体の外側
になり,相互絶縁の条件については自ずから大部分が満
足する。特別な絶縁支持部材など必要とせず経済的であ
る。そして予定されるその後の樹脂モールド工程まで充
分に自立できるだけの自己保持力を有する。また接続部
が外側に位置するため総容積・外周を最小にでき,絶縁
物の必要量を最小にすることができる。したがって経済
的で確実に小型軽量な高電圧発生装置を製造することが
できる。
The present invention has the features as described above, and each connection part of the multi-stage voltage doubler rectifier is outside the structural body, and the condition of mutual insulation is naturally satisfied for the most part. It is economical because no special insulating support member is required. And it has a self-holding force enough to be self-supporting until a scheduled subsequent resin molding process. Further, since the connection portion is located on the outside, the total volume and outer circumference can be minimized, and the required amount of insulator can be minimized. Therefore, a small and lightweight high-voltage generator can be manufactured economically and reliably.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る−60kV出力の多段倍電圧整流
回路の一実施例の回路図を示す。
FIG. 1 shows a circuit diagram of an embodiment of a -60 kV output multi-stage voltage doubler rectifier circuit according to the present invention.

【図2】本発明にかかる多段倍電圧整流回路の一実施例
の配置図を示す。
FIG. 2 is a layout diagram of an embodiment of a multi-stage voltage doubler rectifier circuit according to the present invention.

【符号の説明】[Explanation of symbols]

4…多段倍電圧整流回路 41,42…入力端子 43…
高電圧出力端子 C1,C2,...,C10 …平滑コラム K1,K2,...,K10 …押し上げコラム
4: Multi-stage voltage doubler rectifier circuit 41, 42 ... Input terminal 43 ...
High voltage output terminals C1, C2, ..., C10 ... Smoothing columns K1, K2, ..., K10 ... Push-up columns

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 実開 平1−115783(JP,U) 実開 平1−120792(JP,U) 実開 昭63−4163(JP,U) (58)調査した分野(Int.Cl.7,DB名) H02M 7/10 ──────────────────────────────────────────────────続 き Continued on the front page (56) References JP-A 1-115783 (JP, U) JP-A 1-1120792 (JP, U) JP-A 63-4163 (JP, U) (58) Survey Field (Int.Cl. 7 , DB name) H02M 7/10

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】高周波高電圧を受けて直流高電圧を発生す
る多段倍電圧整流回路であって、n個(nは自然数)の
コンデンサからなる押し上げコラムと、n個のコンデン
サからなる平滑コラムと、同一方向に互いに直列接続さ
れた2n個の整流ダイオードとからなる多段倍電圧整流
回路において, 前記押し上げコラムと平滑コラムの各コンデンサは段数
が増加する方向にそれぞれ一列に対向して配設され、 前記整流ダイオードは前記押し上げコラムと前記平滑コ
ラムそれぞれのコンデンサの間に位置するように配置さ
れ、 前記押し上げコラムと前記平滑コラムそれぞれの各コン
デンサのリード線は互いに他方の前記コラムとは反対側
となる外側に延出され、 前記それぞれのコラムのコンデンサのリード線と前記整
流ダイオードとの接続は、対向する前記コラムの各コン
デンサの外側で行われ、 ることを特徴とする多段倍電圧整流回路。
1. A multi-stage voltage doubler rectifier circuit for generating a DC high voltage by receiving a high frequency high voltage, comprising: a push-up column including n (n is a natural number) capacitors; and a smoothing column including n capacitors. A multi-stage voltage doubler rectifier circuit composed of 2n rectifier diodes connected in series in the same direction, wherein the capacitors of the push-up column and the smoothing column are arranged in a row facing each other in a direction of increasing the number of stages; The rectifier diode is disposed so as to be located between the capacitors of the push-up column and the smoothing column, and the lead wires of the capacitors of the push-up column and the smoothing column are opposite to each other. The connection between the lead wire of the capacitor of each column and the rectifier diode extends outward. The multi-stage voltage doubler rectifier circuit is performed outside each capacitor of the corresponding column.
JP27864996A 1996-09-30 1996-09-30 Multi-stage voltage doubler rectifier circuit Expired - Lifetime JP3266810B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27864996A JP3266810B2 (en) 1996-09-30 1996-09-30 Multi-stage voltage doubler rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27864996A JP3266810B2 (en) 1996-09-30 1996-09-30 Multi-stage voltage doubler rectifier circuit

Publications (2)

Publication Number Publication Date
JPH10108466A JPH10108466A (en) 1998-04-24
JP3266810B2 true JP3266810B2 (en) 2002-03-18

Family

ID=17600229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27864996A Expired - Lifetime JP3266810B2 (en) 1996-09-30 1996-09-30 Multi-stage voltage doubler rectifier circuit

Country Status (1)

Country Link
JP (1) JP3266810B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117294124A (en) * 2023-05-16 2023-12-26 国家电投集团科学技术研究院有限公司 DC-DC converter

Also Published As

Publication number Publication date
JPH10108466A (en) 1998-04-24

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