JP3263365B2 - Liquid crystal display panel and inspection method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) as a pixel switching element.
The present invention relates to an active matrix type liquid crystal display panel using an active element such as a sistor, and more particularly to a liquid crystal display panel capable of inspecting pixel defects in a state of an array substrate before a liquid crystal injection step.

[0002]

2. Description of the Related Art A polysilicon thin film transistor (hereinafter referred to as p
An active matrix type liquid crystal display panel using a switching element of -SiTFT) has a feature that a driving circuit can be built in on the same substrate as a pixel transistor included in a display portion. There are two driving methods for a liquid crystal display panel including such a TFT matrix array, a dot sequential driving method and a line sequential driving method.

[0003] By the way, in recent years, the screen size of liquid crystal panels has been increased,
With the increase in definition, the number of pixels of one liquid crystal panel becomes extremely large, and accordingly, the number of TFTs as pixel switching elements and wiring of image signal lines and scanning signal lines also become extremely large. For this reason, pixel defects due to TFT defects, disconnection and short-circuiting of source lines and other line defects, and other line defects frequently occur. Therefore, it is necessary to inspect TFT defects and line defects such as source lines in advance. In addition, inspection for pixel defects and the like is required to be performed in a state before a liquid crystal injection step, which is a final step in manufacturing a liquid crystal display panel, that is, in a state of a TFT array substrate. This is because, if a pixel defect is inspected after the liquid crystal injection step, when a pixel defect is found, the entire liquid crystal display panel must be discarded, which lowers the manufacturing yield.

However, in the prior art, in the state of the TFT array substrate, an efficient inspection method has hardly been established, and only an inspection for disconnection, short circuit, and other line defects can be performed. When inspecting pixel defects, a liquid crystal display panel is manufactured by injecting liquid crystal between the TFT array substrate and the opposing substrate, a voltage is applied to the liquid crystal display panel, and the liquid crystal display operation is visually observed to observe the pixel defects. Had been checked for presence. However, since the inspection is performed after the liquid crystal display panel is manufactured, when a pixel defect is found as described above, the entire liquid crystal display panel into which liquid crystal has been injected is discarded, and the manufacturing yield is reduced.

Therefore, in a state before the liquid crystal injection step,
There is a demand for detecting a pixel defect, and a pixel defect inspection apparatus disclosed in Japanese Patent Application Laid-Open No. 7-77553 has been proposed to respond to the request. This pixel defect inspection apparatus uses a scanning shift register which forms a part of a driving circuit built in the TFT array substrate in a state of the TFT array substrate before a liquid crystal injection step, thereby sequentially forming one pixel at a time. It is configured to inspect for pixel defects.

[0006]

However, in the above-mentioned conventional example, it can be used only for a liquid crystal display panel of a dot-sequential drive system in which a scanning shift register is incorporated in a drive circuit. There is a problem that can not be used for.

Further, even in the case of a liquid crystal display panel of a dot sequential driving system, in the case of a liquid crystal display panel with a built-in driving circuit in which a driving circuit is formed on an array substrate, an inspection is performed using the above-described inspection apparatus of the prior art. However, a problem arises in terms of reliability. This is because there is a possibility that some failure occurs in the drive circuit itself in the process of forming the drive circuit on the substrate, and the occurrence of the failure in the drive circuit itself lowers the reliability of the pixel defect inspection. Because it becomes.

Further, in the above-mentioned prior art, since pixel defects are sequentially inspected for each pixel, there is a problem that the inspection time is long and the inspection efficiency is poor.

In view of the above problems, it is an object of the present invention to provide a liquid crystal display capable of performing a pixel defect inspection in a state of an array substrate before a liquid crystal injecting step, and performing an inspection in a short time. Is to provide a panel.

[0010]

According to a first aspect of the present invention, a plurality of image signal lines and a plurality of scanning signal lines are formed in a matrix, and A scanning signal line driving circuit for transmitting a scanning signal to the scanning signal line; and an image signal to the image signal line, comprising: an array substrate on which pixel switching elements are respectively formed near intersections between the image signal line and the scanning signal line. An image signal line driving circuit for transmitting the image signal is constituted by a semiconductor layer formed on the array substrate, and in a liquid crystal display panel that performs display by a line-sequential driving method, in one end of the image signal line, The image signal line driving circuit is connected, and a pixel defect inspection circuit for inspecting a pixel defect is connected to the other end of the image signal line, and the pixel defect inspection circuit includes the array. Characterized in that it is constituted by a semiconductor layer formed on the substrate.

By providing the pixel defect inspection circuit as described above, a liquid crystal display panel of a line-sequential drive system can be used.
Inspection of pixel defects can be performed before the liquid crystal injection step. Therefore, it is possible to eliminate waste of manufacturing a defective liquid crystal display panel by injecting liquid crystal into an array substrate containing pixel defects, thereby improving the yield of final products.

When inspecting for pixel defects, the array substrate is driven by applying an image signal voltage in the state of the array substrate before the liquid crystal injection step, and the electric charge accumulated in each pixel on one scanning signal line is determined. Is extracted for each scanning signal line as a discharge voltage waveform (or discharge current waveform), and the extracted discharge voltage waveform is inspected by a pixel defect inspection circuit to determine the presence or absence of a pixel defect. In this manner, pixel defects can be inspected for each scanning signal line.
Inspection efficiency can be improved as compared with the conventional example in which pixel defect inspection is performed for each pixel.

According to a second aspect of the present invention, in the liquid crystal display panel according to the first aspect, the pixel defect inspection circuit is provided for each image signal line, and one scanning signal line is provided via each image signal line. The discharge current value or the discharge voltage value of the electric charge stored in the capacitance of each pixel read out for each pixel is compared with a predetermined reference value, and converted to a logical value according to the magnitude relation and output. And a logic circuit for calculating and outputting a logical product of outputs from the respective comparison circuits.

With the above-described configuration, for example, when the discharge voltage value is equal to or higher than a predetermined reference value, the comparison circuit outputs a logic “1”.
Is output, and when the discharge voltage value is less than a predetermined reference value,
The comparison circuit outputs logic “0”. Therefore, the output of the logic circuit becomes logic "1" only when the discharge voltage value is equal to or higher than the predetermined reference value for all the pixels read out for each scanning signal line. If at least one pixel has a discharge voltage value lower than a predetermined reference value, the output of the logic circuit becomes logic “0”. On the other hand, when a pixel defect is present, almost no charge is accumulated in the pixel capacitance, so that the discharge voltage value is lower than the reference value. When no pixel defect exists, sufficient charge is accumulated in the pixel capacitance. , The discharge voltage value becomes equal to or higher than the reference value. Thus, the presence or absence of a pixel defect can be detected based on the logic state of the output of the logic circuit.

According to a third aspect of the present invention, in the liquid crystal display panel of the second aspect, a signal processing circuit for increasing a pulse width of an output pulse of the comparison circuit is provided between the comparison circuit and the logic circuit. It is characterized by having.

As described above, the inspection accuracy can be improved by increasing the pulse width of the output pulse of the comparison circuit.

According to a fourth aspect of the present invention, a plurality of image signal lines and a plurality of scanning signal lines are formed in a matrix.
A scanning signal line driving circuit for transmitting a scanning signal to the scanning signal line; and an image signal line for transmitting an image to the scanning signal line. An image signal line driving circuit for transmitting a signal is constituted by a semiconductor layer formed on the array substrate, and in a liquid crystal display panel performing display by a dot sequential driving method, one end of the image signal line is The image signal line drive circuit is connected, and a pixel defect inspection circuit for inspecting a pixel defect is connected to the other end of the image signal line. It has the same circuit configuration as the image signal line drive circuit, and is constituted by a semiconductor layer formed on the array substrate.

As described above, since the pixel defect inspection drive circuit has the same circuit configuration as the image signal line drive circuit, if the image signal line drive circuit does not operate normally due to a defect, the pixel defect inspection drive circuit is switched to the image signal line drive circuit. It can be diverted to a line drive circuit, and the yield of final products can be improved.

[0019]

(Embodiment 1) FIG. 1 is a perspective view showing a part of a liquid crystal display panel according to Embodiment 1, and FIG. 2 is a circuit diagram of the liquid crystal display panel according to Embodiment 1. is there. The liquid crystal display panel according to the present invention is a so-called drive circuit built-in type liquid crystal display panel in which a drive circuit for driving a liquid crystal display unit is formed integrally with an array substrate. This liquid crystal display panel is a line sequential drive type liquid crystal display panel. The liquid crystal display panel is an array substrate 1
1, a counter substrate 12 facing the array substrate 11, and a liquid crystal layer 13 sandwiched between the array substrate 11 and the counter substrate 12. Both the array substrate 11 and the opposing substrate 12
It is a transparent glass substrate. On the surface of the array substrate 11,
The plurality of scanning signal lines V1, V2,...
Are arranged corresponding to the intersections of a plurality of image signal lines S1, S2,..., Sn (the image signal lines are collectively referred to by reference numeral S) and the image signal lines S and the scanning signal lines V. Low-temperature polysilicon thin film transistors (hereinafter abbreviated as TFTs) 15 as a plurality of pixel switching elements
And a plurality of pixel electrodes 16 are formed. TFT
The 15 source electrodes 15a are connected to the image signal lines S,
The gate electrode 15b of the TFT 15 is connected to the scanning signal line V. The drain electrode 15c of the TFT 15 is
It is commonly connected to the liquid crystal capacitance CLc and the storage capacitance Cstg. The plurality of TFTs 15 and the plurality of pixel electrodes 1
6, the image signal line S and the scanning signal line V constitute the liquid crystal display unit 5.

Further, an image signal line driving circuit 17 for transmitting an image signal through an image signal line S and a TF through a scanning signal line V are provided around the liquid crystal display unit 5 on the array substrate 11.
A scanning signal line driving circuit 18 for transmitting a scanning signal to the gate electrode 15b of T15 and a pixel defect inspection circuit 20 for detecting a pixel defect are provided. Image signal line drive circuit 1
Reference numeral 7 is connected to one end of the image signal line S, and the pixel defect inspection circuit 20 is connected to the other end of the image signal line S. Here, the pixel defect to be inspected by the pixel defect inspection circuit 20 is a functional defect of the TFT 15, and therefore, the corresponding pixel of the TFT 15 is not displayed at all, or even if it is displayed, the pixel has a predetermined brightness. This means that there is no such thing.

Also, on the inner surface of the counter substrate 12,
An opposing electrode 21 made of a transparent conductive film is formed, and a polarizing plate 22 is formed on the outer surface of the opposing substrate 12. A polarizing plate 23 is formed on the outer surface of the array substrate 11. Note that the pixel defect inspection circuit 20,
The image signal line driving circuit 17 and the scanning signal driving circuit 18
This is a so-called built-in circuit formed on the array substrate 11 in the same manufacturing process as the TFT 15.

FIG. 3 is a circuit diagram showing a specific configuration of the image signal line drive circuit and the pixel defect inspection circuit. The image signal line driving circuit 17 includes a shift register circuit 30, an image data line unit 31, a sample and hold circuit 32, a buffer circuit 33, and analog switches a1, a2,.
and an. The outline of the line sequential driving display operation by the image signal line driving circuit 17 having such a configuration will be described. First, a dot timing signal from the shift register circuit 30 is supplied to the sample and hold circuit 32. Accordingly, the sample hold circuit 32 sequentially samples and holds the image signal sent from the image data line unit 31 in accordance with the dot timing signal. When the sample and hold circuit 32 finishes sampling and holding the data for one scan, the data for one scan is sent from the sample and hold circuit 32 to the buffer circuit 33. After that, the buffer circuit 33 takes each of the image signal lines S1, S over a time corresponding to one horizontal scanning period.
Data is simultaneously written to 2,..., Sn. Such an operation is sequentially performed for each scanning signal line, and one frame of image data is written.

The pixel defect inspection circuit 20 includes comparison circuits B1, B2,..., B provided for each image signal line S.
n (when the comparison circuits are generically indicated by reference numeral B),
.., An-1 (the AND circuit is generally indicated by reference numeral A). One input terminal of the AND circuit A1 is connected to the output line of the comparison circuit B1, and the other input terminal of the AND circuit A1 is connected to the output line of the comparison circuit B2. One input terminal of each of the AND circuits A2, A3,..., An-1 is an output of a preceding AND circuit (for example, the preceding AND circuit related to the AND circuit An-1 means the AND circuit An-2). Connected to the lines and AND circuits A2, A3,
, An-1 are connected to the comparison circuit B, respectively.
, B3,..., Bn. The comparison circuit B includes a discharge voltage value of the electric charge stored in the capacitance of each pixel read out for each scanning signal line V via each image signal line S, a predetermined reference voltage value Vref, , And outputs a logical value corresponding to the magnitude relation. For example, when the discharge voltage value is equal to or higher than the reference voltage value Vref, the comparison circuit B outputs logic "1", and when the discharge voltage value is less than the reference voltage value Vref, the comparison circuit B outputs logic "0". Note that a configuration may be adopted in which a discharge current value is read instead of the discharge voltage value.

The outline of the pixel defect inspection by the pixel defect inspection circuit 20 will be described.
In the state of the FT array substrate, the TFT array substrate is driven by applying an image signal voltage, and the electric charge accumulated in each pixel on one scanning signal line V in the array substrate is set as a discharge voltage waveform to form one scanning signal line. It is taken out for each V and inspected by the pixel defect inspection circuit 20 to recognize the presence or absence of a pixel defect.

FIG. 4 is a timing chart for explaining the operation of the pixel defect inspection. A specific operation of the pixel defect inspection will be described with reference to FIG. First, as shown in FIG. 4A, a selection pulse is applied to the scanning signal line V1,
All the TFTs 15 connected to the scanning signal line V1 are turned on for a predetermined period. In synchronization with this, the analog switches a1, a2, a3,..., An are turned on. As a result, as shown in FIG. 4B, the image signal voltage held in the sample hold circuit 32 is read out to the image signal line S, and is associated with each of the TFTs 15 connected to the scanning signal line V1. The capacitors (corresponding to the liquid crystal capacitor CLc and the storage capacitor Cstg) are simultaneously charged. still,
As the image signal voltage used here, the highest level voltage in the used image signal voltage range is used so that the liquid crystal capacitance CLc associated with the TFT 15 is sufficiently charged.

Next, all the TFTs 15 connected to the scanning signal line V1 and the analog switches a1, a2, a
3, a4,..., An are turned off to maintain the charged state. Then, the analog switches a1, a2, a3, a
While only 4,..., An are in the OFF state, only the TFT 15 is turned on again. Thereby, as shown in FIG. 4C, the charges accumulated in each pixel are discharged through the image signal line S, and a discharge voltage (or discharge current) is given to the pixel defect inspection circuit 20.

The pixel defect inspection circuit 20 diagnoses the presence or absence of a pixel defect by the following signal processing. That is, in the comparison circuit B constituting the pixel defect inspection circuit 20, the reference voltage value Vref is compared with the discharge voltage value given via the image signal line S, and as shown in FIG. When the voltage value is equal to or higher than the reference voltage value Vref, the comparison circuit B outputs a logical value "1", and when the discharge voltage value is lower than the reference voltage value Vref, the comparison circuit B outputs a logical value "0". Then, the AND condition of the output of the comparison circuit B becomes AND circuit A1,
A2,..., An-1 are output from the detection terminal DIV. Therefore, all the TFTs on one scanning signal line V
When the pixel 15 is normal, the output of the detection terminal DIV becomes logic "1". When the TFT 15 has a defect (corresponding to the case where there is a pixel defect), the output of the detection terminal DIV becomes logic "0". . Therefore, the presence or absence of a pixel defect can be detected based on the logic state of the output of the detection terminal DIV.

For example, the scanning signal line V2 and the image signal line S2
It is assumed that the performance of the TFT 15 with respect to the intersection of is poor. All TFs connected to the scanning signal line V1
Since the performance of T15 is good, the peak of the discharge voltage becomes equal to or higher than the reference value Vref, as shown in FIG. Therefore, the outputs of the comparison circuits B1, B2,.
As shown in (d), the logic becomes "1". Therefore, the output of the detection terminal DIV becomes logic “1” as shown in FIG. Next, when the inspection of the TFT 15 connected to the scanning signal line V2 is performed, as shown in FIG. 4C, the peak of the discharge voltage for the image signal line S2 becomes lower than the reference value Vref. Therefore, only the output of the comparison circuit B2 is logic “0”, and the remaining comparison circuits B1, B3,.
The output of n has a logical value “1”. Therefore, the detection terminal DI
The output of V becomes logical "0" as shown in FIG. In this way, the detection terminal D
The logic level of the output of the IV changes, which makes it possible to recognize the presence or absence of a pixel defect.

The reference value Vref may be set depending on whether or not the TFT has a charging capability up to a voltage level allowable as the performance of the TFT. For example, when a state in which a corresponding pixel is not displayed at all due to a performance defect of a TFT is considered as a pixel defect, the reference value Vref may be set to substantially zero level. Further, when a state in which the corresponding pixel is not displayed at all but is less than the predetermined brightness is considered as a pixel defect, the voltage level at which the predetermined brightness is obtained is set to the reference value V.
Set it to ref. Thus, the reference value Vref
Is set arbitrarily, it is possible to inspect pixel defects within a range allowable as the performance of the TFT. Further, in the first embodiment, the pixel defect can be inspected for each scanning signal line, and the inspection can be performed in a shorter time as compared with the conventional example in which the inspection is performed for each pixel. Improvement can be achieved.

In order to specifically recognize the presence or absence of a pixel defect, for example, the detection terminal DIV may be connected to the input terminal I1 of the light emitting device 25 as shown in FIG. When the output of the detection terminal DIV is logic “1”, the transistor Tr is turned on, a forward current flows through the light emitting diode D, and the light emitting diode 26 is turned on. When the output of the detection terminal DIV is logic “0”, the transistor Tr is turned off, no current flows through the light emitting diode 26, and the light emitting diode 26 does not turn on. Thus,
The presence or absence of a pixel defect can be visually recognized.
Instead of the light emitting diode 26, the presence or absence of a pixel defect may be recognized by a buzzer or the like. Further, in the above embodiment, although the two-input AND circuit is used in the pixel defect inspection circuit 20, a configuration using three or more multi-input AND circuits may be employed.

(Embodiment 2) FIG. 6 is a circuit diagram showing a configuration of a pixel defect inspection circuit of a liquid crystal display panel according to Embodiment 2. In the second embodiment, a pixel defect inspection circuit 20A is used in place of the pixel defect inspection circuit 20 in the first embodiment. This pixel defect inspection circuit 20A
Are compared with the comparison circuits B1, B2,..., Bn and the AND circuits A1,
A2,..., An, a T-type flip-flop FF
1, FF2,..., FFn (T-type flip-flops are generally denoted by reference numeral FF) are interposed. With such a configuration, the pulse width of the input signal to the AND circuit A can be increased as described later.

Here, the operating functions of the T-type flip-flop FF shown in FIG. 7 are shown in Table 1.

[Table 1]

In FIG. 7 and Table 1, the symbol “*” means inversion. For example, * PR means inversion of PR, * CL means inversion of CL, and * Q means inversion of Q.

Next, the operation of the pixel defect inspection circuit according to the second embodiment will be described with reference to Table 1 above. The inspection process for pixel defects is basically the same as in the first embodiment. However, due to the configuration in which the T-type flip-flop FF is provided in the pixel defect inspection circuit, the inspection processing in the pixel defect inspection circuit 20A is different from that of the pixel defect inspection circuit 20. First, similarly to the first embodiment, the scanning signal line V
1, a selection pulse is applied to turn on all the TFTs 15 connected to the scanning signal line V1 for a predetermined time. In synchronization with this, the analog switches a1, a2, a3,.
An is turned on, an image signal being sampled and held is input, and the liquid crystal capacitance CLc associated with each TFT 15 is simultaneously charged through the image signal line S. Next, the TFTs 15 and the analog switches a1, a2, a
3, a4,..., An are turned off to maintain the charged state, and then the TFTs 15 are turned on again, so that the discharge voltage (or discharge current) of the electric charge accumulated in each pixel is changed to a pixel defect inspection circuit. 20A, the scanning signal line V
The defect of the pixel related to No. 1 is detected. If it is determined that there is no pixel defect on the scanning signal line V1, the same processing as the inspection processing on the scanning signal line V1 is performed.
2, and if there is no pixel defect, similar inspection processing is sequentially performed on the scanning signal lines V3, V4,.

FIG. 8 is a timing chart showing the operation of the pixel defect inspection circuit 20A. FIG. 8 shows only the waveforms related to the scanning signal line V1 and the flip-flop FF1. Hereinafter, for convenience of explanation, operations related to the scanning signal line V1 and the flip-flop FF1 will be mainly described. The TFT connected to the scanning signal line V1 as described above
Assume that the liquid crystal capacitance CLc associated with No. 15 is discharged as shown in FIG. 8C, and the output of the image signal line B1 is in a state as shown in FIG. 8D. Here, the output of the image signal line B1 corresponds to the count input T of the flip-flop FF1. Therefore, as shown in FIG.
1, the count input T of the flip-flop FF1
Changes from logic “0” to logic “1”. On the other hand, at this time t1, as shown in FIG.
Is a logic "1" and the clear * CL is also a logic "1" as shown in FIG.
F1 is in the toggle operation state according to Table 1. Therefore, the output Q
Becomes * Qn-1. Here, Qn-1 is the Q before time t1.
Therefore, as shown in FIG. 8 (g), Qn-
1 is logic "0". Therefore, * Qn-1 is logical "1"
The output Q changes to logic "1" at time t1, which is the rising edge of the count input T, as shown in FIG. Then, the logic “1” is maintained until time t2. It should be noted that even when the count input T changes from logic "1" to logic "0", the output Q does not change from Table 1. Then, at time t2, the clear * CL changes from logic "1" to logic "0", so that the output Q at this time is a toggle operation from Table 1. Therefore, as shown in FIG. 8 (g), the output Q changes from logic “1” to logic “0” at time t2.
Changes to

The thus obtained output Q shown in FIG.
And the count input T shown in FIG.
It is recognized that the pulse width of the output Q is larger than that of the count input T. The same applies to the outputs of the other flip-flops FF2,... FFn. Thus, between the comparison circuit B and the AND circuit A, T
With the configuration in which each of the flip-flops FF is interposed, the pulse width of the input signal to the AND circuit A can be increased, and the pixel defect inspection circuit 20A
Accuracy can be improved. Note that the subsequent signal processing of the AND circuit A is the same as in the first embodiment. If all the TFTs on one scanning signal line V are normal, the output of the detection terminal DIV changes to logic “1”. When there is a pixel defect, the output of the detection terminal DIV becomes logic “0”,
The presence or absence of a pixel defect can be identified.

(Embodiment 3) FIG. 9 is an overall configuration diagram of a liquid crystal display panel according to Embodiment 3. The third embodiment is similar to the first embodiment and corresponding parts are denoted by the same reference numerals. Although the liquid crystal display panel of the line-sequential drive system is used in the first embodiment, the difference is that the liquid crystal display panel of the point-sequential drive system is used in the third embodiment. Therefore, in the third embodiment, an image signal line driving circuit 17A for dot sequential driving is used instead of the image signal line driving circuit 17 in the first embodiment. The image signal line driving circuit 17A includes analog switches a1, a2, a3,..., An n connected to the image signal lines S1, S2, S3,.
And the analog switches a1, a2, a3,.
And a scanning shift register 50 for sequentially sending pulses for turning ON the dot timing signal. The pixel defect inspection circuit 20B according to the third embodiment includes analog switches a12, a22, a32, a42,..., An2 connected to the respective image signal lines S, and analog switches a12, a22, a32, a42,
, And a shift register 62 that sequentially sends pulses for turning on an2 by a dot timing signal, and has the same circuit configuration as the image signal line driving circuit 17A.

Next, an inspection process for a pixel defect according to the third embodiment will be described. The pixel defect inspection in the third embodiment is basically the same as that in the first embodiment. However, since the liquid crystal display panel of the third embodiment is driven by the dot sequential driving method, the TFT
5 in that the electric charge accumulated in the liquid crystal capacitance CLc related to No. 5 is detected as a discharge voltage waveform by the pixel defect inspection circuit 20B for each pixel. This will be specifically described below. For example, when the scanning signal line V1 is selected and the shift register 50 is scanned while the gate voltage is being applied, the analog switches a1, a2, a3, a4,.
State. Thereby, the image data is sequentially derived to the image signal lines S1, S2,..., Sn via the data line D1, and the liquid crystal capacitance CLc associated with the TFT 15 forming each corresponding pixel is charged. Next, the analog switches a1, a2, a3, a4,..., An are turned off.

Next, the shift register 62 constituting the pixel defect inspection circuit 20B is scanned, and the electric charge accumulated in the liquid crystal capacitance CLc associated with each TFT 15 is discharged. That is, by scanning the shift register 62 and sequentially turning on the analog switches a12, a22, a32, a42,..., An2 in this order, the switches a1
2, a22, a32, a42,..., An2, the charge of each pixel is taken out from the data line D2 as a discharge voltage waveform (or discharge current waveform). It should be noted that the specific determination of the presence / absence of a pixel defect is performed, for example, in a conventional example (Japanese Patent Laid-Open No.
No. 3) may be used. That is, the discharge voltage waveform extracted from the data line D2 may be input to the pixel defect inspection device to inspect the presence or absence of a pixel defect.

As described above, in order to write an image signal from one end of the image signal line S and read out the written image signal from the other end of the image signal line S, for example, a selection pulse is applied. Scanning signal line V and image signal line S
If a line defect exists between the intersection with the pixel defect inspection circuit 20B and the pixel defect inspection circuit 20B, it can be inspected together. For example, when a line defect is present at the position of the mark X on the image signal line S2 shown in FIG. 9, the discharge voltage waveform is used for inspecting a pixel defect in the first row and the second column. The circuit 20B cannot read out the data, and the voltage waveform taken out from the data line D2 becomes almost 0 level, and a line defect is detected. In this manner, not only pixel defects but also line defects can be inspected, so that inspection efficiency can be improved. This is because, if a line defect is detected during the inspection process for a pixel defect, the TFT array substrate having the line defect is discarded, and there is no need to perform a pixel defect inspection thereafter.

In the third embodiment, since the pixel defect inspection drive circuit 20B has the same circuit configuration as the image signal line drive circuit 17A, if the image signal line drive circuit 17A does not operate normally due to a defect, the pixel defect inspection drive circuit 20B Driving circuit 20 for defect inspection
B has a specific effect that it can be diverted to the image signal line driving circuit 17A.

Next, the scanning signal line driving circuit 18 and the image signal line driving circuit 1 used in the first to third embodiments will be described.
7, 17A and pixel defect inspection circuits 20, 20A, 20
A method for manufacturing a polysilicon thin film transistor constituting a built-in circuit such as B will be described with reference to FIG. First, a base insulating film 101 made of a material such as SiO2 is formed on a glass substrate 100 made of a translucent glass having a strain point of 670 ° C. by a method such as a normal pressure CVD method at a temperature of 450 ° C. . The thickness of the base insulating film 101 is, eg, 2000 °.

After the formation of the base insulating film 101, a-S
i: A semiconductor material film 102 ′ made of H (a compound of amorphous silicon and hydrogen) is formed to a predetermined thickness (for example, 500 °) by a plasma CVD method, and further formed into a predetermined shape by a lithography process. Perform patterning. A predetermined condition (for example, a processing temperature of 450 ° C. and a processing time of 60 ° C.) is applied to the patterned semiconductor material film 102 ′.
Min) to perform dehydrogenation treatment. The purpose of this step is to prevent ablation of the semiconductor material film 102 'due to desorption of hydrogen during crystallization.

After dehydrogenation, the semiconductor material film 102 'is crystallized by a method such as irradiation with a XeCl excimer laser having a wavelength of 380 nm, and the semiconductor material film 102'
The semiconductor layer 102 is made of Si (see FIG. 10A).

Next, on the semiconductor layer 102, for example, SiO 2
The gate oxide film 103 is formed at a temperature of 450 ° C. by atmospheric pressure CVD to a very thin film thickness of, for example, 1000 °. After the gate oxide film 103 is formed, the conductor film 104 ′ made of Al or the like is formed to a predetermined thickness (for example, 3000).
The film is formed by a method such as sputtering so as to satisfy Å). Then, the conductor film 104 ′ is patterned into a predetermined shape by a lithography process using an Al etching solution.
4 (see FIG. 10B).

Next, impurities such as phosphorus and boron are implanted into ions on both sides of the semiconductor layer 102 by using the gate electrode 104 as a mask by a technique such as an ion doping method (self-aligned structure). Thereby, the semiconductor layer 10
In FIG. 2, a channel region 102a is formed in the center, and a source region 102b and a drain region 102c are formed on both sides of the channel region 102a (see FIG. 10C).

Next, an interlayer insulating layer 105 made of SiO 2 or the like is formed on the gate oxide film 103 by a predetermined thickness (for example, 400 μm).
0 °), and the gate electrode 104 is covered with the formed interlayer insulating film 105. The interlayer insulating film 105 is formed by, for example, a normal pressure CVD method at a temperature of 450 ° C. (see FIG. 10D).

Next, the interlayer insulating film 105 and the gate insulating film 1
03 and the source region 1 using a lithography process.
02b, a contact hole 106 reaching the drain region 102c is formed. After forming the contact hole 106, a second film such as a Ti film or an Al film is formed on the interlayer insulating film 105.
A conductive film 107 ′ made of a stacked body of various types of conductors is formed. The conductive film 107 'is formed by, for example, sputtering. The thickness of the Ti film is suitably, for example, 1000 °, and the thickness of the Al film is, for example, 7000 °.
The contact hole 106 is completely filled with the conductive film 107 'thus formed. Further, the conductive film 10
The source / drain electrodes 107 are formed by patterning 7 'into a predetermined shape by a lithography process using a BCl3 / Cl2 based gas (see FIG. 10E).

Next, a passivation film 10 serving as a protective film
8 is formed. Subsequently, under the conditions of a processing temperature of 350 ° C., a deuterium gas flow rate of 300 sccm, and an RF power of 800 W,
Perform a plasma hydrogenation treatment for 2 hours. Finally, in a lithography process, the passivation film 108 is patterned in a predetermined shape, whereby a thin film transistor forming a built-in drive circuit is completed.

In the first to third embodiments, a low-temperature polysilicon TFT is used, but a TFT made of another single-crystal or polycrystalline semiconductor material may be used.

The TFTs constituting the matrix of the liquid crystal display unit 5 are amorphous TFTs, and built-in circuits (scanning signal line driving circuit 18, image signal line driving circuits 17, 17A and pixel defect inspection circuits 20, 20A, 20B). Constituent T
The display unit and the built-in drive circuit may be constituted by TFTs using different materials, such as a FT being a low-temperature polysilicon TFT.

[0052]

As described above, according to the present invention, it is possible to detect a pixel defect in a liquid crystal display panel of a line-sequential drive system in a state of an array substrate before a liquid crystal injection step. Therefore, waste of manufacturing a liquid crystal display panel having a pixel defect can be eliminated, and the yield of a final product can be improved.

Further, since a pixel defect can be inspected for each scanning signal line, the inspection efficiency can be improved as compared with the conventional example in which inspection is performed for each pixel.

Further, in the liquid crystal display panel of the dot sequential driving system, the pixel defect inspection drive circuit has the same circuit configuration as the image signal line drive circuit. The drive circuit for defect inspection can be diverted to the image signal line drive circuit, and the yield of final products can be improved.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a part of a liquid crystal display panel according to a first embodiment.

FIG. 2 is a circuit diagram of the liquid crystal display panel according to Embodiment 1.

FIG. 3 is a circuit diagram showing a specific configuration of an image signal line driving circuit and a pixel defect inspection circuit used in the liquid crystal display panel according to the first embodiment.

FIG. 4 is a timing chart illustrating an operation of a pixel defect inspection according to the first embodiment;

FIG. 5 is a circuit diagram of a light emitting device.

FIG. 6 is a circuit diagram showing a configuration of a pixel defect inspection circuit according to a second embodiment.

FIG. 7 is a circuit diagram of a T-type flip-flop.

FIG. 8 is a timing chart showing the operation of the pixel defect inspection circuit according to the second embodiment.

FIG. 9 is an overall configuration diagram of a liquid crystal display panel according to a third embodiment.

FIG. 10 is a sectional view showing a manufacturing process of a polysilicon TFT.

[Explanation of symbols]

 11: Array substrate 12: Counter substrate 13: Liquid crystal layer 15: TFT 16: Pixel electrode 17, 17A: Image signal line 18: Scanning signal line 20, 20A, 20B: Pixel defect inspection circuit A1, A2,... 1: AND circuit B1, B2,..., Bn: comparison circuit V1, V2,..., Vn: scanning signal line S1, S2,.

Continuation of the front page (56) References JP-A-10-214065 (JP, A) JP-A-7-77553 (JP, A) JP-A-4-288588 (JP, A) JP-A-3-18891 (JP) JP-A-2-154292 (JP, A) JP-A-63-52121 (JP, A) JP-A-9-15645 (JP, A) JP-A-5-10999 (JP, A) 5-265026 (JP, A) JP-A-5-297826 (JP, A) JP-A-7-104709 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/136 G02F 1/1345 G02F 1/13 G02F 1/133

Claims (7)

(57) [Claims] 1. An array substrate in which a plurality of image signal lines and a plurality of scanning signal lines are formed in a matrix, and a pixel switching element is formed at a position near each intersection of the image signal lines and the scanning signal lines. A scanning signal line driving circuit for transmitting a scanning signal to the scanning signal line, and an image signal line driving circuit for transmitting an image signal to the image signal line, a built-in circuit comprising a semiconductor layer formed on the array substrate In a liquid crystal display panel that performs display by a line-sequential driving method, the image signal line driving circuit includes an analog switch capable of electrically separating each image signal line from the image signal line driving circuit. A pixel defect inspection circuit for inspecting pixel defects is provided at an end of the image signal line opposite to the image signal line driving circuit. The pixel defect inspection circuit is a built-in circuit composed of a semiconductor layer formed on the array substrate, and is provided for each image signal line, and one scanning signal is provided via each image signal line. The discharge current value or the discharge voltage value of the electric charge stored in the capacitance of each pixel read for each line is compared with a predetermined reference value, and converted to a logical value according to the magnitude relation. A liquid crystal display panel, comprising: a comparison circuit that outputs a signal; and a logic circuit that calculates a logical product of outputs from the respective comparison circuits and outputs the calculated logical product as a signal indicating the presence or absence of a pixel defect. . 2. The method according to claim 1, wherein the comparing circuit and the logic circuit include:
2. The liquid crystal display panel according to claim 1, further comprising a T-type flip-flop for increasing a pulse width of an output pulse of the comparison circuit. 3. A light emitting device to which an output from the logic circuit is supplied and which can recognize the presence or absence of a pixel defect by the presence or absence of a light emitting state, or a buzzer device which can recognize the presence or absence of a pixel defect by the presence or absence of sound. 3. The liquid crystal display panel according to claim 1, further comprising a single connectable detection terminal. 4. An array substrate in which a plurality of image signal lines and a plurality of scanning signal lines are formed in a matrix and a pixel switching element is formed at a position near each intersection of the image signal lines and the scanning signal lines. A scanning signal line driving circuit for transmitting a scanning signal to the scanning signal line, and an image signal line driving circuit for transmitting an image signal to the image signal line, a built-in circuit comprising a semiconductor layer formed on the array substrate Wherein the image signal line driving circuit includes an analog switch connected to each image signal line, and a shift register for sequentially turning on each analog switch. A pixel defect inspection circuit for inspecting a pixel defect is connected to an end of the image signal line opposite to the image signal line driving circuit. The pixel signal inspection circuit is provided with the image signal line drive circuit so that the image signal line drive circuit can be driven in a dot-sequential manner in place of the image signal line drive circuit when the image signal line drive circuit is defective and does not operate normally. A liquid crystal display panel having the same circuit configuration, wherein the pixel defect inspection circuit is a built-in circuit composed of a semiconductor layer formed on the array substrate. 5. The inspection method for a liquid crystal display panel according to claim 1, wherein the analog switch is turned on, and the image signal line driving circuit and the scanning signal line driving circuit perform line sequential driving. Writing an image signal to all pixels connected to one scanning signal line, turning off the analog switch, reading the image signal written to the pixel to a pixel defect inspection circuit,
Inspecting the presence / absence of a pixel defect by a pixel defect inspection circuit and outputting a signal indicating the presence / absence of the pixel defect. A method for inspecting a liquid crystal display panel, comprising: 6. The inspection method for a liquid crystal display panel according to claim 3, wherein the analog switch is turned on, and one scan is performed by line sequential driving by an image signal line driving circuit and a scanning signal line driving circuit. Writing an image signal to all pixels connected to the signal line; turning off the analog switch, reading the image signal written to the pixel to a pixel defect inspection circuit,
A step of outputting a signal indicating the presence or absence of a pixel defect to a detection terminal by inspecting the presence or absence of a pixel defect by a pixel defect inspection circuit, and connecting a light emitting device or an audio device to the detection terminal in advance, A step of enabling the presence or absence of a pixel defect to be recognized based on the presence or absence of light emission or the presence or absence of sound of a buzzer device, and a method for inspecting a liquid crystal display panel. 7. The method for inspecting a liquid crystal display panel according to claim 4, wherein one of the plurality of scanning signal lines is selected, and during the selection period, a signal in the image signal line driving circuit is selected. The shift register is scanned to sequentially turn on the analog switches in the image signal line driving circuit, the image signals are sequentially output to the plurality of image signal lines, and the image signals are sequentially output for each pixel connected to the selected scanning signal line. Writing the voltage, turning off the analog switches in the image signal line driving circuit, and scanning the shift register in the pixel defect inspection circuit to sequentially turn on the analog switches in the pixel defect inspection circuit; Reading the image signal voltage sequentially for each pixel connected to the selected scanning signal line, and outputting the read image signal voltage to an external inspection device. Inspection methods.