JP3262853B2 - Driving circuit and driving method for liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a liquid crystal display device.
And it relates to a driving method, in particular, the input image data
Multiple data electrodes for split display in liquid crystal display devices
Equipped with a driver that uses memory to order the image data
And supply them in parallel to each data electrode driver
In both cases, the data electrode driver is operated in parallel to
In a driving circuit of a liquid crystal display device for driving a liquid crystal display device, even if the number of data electrode drivers increases, it can be dealt with only by increasing the number of bits of an address counter corresponding to a memory, and less hardware is required. The present invention relates to a driving circuit of a liquid crystal display device capable of generating a memory address in a small amount.

In recent years, high image quality of liquid crystal display devices has been demanded, and therefore, it is necessary to display image data sent at a speed higher than the maximum operation speed of a liquid crystal driver in a driving circuit on a liquid crystal display panel. It is necessary to realize a driving circuit for a liquid crystal display device with a smaller circuit scale and at a lower cost.

[0003]

2. Description of the Related Art FIG. 9 shows a configuration diagram of a driving circuit of a conventional liquid crystal display device. As shown in FIG. 1, in the drive circuit of the conventional liquid crystal display device, when image data Data faster than the maximum operation speed of the liquid crystal driver is displayed on the liquid crystal display panel 1, for example, the data electrode driver 13-
The liquid crystal display panel 1 was driven by operating 1 to 13-3 in parallel.

For this reason, the image data is rearranged using the memory 5 as shown in FIG.
By providing three latch circuits 4-1 to 4-3 on the output side of the device, serial-parallel conversion of image data is performed.
Data electrode driver 13-1 divided into three blocks
To 13-3 can be operated in parallel.

In order to rearrange the image data as shown in FIG. 10, three address counters 111, 112, and 1 equal to the number of divided blocks of the data electrode driver are generated by an address counter 107 for generating an address of the memory 5.
13 are operated in parallel. That is, the first address counter 111 counts up from the address a where the data A1 is stored, the second address counter 112 counts up from the address b where the data B1 is stored, and the third address counter 113 stores the data C1. From the address c to be counted in parallel. In parallel with this, an address for the memory 5 is switched by the selector 115 based on a selection control signal (generated by a timing control unit not shown), and the contents of the memory are output. And latches 4-1 to 4
If the latch timing of -3 is synchronized with the selection control signal, the image data applied to the data electrode drivers 13-1 to 13-3 becomes as shown in FIG.

[0006]

As described above, in the conventional driving circuit of the liquid crystal display device, it is necessary to provide, as the address counter for generating the address of the memory, the same number of address counters as the number of divided blocks of the data electrode driver. As the number of divided blocks of the data electrode driver increases, a corresponding number of address counters are required, and the circuit and operation control of a selector for selecting a plurality of address counter outputs are also complicated. Was.

[0007] Accordingly, the present invention provides a method for inputting image data.
Are displayed on a liquid crystal display.
Equipped with a pole driver and use memory for the data order of image data
And supply them in parallel to each data electrode driver
At the same time, the data electrode driver
In a driving circuit of the liquid crystal display device that drives the liquid crystal display device, the number of divided displays in the liquid crystal display device, that is,
Even if the number of data electrode drivers increases, it can be dealt with only by increasing the number of bits of the address counter corresponding to the memory,
It is an object of the present invention to provide a driving circuit of a liquid crystal display device capable of generating a memory address with a smaller amount of hardware.

[0008]

FIG. 1 is a diagram illustrating the principle of the present invention. In order to solve the above-mentioned problem, a driving circuit for a liquid crystal display device according to the first aspect of the present invention includes
Divided into multiple blocks, and each of the divided blocks
A plurality of data electrode drivers to be driven and the liquid crystal display
A memory for storing image data to be displayed on the panel,
When storing the image data in the memory,
A write address counter for generating an address,
Reads image data with a dress from the memory
Read address to generate the read address when
And a counter, wherein each of the data electrode drivers is
The image data based on the read / write address.
From the memory and operate each of the data electrode drivers in parallel
Driving the liquid crystal display device to drive the liquid crystal display panel.
Wherein the write address counter is
1st counting to the same number as the number of outputs of the data electrode driver
A counter and the first counter being the data electrode driver.
1st assert signal when counting to the same number as
And outputs the first counter to reset the first counter.
And count up based on the first assertion signal,
A second counter counting up to the same number as the number of blocks;
The count value of the second counter is stored in the upper bit and the first
The count value of the counter is used as the lower bit, and the first counter and the
And writing based on the count value in the second counter.
Write address generation means for generating a write address
And the read address counter.
Is a third counter counting up to the same number as the number of blocks.
And the third counter counts up to the same number as the number of blocks.
Output the second assert signal and output the third
A second decoder for resetting the counter, the second assertion,
Count up based on the signal, and
A fourth counter for counting up to the same number as the number of outputs of Iva,
The count value of the third counter is stored in the upper bit and the fourth
The count value of the counter is used as the lower bit, and the third counter and
And reading based on the count value in the fourth counter.
Read address generation means for generating an output address;
Is provided . The driving method of the liquid crystal display device of the invention described in claim 2, a plurality of liquid crystal display panel
Divided into blocks and drive each of the divided blocks
Image data to be displayed on the liquid crystal display panel.
Storing the data in the memory; and storing the image in the memory.
Generate write address when storing image data
A write address generation process; and
To generate a read address when reading from memory
And an overflow address generation process.
The image data is stored in the memo based on the read address.
The LCD panel is displayed for each block.
A method for driving a liquid crystal display device driven by columns,
In the write address generation process, the data electrode
1st counting process that repeats counting every number of outputs
And the data electrode driver by the first counting process.
1st assertion signal when counting up to the same number of outputs as
And a first signal output process for outputting the first assertion signal
Count up based on
And a second counting process for counting by
The higher-order bit of the counted value and the first counting process
The count value counted by the above is set as the lower bit,
Before being counted by the counting process and the second counting process
Write to generate a write address based on the count value
Address generation processing, the read address
In the generation process, it repeats every number equal to the number of blocks.
A third counting process for counting and counting, and the third counting process.
When counting up to the same number as the number of blocks, the second
A second signal output process for outputting a second
Counts up on the basis of the
A fourth counting process for counting up to the same number as the number of outputs of the driver;
The count value counted by the third counting process is used for the upper bit.
And the count value counted by the fourth counting process.
The third counting process and the fourth counting as lower bits
Read based on the count value counted by the processing
Read address generation processing for generating an address.
And it has a non-configuration.

[0009]

In the driving circuit for a liquid crystal display device according to the present invention, as shown in FIG. 1, a write address counter 7 for generating a write address of the memory 5 is provided with a data electrode.
An n-ary cow that counts repeatedly for each number of outputs of the driver
7nc, the same number as the number of outputs of the data electrode driver.
Output the first assertion signal when counting
And a counter based on the first assertion signal.
The LCD panel into multiple blocks.
By the m-ary counter 7mc counting to the same number as the divided number
Configured, the upper q bits (q address writes output from m counter 7Mc (smallest integer p exceeding log2 n) lower p bits of write addresses output from the n-ary counter 7nc exceeds the log2 m Generate the write address as the smallest integer).

A read address counter 9 for generating a read address of the memory 5 is provided with a liquid crystal display panel.
Repeated count for the same number as the number of divisions into multiple blocks
9-m counter to be counted, divided into a plurality of blocks
2nd assert signal when counting up to the same number as the divided number
And a second assertion signal for outputting the second assertion signal.
Count up based on the
An n-ary counter 9nc counts up to the same number as the number of outputs.
The read address is generated using the output from the m-ary counter 9mc as the upper q bits of the read address and the output from the n-ary counter 9nc as the lower p bits of the read address.

Therefore, since the image data can be read based on the upper bits in the address given when the image data is stored in the memory, the image data can be rearranged based on the upper bits. That is, the address bits corresponding to the divided block number m of the data electrode driver 3-1 to 3-m corresponds to the upper q bits, out of each of the data electrode driver 3-1 to 3-m
Since the address bits corresponding to the power factor n correspond to the lower p bits, the number of address counters corresponding to the data electrode driver of each block is provided as in the prior art, and the image data is rearranged without being selected by the selector. Can be performed. As a result, even if the number m of divided blocks of the data electrode driver is increased, it can be dealt with only by increasing the number of bits of the m-ary counter 7mc and the m-ary counter 9mc for counting m , and a smaller amount of hardware Thus, a driving circuit of a liquid crystal display device capable of generating a memory address can be realized. In the driving method of the liquid crystal display device according to the second aspect of the present invention, as shown in FIG. 1, the output from the n-ary counter 7nc is set to the lower p bits (p is log2 The output from the m-ary counter 7mc is the upper q bits (q is log2 m).
), And the read address is generated by using the output from the m-ary counter 9mc as the upper q bits and the output from the n-ary counter 9nc as the lower p bits. Therefore, since the image data can be read based on the upper bits in the address given when the image data is stored in the memory, the image data can be rearranged based on the upper bits, and the data electrode driver can be divided. Even if the number m of blocks increases, it can be dealt with only by increasing the number of bits of the m-ary counter 7mc and the m-ary counter 9mc that count m, and can drive a liquid crystal display device that can generate a memory address with a smaller amount of hardware. A circuit can be realized.

[0012]

Next, an embodiment according to the present invention will be described with reference to the drawings. FIG. 2 shows a configuration diagram of a driving circuit of a liquid crystal display device according to one embodiment of the present invention. In the figure, the same reference numerals are given to the portions that overlap with FIG. 9 (conventional example).

In FIG. 2, the driving circuit of the liquid crystal display device of the present embodiment is divided into 1, 3 (m = 3) blocks of the liquid crystal display panel to be driven, and n blocks (n is an arbitrary number) are provided. Data electrode drivers 3-1 to 3-3 for driving data lines of positive integers, where n = 120.
And from the image data Data to the data electrode driver 3
It comprises an image data processing unit for generating image data to be supplied to -1 to 3-3. For simplicity, a gate electrode driver for driving a gate line and a timing control unit for generating a control signal group for each component from a clock signal, a horizontal synchronization signal, and a vertical synchronization signal are not shown. .

The image data processing section includes two memories 5-1 and 5-2 for holding the image data converted into digital image data for a predetermined period, and writing in the first memory M1 and the second memory M2. A write address counter 7 for generating a write address;
-1 and a read address counter 9 for generating a read address in reading from the second memory 5-2, a write address counter 7 output during writing, and a read address counter 9 output during reading to select the first memory 5-1 and the second memory 5-2. Selectors 11-1 and 11-2 serving as addresses of the second memory 5-2, and a first memory 5-1
And input buffers 13i1 and 13i to the second memory 5-2
3i2; output buffers 13o1 and 13o2 to the first memory 5-1 and the second memory 5-2;
And latch circuits 4-1 to 4-3 for latching the outputs of the first and second memories 5-2. The input buffers 13i1 and 13i2 and the output buffer 13o1
And OE terminals of 13o2 are output enable signal terminals.

The selection of the selectors 11-1 and 11-2 is controlled by read / write signals R / W and R / W #, and the signal R / W # is an inverted signal of the signal R / W. That is, when the first memory 5-1 writes data, the second memory 5-2 reads data, and the first memory 5-2 reads data.
When the memory 5-1 reads data, the second memory 5-
2 is data writing. With such a configuration, continuous data can be handled by always operating the first memory 5-1 and the second memory 5-2.

FIG. 3 shows a write address counter 7.
FIG. In the figure, a write address counter 7 includes an n-ary counter 7nc and an n-ary counter 7n
a decoder 7d1 that outputs a signal that becomes asserted when c counts up to n (= 120); an m counter 7mc that counts up to m (= 3) based on the output of the decoder 7d1;
a decoder 7d2 that outputs a signal that becomes an assert when the m counter 7mc counts up to m.
Note that the n-ary counter 7nc and the m counter 7mc operate with a clock CLOCK at the same speed as the image data Data, and the outputs of the decoders 7d1 and 7d2 are
These are reset inputs for the n-ary counter 7nc and the m counter 7mc, respectively.

With such a configuration, the n-ary counter 7n
The output from c is the lower 7 bits ADD of the write address.
1 (W) to ADD7 (W), and outputs from the m counter 7mc are the upper 2 bits ADD8 (W) of the write address,
A write address is generated as ADD9 (W).

FIG. 4 shows a read address counter 9.
FIG. In the figure, a read address counter 9 has an m-ary counter 9mc and an m-ary counter 9m
a decoder 9d2 that outputs a signal that becomes an assert when c counts to m (= 3); an n counter 9nc that counts to n (= 120) based on the output of the decoder 9d2;
The decoder 9d1 outputs a signal that becomes an assert when the n counter 9nc counts to n.
Note that the m-ary counter 9mc and the n counter 9nc operate with a clock CLOCK having the same speed as the image data Data, and the outputs of the decoders 9d1 and 9d2 are
These are reset inputs of the n counter 9nc and the m-ary counter 9mc, respectively.

With such a configuration, the n counter 9nc
From the lower 7 bits of the read address ADD1
(R) to ADD7 (R), the output from the m-ary counter 9mc is read as the upper 2 bits ADD8 (R) of the read address,
A read address is generated as ADD9 (R).

FIG. 5 is a diagram for explaining how the write address and the read address are counted. Since the write addresses are counted as shown in FIG. 5A, the memory maps of the first memory 5-1 and the second memory 5-2 are as shown in FIG. 6A. Further, since the read addresses are counted as shown in FIG. 5B, the image data is rearranged as shown in FIG. Modification of Embodiment In the above-described embodiment, as shown in FIG. 6A, an empty area is generated between data areas for the data electrode drivers 3-1 to 3-3. If the circuit shown in FIG. 7 is added to the write addresses ADD1 (W) to ADD9 (W) and the read addresses ADD1 (R) to ADD9 (R),
This empty area can be eliminated as in the memory map shown in FIG. 6B, and the first memory 5-1 and the second memory 5-
2 can reduce the storage capacity.

FIG. 7 shows a write address ADD1 (W).
FIG. 21 is a configuration diagram of a circuit added to ADD9 (W). Upper bits ADD8 (W), ADD9 of write address
(W) is decoded by the decoder 21 to generate a selection signal indicating which data electrode driver 3-1 to 3-3 corresponds to the address, and a constant value is selected by the selector 22 based on the selection signal. Then, a constant value is subtracted from the write addresses ADD1 (W) to ADD9 (W) by the subtractor 23, and new write addresses ADR1 (W) to A
The configuration is DR9 (W).

The constant value to be subtracted is "0" for the data electrode first driver 3-1 and the data electrode second driver 3
−2, “Δx1”, data electrode third driver 3
“−x2” for −3. Where p is log
_{When the} smallest integer exceeding ₂ n and the smallest integer exceeding log ₂ m, Δx1 = 2 ^p −n−1, Δxr = r ×
Δx1 (r = 2, 3,..., Q). In this example, n = 1
20, m = 3, p = 7, q = 2, Δx1 =
9, Δx2 = 18.

Read addresses ADD1 (R) to ADD
9 (R) is similarly configured to generate new read addresses ADR1 (R) to ADR9 (R).

As another modified example, the first memory 5-1
And the second memory 5-2, as shown in FIG.
It is also possible to configure with AM5 '. Further, the configuration of the write address counter 7 and the read address counter 9 can be realized using a PLD (Programmable Logic Device), a gate array, a custom IC, or the like.

For example, when using a PLD, it can be realized by the following simple logical formula. Here, the symbol & is logical product, + is addition, <is less than, == is equivalent,

Is a logical sum, # is negation,. d represents the data input of the D flip-flop. (1) Write address counter 7 Qn. d = (Qn + 1) & (Qn <n): Indicates generation of lower bits of the address, and counts up while the counter outputs Q1 to Qp are less than n.

CARRY = (Qn == n): When the counter outputs Q1 to Qp become equal to n, the signal CARRY is asserted. Qm. d = CARRY & (Qm + 1)

(CARRY #) & Qm: Indicates the generation of the upper bits of the address. When the signal CARRY is asserted, the counter outputs Qp + 1 to Qp + q are counted up, and when the signal CARRY is negated, the counter output Qp
+1 to Qp + q are unchanged. (2) Read address counter 9 Qm. d = (Qm + 1) & (Qm <m): represents the generation of the upper bits of the address, and the counter outputs Qp + 1 to Qp +
Count up while q is less than m.

CARRY = (Qm == m): When the counter outputs Qp + 1 to Qp + q become equal to m, the signal CA
RRY is asserted. Qn. d = CARRY & (Qn + 1)

(CARRY #) & Qn: Indicates the generation of the lower bits of the address. When the signal CARRY is asserted, the counter outputs Q1 to Qp are counted up, and the signal C
When ARRY is negated, the counter outputs Q1 to Qp do not change.

[0031]

As described above, according to the first aspect of the present invention, the write address counter 7 stores
N-ary that repeatedly counts the same number as the output number of the electrode driver
The counter 7nc is equal to the number of outputs of the data electrode driver.
Output the first assertion signal when counting up to the first
And a decoder based on the first assertion signal.
Up and split the LCD panel into multiple blocks.
M-ary counter 7mc that counts up to the same number as the divided number
Write the output from the n-ary counter
Lower p bits (where p is the smallest integer exceeding log2 n)
Number), the output from the m counter is higher than the write address
q bits (q is the smallest integer exceeding log2 m)
To generate a write address, and
Address counter and the LCD panel
M-ary power that repeatedly counts the same number as the number of divisions
Counter 9mc, the number of divisions into the plurality of blocks, and
A second assertion signal is output when counting up to the same number.
2 decoder, and based on the second assert signal,
Counts up and equals the number of outputs of the data electrode driver
And the output from the m-ary counter is the upper q bits of the read address,
By generating the read address using the output from the n-ary counter as the lower p bits of the read address,
Since the image data can be read based on the upper bits in the address given when the image data is stored in the memory, the image data can be rearranged based on the upper bits. That is, the address bits corresponding to the number m of divided blocks of the data electrode driver correspond to the upper q bits, and the address bits corresponding to the output number n of each data electrode driver correspond to the lower p bits. Therefore, the number of address counters corresponding to the data electrode drivers of each block is provided as in the prior art, and the image data can be rearranged without selection by the selector, and the number m of divided blocks of the data electrode driver increases. However, it is possible to provide a driving circuit for a liquid crystal display device that can cope with only by increasing the number of bits of an m-ary counter that counts m and that can generate a memory address with a smaller amount of hardware. . According to the second aspect of the present invention, a write address counter is provided.
Data 7 is repeated by the same number as the number of outputs of the data electrode driver.
N-ary counter 7nc for counting
1st assert signal when counting to the same number as
And a first assertion signal
Count up based on the number of LCD panels
M cows counting up to the same number as the number of divisions into blocks
The output from the n-ary counter.
Lower p bits of the write address (p exceeds log2n)
Write the output from the m counter.
The upper q bits of the dress (q is the minimum over log2 m
Generate the write address as an integer), and also read
Address counter, and the LCD panel
M-base that repeatedly counts the same number as the number of divisions into blocks
Counter 9mc, the number of divisions into the plurality of blocks
Output the second assertion signal when counting up to the same number as
Based on a second decoder and the second assertion signal
Count up to match the number of outputs of the data electrode driver.
It is composed of an n counter 9nc that counts up to
The output from the counter to the upper q bits of the read address,
The output from the n counter is the lower p bits of the read address.
By generating the read address as a
Address assigned when storing image data in memory
Reads image data based on upper bits in
Can be. Therefore, the number of address counters corresponding to the data electrode drivers of each block is provided as in the prior art, and the image data can be rearranged without selection by the selector, and the number m of divided blocks of the data electrode driver increases. However, it is possible to provide a driving circuit for a liquid crystal display device that can cope with only by increasing the number of bits of an m-ary counter that counts m and that can generate a memory address with a smaller amount of hardware. .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of a driving circuit of the liquid crystal display device according to one embodiment of the present invention.

FIG. 3 is a detailed configuration diagram of a write address counter in the embodiment.

FIG. 4 is a detailed configuration diagram of a read address counter in the embodiment.

FIGS. 5A and 5B are explanatory diagrams of generation of write and read addresses. FIG. 5A shows a write address, and FIG. 5B shows a read address.

FIG. 6A is a memory map in an embodiment, and FIG. 6B is a memory map in a modification.

FIG. 7 is a configuration diagram of an additional circuit in a modified example.

FIG. 8 is a configuration diagram of a memory according to another modification.

FIG. 9 is a configuration diagram of a driving circuit of a conventional liquid crystal display device.

FIG. 10 is an explanatory diagram of rearrangement of image data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display panel 3-1 to 3-m ... Data electrode driver 4-1 to 4-m ... Latch circuit 5, 5-1 and 5-2 ... Memory 7 ... Write address counter 7nc ... N-ary counter 7mc ... m Counters 7d1, 7d2, 9d1, 9d2... Decoder 9... Read address counter 9mc... M-ary counter 9nc... N Counters 11-1, 11-2... Selectors 13i1, 13i2. Selector 23 ... Subtractor n ... Number of data lines m ... Number of blocks of data electrode driver Data ... Image data OE ... Output enable signal terminal R / W, R / W # ... Read / write signal CLOCK ... Clock ADD1 (W) ~ ADD9 (W): Write address ADR1 (W) to ADR9 ( ) ... write address ADD1 (R) ~ADD9 (R) ... read address

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 505 G09G 3/20

Claims (2)

(57) [Claims] 1. A liquid crystal display panel is divided into a plurality of blocks.
And a plurality of data to drive each of the divided blocks
Data driver and an image to be displayed on the liquid crystal display panel.
A memory for storing image data; and
Write to generate a write address when storing data
Address counter and an image to which the address is assigned.
Read address when reading image data from the memory
And a read address counter for generating addresses.
Each of the data electrode drivers receives the read address.
Obtaining the image data from the memory based on
By operating the data electrode drivers in parallel, the liquid crystal display
A drive circuit of a liquid crystal display device for driving a channel, wherein the write address counter counts up to the same number as the number of outputs of the data electrode driver.
One counter, and the first counter determines the number of outputs of the data electrode driver.
Outputs the first assertion signal when counting to the same number
A first decoder for resetting the first counter, counting up based on a first assert signal,
A second counter for counting up the lock as many upper bit and the first count value of the second counter
The count value of the counter is set as a lower bit, and the first counter
And based on the count value in the second counter
Write address generation means for generating a write address
And a third counter , wherein the read address counter counts up to the same number as the block number, and a third counter counts up to the same number as the block number.
Sometimes, the second assertion signal is output to the third counter
And a second decoder for resetting the count value based on the second assert signal.
4th counting up to the same number as the output number of the data electrode driver
A counter, and counting the count value of the third counter with upper bits and the fourth bit.
Setting the count value of the counter as a lower bit;
And based on the count value in the fourth counter
Read address generation means for generating a read address
Driving circuit of the liquid crystal display device characterized by comprising a, the. 2. The liquid crystal display panel is divided into a plurality of blocks.
When driving each of the divided blocks,
Stores image data to be displayed on the LCD panel in memory
And storing the image data in the memory.
Write address to generate write address when
Generation processing and reading the image data from the memory
Read address generator to generate read address when
The read address at the time of driving.
Acquiring the image data from the memory based on
Liquid crystal for driving the liquid crystal display panel in parallel for each block
A method of driving a display device, wherein in the write address generation process, counting is repeated for each of the same number as the number of outputs of a data electrode driver.
A first counting process, and an output of the data electrode driver by the first counting process.
Outputs the first assert signal when the count reaches the same number as the power factor.
A first signal output process to be performed, and counting up based on the first assertion signal.
A second counting process for counting up to the same number as the number of blocks, and a count value counted by the second counting process as an upper bit.
And the count value counted by the first counting process.
The first counting process and the second counting as lower bits
Write based on the count value counted by processing
It includes a write address generation process of generating an address, the, in the read address generation process, third counting processing for counting repeatedly a number of blocks and each equal
And the third counting process counts up to the same number as the number of blocks.
A second signal that outputs a second assertion signal when counted
Output processing and counting up based on the second assertion signal,
4th counting up to the same number as the output number of the data electrode driver
The counting process and the count value counted by the third counting process are performed in the upper bits.
And the count value counted by the fourth counting process.
The third counting process and the fourth counting
Read based on the count value counted by the processing
Method of driving a liquid crystal display device which comprises a read address generation process of generating an address, the.