JPS62988A - Display of image data - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an image processing system, and in particular, to an image processing system that processes image data stored in an image memory on a CRT or liquid crystal display.

6. Concerning the display method when displaying on a monitor such as a plasma display (Background) In an image processing device, the number of pieces of information about the image to be processed is greater than the number of pixels (number of pixels) of the monitor displaying the image.
To accommodate this, some devices have image memory for display that is larger in size than the number of pixels on the monitor.

For example, it has a display memory whose size is four times the number of pixels of the monitor, and normally only 174 areas of this memory are displayed and various processes are performed. Some of this processing involves only one side, while others involve the entire image.

In the latter case, partial images are generally displayed sequentially by changing addresses, but since the entire image cannot be grasped at once, accurate processing may not be possible. Therefore, in order to perform image processing quickly and accurately, it is desirable to reduce the size of the image on the display memory and display it on a monitor so that the entire image can be grasped with the naked eye.

(Prior Art) A simple means of displaying image data on a reduced image monitor from image data stored in memory for normal display or normal reproduction is to thin out the read addresses of the memory.

However, for the memory used for monitor display, since the access time T of the memory element is long with respect to the time timing t of monitor display of one pixel data, the number of parallels N such that tXN≧T is calculated and Write N pixel data in parallel to N display memories, read N pixel data in parallel from N display memories, and read it in parallel.
Within xN time, the images are assembled in series in the original chronological order and supplied to the monitor as one normal image display.

In order to obtain 172 reduced images of the original image as a monitor display, it is necessary to thin out the data every other pixel in the horizontal direction, as shown by diagonal lines in FIG. Two methods have been proposed to perform this thinning process.

The first method is to access the display memory, which has a short access time, in half the normal readout cycle, and
Read data for N pixels and perform parallel/direct conversion (parallel/direct conversion)
Serial conversion; hereinafter abbreviated as P/S conversion. ) at the time of
Every other one, about one cycle.

This is a method of thinning out unnecessary data so that it becomes data for 8 pixels.

The second type is equipped with two display memories that store the same image data at the same address, and at the same time it is read out from one memory as, for example, LSB (lower bit of O) "0" of the address, and at the same time the next address (e.g. address L)
SB is set to 1'') from the other memory, and the read data for 2N pixels is transferred to P/
This is a method of thinning out unnecessary data so that there is data for 8 pixels during S conversion.

(Problems to be Solved by the Invention) However, the first method requires a memory element with a short access time, making the device expensive.

The second method also requires the provision of a plurality of display memories, which is extremely uneconomical. Furthermore, a 1/4 reduced image,
Obtaining a 1/8 scaled image is more uneconomical than obtaining a 1/2 scaled image.

(Object of the Invention) Therefore, the present invention does not require a memory element with a short access time, and does not require an extra display memory.
The main purpose is to obtain a reduced image that is faithful to the original image on a 72-inch screen, in other words, to obtain a reduced image that is faithful to the original image using a conventional display memory that is normally displayed.

(Means for solving the problem) In order to solve the problem, in the present invention, when a pixel memory is configured, memory elements are numbered sequentially from 0 to 2m-1, and at the same location of each memory element. .

When pixel data is written to the pixel memory for every 2m pieces of pixel data in a group in chronological order constituting an image and displayed on a monitor, the written pixel data is read out in parallel from one pixel memory and rearranged in chronological order. , displaying the order of pixel data by controlling the address given to the pixel memory, serial/parallel conversion, and parallel/serial conversion when writing after serial/parallel conversion, and during parallel/serial conversion after reading. Or, it is basically a reduced display.

When writing data to a memory, conventionally, time-series pixel data (2 m pieces) were written in the same location of the memilli elements (2 m pieces) in the order of the memory element number, but in the present invention, Depending on the address to access the memory element, the correspondence between the memory number and the order of time-series pixel data is changed and written. This is 5 pixels: M When reading the reduced image, 2 pixels are thinned out according to the reduction rate. In order to read out pixel data as a group, if you simply write in chronological order and memory number order, you will not be able to obtain the two pieces of data you need in one parallel read from 2m memory elements. It is.

The data written to the memory element as described above is
In order to perform normal display and reduced display, 2m pieces of data are required to be read from 2m memory elements in one parallel readout for normal display or reduced display. In order to obtain the data, each memory element is accessed by giving an independent address, and when reducing the display, the addresses where the data necessary for thinning out are stored are read simultaneously in parallel, and the read 2m pieces of data are The data is rearranged and displayed in chronological order.

Taking the case of normal display and 1/2 reduced display as an example, to describe it more specifically, the memory element address = 0.1, 2
．． 3..., 2m pixel data of the (2k)th pixel data group are stored at the (2k)th address (even address) of the memory element.
Write the pixel data order in the numerical order of the memory element, and write the 2' pixel data of the (2nd+1)th pixel data group to the (2nd+1)th address (odd address) of the memory element in the order of 1 pixel data. is the number of the memory element, 1, ○+3+2+...
, 2m-], and 2m-2.

Next, when reading pixel data in normal display, the second
k) The pixel data read from the address is output to the monitor in the order of memory element number, and the pixel data read from the (2nd +1) address is 1.0, 3 in memory element number.
,2. ..., 2m-1, 2m''-2 are output to the monitor side in this order.

When reading pixel data in 1/2 reduced display, double the vertical address and horizontal address given to the memory element as in normal display, and simultaneously read pixel data from the memory element with even symbol at an even horizontal address.

Pixel data is read from the odd-numbered memory element at a horizontal address obtained by adding 1 to the previous even-numbered horizontal address via another independent address line.

Then, the read pixel data is assembled in one chronological order by controlling m-bit address data for selecting a memory element, and output to the monitor side.

Generally, the smallest reduction ratio of an image that can be obtained by simply thinning out image data without causing image distortion using one memory element is 1/2 m.

In this case, normal display, 1/2 reduced display, 1/4 reduced display, . . . 172m reduced/JS display can be arbitrarily selected.

The order in which image data is stored in the 2° memory elements is for the lowest address 2° of the memory element (from address O to address 2m''), and at address O, the memory element number is simply stored in the order of the pixel data. Address 1
To do this, shift the pixel data order by one,
The image data is stored in the order of memory element numbers, and by shifting by one, the image data that protrudes is put into an empty memory element number by shifting by one. In this way, the data is sequentially shifted and stored up to address 2m-1.

By storing the data as described above, the image data thinned out by 5 can be read out.

The reading order is 1. In normal display, the read pixel data and pieces are arranged in the order of the image data according to the lowest address of the memory element, and in 1/2 reduced display, the horizontal and vertical addresses are Double the display, and through independent address lines, the even numbered memory elements are given fk lower address 2k (k=0.l, 2.--72) to read out pixel data, and the odd numbered For drinking, -1 is given to the lowest address 2, one pixel data is read out, and a total of two pieces of data are rearranged in the order of pixel data.

Generally, in a 2m72° (n=1+2.・m) reduced display,
Multiply the horizontal address and vertical address by twice the normal display, divide each memory element number 2n into memory element groups via an independent address line, and for every lowest address 2n, the 0th memory element in the memory element group. For the first memory element, read the pixel data read at address 0, for the first memory element, read the pixel data read at the address, and for the second memory element, read the pixel data read at the address, for a total of 2m pieces. , the pixel data is rearranged in order.

(Function) Depending on the value of the lower address 2m, the address to be accessed for each pixel memory is changed depending on the method of changing the storage order of pixel data, the display purpose (normal display/reduced display), the lower address, etc. Appropriate sequential pixel data is selected for normal display or reduced display by the method of reading out the two pixel data and the method of rearranging the pixel data according to the purpose.
Ru.

(Example) Hereinafter, the present invention will be described in more detail based on examples for 1/2 reduced display and normal display.

In the example, as shown in FIG. 3, the horizontal x vertical dimensions are
Equipped with 2048 x 2048 display memory (1),
When displaying on a CRT monitor (2) with a screen size of 1024 x 1024, normally a memory area of 1024 x 1024, which is equal to the screen size (1
Display n).

The image data stored in the display memory (1) is as follows.

For example, as shown in Figure 4, in 1 chronological order, from ○ to 22
It is assumed that the pixel data is numbered up to 22-1 and consists of 4M pixel data.

In the case of a color image display used in a color prepress system, the total information size is 4MX x 1 byte x number of colors.
Here, information on one byte in the depth direction and the number of colors representing FFu4 is not shown and will be omitted in the following description.

In FIG. 4, 4M pixel data are expressed by group numbers in chronological order and pixel position numbers in chronological order within the group.

For example, 16 squares in the upper left corner 2m...2' = 16
) is the pixel position number 0, 1, 2, . . . of the 0th group.
...16 data of 9°A, B, C, D, E, F are shown. The data group in the lower right corner shows 16 pixel data in chronological order of the 12mth group. The final data in the lower right corner shows pixel data from numbers O to F of the (2m1) group.

Below, when indicating one pixel data, group numbers 0 to (2m8+
) and nine pixel position numbers 0-F.

The image data from the 0th group to the (2m-1)th group is
It is divided into 128 groups (128×16=2048) in the horizontal direction and 2048 groups in the vertical direction, which correspond to the size of one display memory (1) (FIG. 3).

The specific structure of the display memory (1) is, as shown in FIG. 5, 16 memory elements (M) of 255K×1 focus.

..., (M) are arranged in parallel, and the memory block (MB
), and this memory block (MB) is used as 1 pin×4.

Each memory element (M) has a memory element number of 0.1 in advance.
,2. ..., E, F are given. below.

Each memory element is distinguished and designated by this number.

Each memory element (M) has an address from 0 to (12m'-1), and if image data in chronological order is stored in these addresses, the image data structure shown in FIG. In correspondence, the 16 pixel data of the nth group are stored in the same location of each memory element (M), that is, the nth address.

Figure 1 shows a 4M image, I M (1024X 102
4) shows a schematic block diagram of a reducible display system.

Circuit blocks (3), (4), (5), (6), (7)
, (8) are controlled by signals from the microprocessor (9).

The vertical address generation circuit (3) also synchronizes with the horizontal cycle signal of the CRT (2), and generates a range from 0+α to 1023+α (α is a constant set by CP TJ (9), and represents a shift value in the vertical direction, from 0 to 1023+α). It is an integer up to 1024.

When the 1/2 JR small display is displayed, addresses up to 0 (0 is set) are generated.

The horizontal address generation circuit (4) generates a signal from 0+β to 1023+β (β is CPU (9)) during the period of one horizontal opening signal.
This is a constant set by , and is an integer from 0 to 1024 representing the horizontal shift value, and generates an address up to 0 (0 is set for 1/2 reduction display).

The display memory write circuit (5) supplies a 4-bit address signal for memory element selection to the display memory (1) during writing. Image data stored on the disk (10) is written to the display memory (1) through the display memory write circuit (5). Times X (6), (7)
is activated only when a control signal indicating reduced display is applied from the microprocessor (9).

The circuit (6) doubles the vertical address generated by the vertical address generation circuit (3). The circuit (7) doubles the upper 7 bits of the horizontal address generated by the horizontal address generation circuit (4).

The P/S conversion control circuit (8) includes a horizontal address generation circuit (
4) One display memory (1) and subsequent P/S conversion circuit (11) based on the lower 4 bit address signal supplied from
control. This P/S conversion control circuit (8) operates in two different modes corresponding to normal display and reduced display according to control signals from the microprocessor (9).

The image data written in the display memory (1) consists of a total of 18 bits consisting of an 11-bit vertical address from the vertical address generation circuit (3) and a horizontal address of the upper 7 bits from the horizontal address generation circuit (4). accessed with

This 18-bit address is given to each memory element (M) shown in FIG. 5, and data for one pixel is read out from all memory elements (M). readout period)
is 320ns (memory element access time is 320ns
20 ns or less).

The parallel 16 pixel data read out from the display memory (]) is converted into serial data using a 20 ns clock in the P/S conversion circuit (11). The serial pixel data is D
/^ Converted to an analog signal by the conversion circuit (12) and CR
One screen is displayed on T(2) at 120 ns.

The address control method during writing will be explained based on FIGS. 6 and 7.

Each memory element (M) has an 11-bit vertical address Va
dd O~10 and horizontal address Hadd O=10
The top 7 bins 1 lad 4 to 10 were combined.

It is accessed with an 18-bit memory element address Madd. The lower 4 bits Hadd O~3 are memory elements (
It is used to access (chip select) the address in M).

When this address Madd is an even number (Hadd 4 =
O) is a group of 16 pixel data arranged in chronological order.

Memory element number 0.1, 2, 3. ..., E, F, numbering one pixel at a time 0 For example, if it is pixel data of the 0th group, the first pixel data (0, 0) (pixel position number of the 0th group) is Written to address O of memory (M-0), the second (o, i) is written to memory element (M-1)
is written to address 0.

When the address Madd given to the memory element is an odd number, () Hadd4 = 1), a group of 16 pixel data is stored in chronological order by memory element number 1, 0.
゜3.2,5,4. ..., F, E in that order.

For example, if the pixel data of the 11th group is pixel data (1
, 0) is not written to address 1 of memory element (M-0), but written to address 1 of memory element (M-1), so that pixel data (1, 1) is Written to address 1.

As shown in FIG. 6, this write control uses the LSB (
This is performed using the output HaddO' of the exclusive OR circuit (13) which receives as inputs the LSB (=Hadd4) of the memory element address Madd and the LSB (=Hadd4) of the memory element address Madd.

The 4-man power 16-output decoder (14) is 1ladd O
', Haddl, I(add2, Hadd3
, memory elements (M-0), (M-1),..., (
M-F) respective chip select signals C5O, C
5I, -, C5F is made, but if Hadd4 = O, then 1ladd O = Hadd O',
cso, csi, ., csF become active in this order. On the other hand, if Hadd4=1, π feathers] = H
a d d O', C5I, C5O, C
53, . . . , C5F, and C5E become active in this order.

The state of pixel data written in each memory element in this way is illustrated in FIG. 7(B).

When the pixel data generation timing is early (for example, 20n
s) is provided with a launch circuit and select signals (C3O, C
The image data latched by 5I, ..., C3F) is written to the memory element once every cycle (320ns).
It is sufficient to write six pieces of pixel data in parallel.

In this way, in order to write to and read out the display memory for 4M pixels for normal display (displaying 1M pixels out of 4M pixels), the order of the image data is changed to the read address Had.
When d4 is an even number, the order is maintained, and when it is an odd number, the order is changed.

To read and display with 172 reduced size, α and β in normal display are set to 0, Hadd upper 7 bits, Vadd11
The address of the bit is doubled and the even numbered memory element (M
-0), (M-2), (M-4), ..., (M-
Read only even addresses for E), and at the same time,
Odd numbered memory elements (M-1), (M-3),...
, (M - F) is read at an address obtained by adding 1 to the above even address.

In FIG. 7 (8), the pixel data to be read out is surrounded by O,
It shows the relationship with memory addresses.

Here, 1 is the address in normal display multiplied by 2. As shown in Figure 1, α and β are set to 0, and the upper 7 bits of the horizontal address and 11 bits of the vertical address, which are the device address, are respectively It is twice as much.

When displaying from normal (0,0) pixel data, the display size is 1024 x 1024, so the address only needs 10 bits (XIO bits), and both the horizontal and vertical addresses are The most significant bit is always O. Therefore, even if the display address from this ('o, o) data is doubled, there will be no overflow and each memory element will still be accessed using a total of 18 bits of address.

An example of a circuit for performing the above control is shown in FIG.

As shown, even numbered memory elements (M-0).

Address lines (15) leading to (M-2), (M-4), ..., (M-E) and odd numbered memory elements (
Equipped with two systems of address lines (16) leading to M-1), (M-3), ... (M-F).

The exclusive OR circuit (17) performs the operation of adding 1 to even addresses.
I'm doing it.

That is, when the normal/reduced display switching signal Eχ is set to 1 (corresponding to the high level signal rHJ), the gate circuit (1
8), an address that is twice the address where α and β are O is given to the even numbered memory elements through the address line (15), and at the same time RTaTa-, which is the inversion of Hadd 4, is Odd address signals of +1 as the lower bits are applied to odd numbered memory elements through address lines (16).

Data DO to DF are read from each memory element at a read period (
320 ns) and provided to the selector (25) via the latch (26).

For example, if the double address Hadd 4 is set to O#, Do, D2 . D4.・
..., the data (0,0), (0,2), (0,4), etc. are stored in Di,
D3. D5. ...to (1°0), (1,2), (1
, 4)... are read out (Figure 9 (^))
.

This read data D is not arranged in display chronological order, so by controlling the lower 4 bits of the horizontal address during P/S conversion, the data D is displayed as shown in FIG. 9(B). I am trying to obtain overwhelming display data in the order shown.

That is, as shown in FIG. 8, the output data DO of I6
-Selector (25) that selects one data from OF
is used to send the 4-bit select signal from the lower
d O, Hadd 1, Hadd 2, Had
Instead of d 3, selector (2m) ~ (24)
Switch with Hadd 3.

The output data is arranged in the original chronological order as Hadd O, Hadd 1, and Hadd 2.

This select signal is given from the PuS conversion control circuit (8).

When the normal/reduction switching signal EX is set to "H", the control human power B becomes rHJ, and the 4-input selection selector (2m)
, (22), (23), and (24) are selected. Hadd3 to LSB, Ha
ddO, Hadd1, Hadd2 are the respective selectors (2m), (22), (23),
(24) is output.

In the case of normal display in which any IM in the 4M memory area is read, the normal/reduction switching signal EX is set to the low level signal "
It is set to "L".

The gate circuit (18) is closed by the signal EX, and the gate circuit (19) is opened.The normal element address, which increments by 1 for both vertical and horizontal addresses, is passed through the gate circuit (19) as the same address signal. Address line (1s)
, 06) and is simultaneously input to all memory elements.

By the way, in preparation for reduced display, when writing pixel data, different writing methods were used for even addresses and odd addresses.

Therefore, the select signal given to the selector (25) is set to the lowest bit Hadd of the horizontal address of the element address.
The order in which pixel data is written will be explained with reference to FIG.

In 1/16 reduced display, 1 out of 16 memory elements
In order to read out pixel data for every 6th pixel, starting from memory element number 0, the lowest memory element address (Hadd4
~7) The pixel data number 0 of the 0th group is at address O, and from the memory element number n, the data number 0 of the nth group is at address n, the lowest address of the memory element,... It must be possible to read out the coordinates (0,
0) to (F, F), the pixel data of No. 0 of each group is written diagonally downward at 45 degrees, and the pixel data of No. 0 of each group is written.

Next, regarding 178-reduced display, in order to read out pixel data every 8th from 16 memory elements, memory element numbers O to 7 must be set to number 0 of each group during 1716-reduced display. Since the pixel data has been written, the data of number 8 of each group is written to memory element numbers 8 to F. For the memory element lowest address O, suppose that the pixel data is written in the order of the pixel data and in the order of the memory element number. , 17
It is controlled by 4 of 16 reduction display.

That is, selectors (2m), (22), (23), (
Since the control human power B in 24) is rLJ, input hO or 1 is selected, but either input 0 or input 1 is selected depending on the control input A to which Hadd4 is input.

When the address is an even number, input O is selected with Hadd 4 = O, and l+addo becomes the LSB. When it's an odd number address.

When Hadd4 = 1, input 1 is selected and the LSB is stone sword).

As a result, in the selector (25), when the address is an even number, the order is DO, DI, . . . DF, and when the address is an odd number, the order is Di, Do, D3 . D2. ...
, DF, DE. EXOR circuit (17)
and selector (25) perform P/S conversion (1
1). FIG. 10 shows the state of this readout and P/S conversion.

The above embodiment is a case of 1/2 reduced display.

A 1/2' reduction display is also possible using a similar method.

As mentioned above, when the number of memory elements is 2 m, normal display, 1/2 m reduction display, 1/2 m reduction display can be performed. As an example, a case where the number of memory elements is 16 will be explained.

Similarly to the explanation, the pixel data of No. 8 in each group is
Write the 8th pixel data of each group at 5°.

Considering the 1/4 reduction and 1/2 reduction display in the same way, the seventh
Can draw diagram (C).

Figure 11 shows an example of the write circuit, Figures 12, 13, and 1.
Figure 4 shows an example of a readout circuit.

The example of the write circuit shown in FIG. 11 will be explained.

What is different from Fig. 6 is the (exclusive OR) EX-OR circuit (13
) is provided with an adder (31).

Select the memory element number using the horizontal address (Hadd O~3), and select the memory element lowest address (Hadd4~3).
Step 7) shifts the pixel data order and memory element number order during writing.

The adder (31) adds the address (HaddO-3) and the address ()ladd4-7). Ord-flow due to addition is ignored, and as shown in FIG. 7(C),
If the generation timing of 0 pixel data written sequentially according to the lowest address of the memory element is early, a latch circuit is provided and select signals (cso, csl...
, C3F), 16 pixel data may be written to the memory element in each write cycle.

An example of the readout circuit shown in FIG. 12 (writing example shown in FIG. 11) will be described. What is different from Fig. 8 is the P/S conversion control circuit (
8) and exclusive OR circuit (17) are simply replaced with a new P/S conversion circuit (8') and element-specific address generation circuit (32).

Address doubling circuits (6) and (7), depending on the reduced display,
That you have to change it by 2 times, 4 times, 8 times, 16 times.

The shift amounts α and β are 0;α/4°β/ according to the reduced display.
4;α/8. β/8: α/16. Needless to say, an appropriate shift amount such as β/16 should be set.

Details of the P/S conversion control circuit (8') are shown in FIG. 14, and details of the element-specific address generation circuit (32) are shown in FIG. 13.

The pixel data is rearranged by the P/S conversion control circuit (8'
) and the element-specific address generation circuit (32).

These circuits are located at addresses HaddO to 7. Data may be created in a ROM whose address is the reduction lh ratio so that the pixel data in each reduction display in FIG. 7(C) appears in order.

FIG. 13 shows an embodiment of the element-specific address generation circuit (32), which includes gated selectors (51-0) to (51-F).
and adders (52-0) to (52-F), and the address of each memory element (M -0) to (M -F) is shifted by the adder (52-0) to (52-F) according to the reduction rate. 52), and the shift amount is added by selectors (51-0) to (51-0).
F) is selected.

Address of 0th memory element (M-0) Add M
0, the shift amount is always 0 regardless of reduced display.0 In normal display, rHJ is input to the G input of the selector (51).
is input, and all selector outputs become O.

The shift amount is O.

The values of A and B are 0, 0 when the reduction rate is 1/2, 1 when it is 1/4, 0 when it is 0.1/8, and 1°1 when the reduction rate is 1/16. . The selector (51) requires O input for 1/2 reduced display, and manual input for 1/4 reduced display.
Select 2 inputs for 1/8 reduced display, and 3 inputs for 1/16 reduced/J1 display.

Address AddM of second memory element (M-Q)
12, in l/2 display, the shift amount is 0. For odd number a, the shift amount is 1. In l/4 display, it is divided into 4 groups of 4 in order, and the 0th of the group is set to shift J.
10.The first shift is Jll, and the second shift amount is 2.
The shift amount is 3 for the third @. In l/8 display, 8
The 0th group has a shift amount of Ol·, and the 8th group has a shift amount of 8. l/1
In the 6 display, the memory element number becomes the shift amount.

FIG. 14 shows an example of the P/S conversion control circuit (8').

It is composed of selectors (71) to (74), a Caro calculator (T7), and gates (75) and (76).

In normal display, game 1- (75) (76) r)(
J is input, A and B both become ")(", and the address Hadd O of the three selectors (71) to (73) is input.
-3 are output in order. The adder (74) adds the addresses Hadd 4 to 7 and outputs the result to the selector (25). As shown in Figure 7(C), address Hadd 4
~7 is added to address l1addO~3 as a shift amount.

In l/2 display, Hadd O-3 is every second, so shift Hadd O-3 one by one (Hadd
1, 2.

3.0), every second memory element number is selected and Hadd 4 to 7 are added.

This is equivalent to the shift in the address direction of the memory element in FIG. 7(C). Overflows are ignored and passed through in order.

In l/4 display, Hadd O~3 is every fourth.

By further shifting Hadd O~3 one by one from l/2 display (l/4 of Hadd2, 3, 0.1),
By selecting every fourth memory element and adding Hadds 4 to 7, it becomes equal to the shift in the memory element allodress direction in FIG. 7(C). Overflows are ignored and passed in order.

In l/8 display, Hadd O~3 is every 8th.

From the l/4 display, by further shifting l+addo~3 by one (in the order of Hadd3, 0, 1, 2), every eighth memory element is selected, and by adding Hadd4~7, the This is equivalent to the shift in the address direction of the memory element in FIG. 7(C). Overflow is ignored.

In l/15 display, it is every 16th item, so it goes around once.

Hadd O to 3 may be in that order.

Data output from memory elements (ni-〇) to (M-F) is.

It is applied to the selector (25) via the latch (26) every read cycle.

In this embodiment, as shown in FIG. 7(C), for example, the loading and reading of pixel data is shifted in order, but if a ROM is used, within a periodic range, regardless of the order, it is always Needless to say, it is sufficient if the pixel data can be read in the required order.

As described above, the present invention controls writing to a memory element, controls reading, and controls the arrangement of read data. Not limited to 1/4 reduction display, but generally reduction display up to 1/2' is possible.

The above embodiment assumes that the memory size is larger than the screen size, but even if the memory size is equal to or less than the screen size, this method can be applied in the same way, and the reduced image can be displayed within the screen. (The area other than the display part can be displayed in black).

If switching between normal image display and reduced image display is performed during the blanking period of the monitor, no disturbance will occur in the displayed image.

Further, although the above embodiment has been described as displaying an image on a CRT monitor, this method may be similarly applied when printing an image (reduced image) using a printing device.

(Effects of the Invention) As described above, according to the present invention, since the address given to the image memory is controlled so that one time series of image data is thinned out in units of the number of pixel data corresponding to the reduction ratio, the original image It is possible to obtain a reduced image that is faithful to the original image, and furthermore, it is possible to obtain a reduced image that is faithful to the original image without using high-speed memory elements or multiple image memories. Just use it as is.

Since only the address changes, it is instantaneous (for example, l/3
0 or l/60 seconds), it is possible to switch between normal image display and reduced image display.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of how to thin out pixel data in this embodiment, and Fig. 3 shows the correspondence between memory size and screen size in the embodiment. FIG. 4 is an explanatory diagram showing the structure of image data. FIG. 5 is a schematic diagram of a memory block. FIG. 6 is a detailed diagram of the image memory write circuit, and FIGS. 7 (^), (B), and (C) are explanatory diagrams at the time of one write. FIG. 8 is an illustrative diagram of the readout circuit; FIGS. 9(^), (B), and (C) are explanatory diagrams of readout and P/S conversion in the case of reduced display; FIGS. 10(A), ( B) is an explanatory diagram in case of 1 normal display,
FIG. 11 is a detailed diagram of the write circuit of another embodiment, the first
FIG. 2 is a detailed diagram of the readout circuit of the embodiment of FIG. 11. 13 and 14 are detailed circuit diagrams of the blocks in FIG. 12. (1)...Image memory for display (2)...
CRT (3)...Vertical address generation circuit (4)...
Horizontal address generation circuit (5)...Display memory writing circuit (6), (7)...Address doubling circuit (8)...
P/S conversion control circuit 'N! (M)...Memory element (MB
)...Memory block (13), (17)
...Exclusive OR circuit (Is), (16)...Address line (2m) to (24)...Selector (
25)...Selector (26)...
Latch Figure 2 Figure 3 Prisoner Damage 204a-1 ← Figure 7 (C) No L') No. 1 0123456789ABCDEF Figure 9 1 Right -y -1 ÷ Procedural amendment (voluntary) 1985 4 Month 72. Day

Claims (7)

[Claims] (1) Divide the pixel data forming the ordered sequence into groups of 2^m pieces, write the pixel data of each divided group to the same location of the 2^m memory elements, and When reading 2^m pixel data in parallel from the memory element, converting it from parallel to serial so that it follows the original sequence, and displaying the image on the monitor, when writing the pixel data to the memory element, the above 2. ^m
For every at least two consecutive addresses that access memory elements of Control is performed for at least two groups so that pixel data of the same specific number within the group is written to memory elements of mutually different numbers, and when reading pixel data from the memory elements, when displaying a normal image, , the 2^m pieces of data read from the 2^m memory elements are rearranged according to the write control using consecutive addresses, and when displaying a 1/2^n reduced image, the vertical addresses and Both horizontal addresses are multiplied by 2^n according to the 1/2^n reduction, and the above 2^m memory elements are written so that 2^m pixel data is read every 2^n. Read with 2^n types of addresses according to the control, arrange the order of the read 2^m pixel data based on the above writing control and readout control, and write it to either a normal image or a reduced image, as desired. 1. A method for displaying image data, characterized by being able to switch to and display image data. (2) When pixel data is stored in the memory element, the even number of every 2^m consecutive sequential pixel data group is
The pixel data is sequentially written into 2^m memory elements by replacing the odd-numbered data with the even-numbered data and the odd-numbered pixel data, respectively. How to display image data. (3) When reading pixel data from memory elements and displaying a normal image, data is read from 2^m memory elements, and if the lowest address to access the memory elements is an even number, the data is read in the order of the memory elements. , when the lowest address for accessing the memory element is an odd number, the control is performed to display a normal image on the monitor in the order in which even and odd data in the memory element are exchanged. The method of displaying image data described in section 2). (4) When reading pixel data from a memory element and displaying it in a 1/2 reduced size, double both the vertical and horizontal addresses, assign an even address to an even numbered memory element, and assign an even address to an odd numbered memory element. Odd addresses are given simultaneously and independently, and 2^m data are read for each consecutive even and odd address pair, and the data read from the even numbered memory element in the order of the memory element number and the data from the odd numbered memory element are read. Claim No. 1, characterized in that the data read out in the order of memory element numbers is displayed sequentially on a monitor.
The method of displaying image data described in section 2). (5) When writing pixel data from a memory element, the order of consecutive sequential pixel data every 2^m is shifted in the order of the memory element by cyclically shifting the order according to the value corresponding to the memory element access address value. Claim 1 (1) is characterized in that the pixel data thus obtained is stored in a memory element.
) How to display image data as described in section. (6) When reading pixel data from the memory element and displaying a normal image, rearrange the 2^m pieces of read image data according to the lowest 2^m value of the access address,
The method for displaying image data according to claim 5, characterized in that a normal image is displayed on a monitor. (7) Read pixel data from memory element and reduce by 1/2^
n When displaying a reduced image, both vertical and horizontal addresses are 2^
Multiply by n, divide into groups of 2^n pieces in numerical order, give lower addresses 0, 1, ..., 2^n-1 to the memory elements independently, and read 2^m pieces of data from the memory elements. , according to the numerical value of the lowest 2^m of each access address, the data order is rearranged and a 1/2^n reduced display is performed on the monitor. The method for displaying image data described in section 5).