JP3262284B2 - Semiconductor test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single semiconductor test apparatus provided with two test stations, which are operated simultaneously at the same time in the two test stations, or two test stations are operated at the same time. The present invention relates to a semiconductor test apparatus (IC tester) for testing an analog semiconductor device by operating stations alternately in a time-division manner.

[0002]

2. Description of the Related Art First, referring to FIG.
The C tester main body, to which two test stations 1 and 2 are connected. C is a central control unit for setting various test measurement conditions for the IC tester main body T and the two test stations 1 and 2. The test stations 1 and 2 are provided with performance boards 3 and 4 for testing and measuring ICs 5 and 6 to be tested and measured from the IC tester main body T via these performance boards 3 and 4. It is configured to transmit and receive signals. The IC under test is placed in the IC tester main body T.
For testing two analog pins 5 and 6 each
Allowed comprising two signal generating / signal reception measurement unit channel ch1 and channel ch2 is, these channels ch1 and channel ch2 via the changeover switch 7 and 8, respectively, are switched connected to the test station 1 and 2 You. The interconnection relationship between the six channels ch1 and ch2, the changeover switches 7 and 8, and the test stations 1 and 2 is as shown in FIG. Two analog pins
When measuring IC5 with
Switch 7 and 8 to station 1
When switching IC6 at station 2, switch
Switches 7 and 8 are switched to station 2 and connected
do.

Here, two test stations 1 and 2 are operated at the same time at the same time to make one analog pin.
For simultaneous measurement of measuring IC5 and IC6 have the emissions at the same time, figure toggle switches 7 and 8 2 (b)
Is switched as shown in FIG.
While connected to the station 1, the channel ch2 is connected to the test station 2. In this case, the two IC5 and IC6 to be measured and tested are the same IC, and the two signal generation / signal reception measurement units, channel ch1 and channel ch2, are completely identical to each other and identical to each other. IC5 and IC
The same test measurement shall be made for 6. And
Channel ch1 is connected to the pin electronics card PE ch 1 and similarly corresponding predetermined port of the performance board 3 corresponding to the channel ch1 in the test station 1 (e.g., the first port). Most
Finally, the port corresponding to the channel ch1 and the target pin (for example, the first pin) of the IC 5 to be tested and measured are connected. On the other hand, for the channel ch2, the pin electronics card PE ch 2 and similarly corresponding predetermined port of the performance board 4 corresponding to the channel ch2 in the test station 2 (e.g., 7
Port 6) , and finally a port to be tested and measured with a port corresponding to the channel ch2 (for example, the seventh port).
Target pin (e.g., the first pin) and the connection (e.g., Fig. 2
(Arrow in (b)) .

[0004] It is called normal measurement that two test stations 1 and 2 are alternately operated in a time-division manner to test and measure different types of semiconductor devices in the test stations 1 and 2. Although not shown in the figure,
A large number of channels ch for
Electronics card PEch is usually prepared
ing.

[0005]

Referring to FIG. 4 for a detailed description of the connection relationship in the measurement described above, the predetermined port of the performance board 3 is a port corresponding to channel ch1 (first port) . On the other hand, the predetermined port of the performance board 4 is a port corresponding to the channel ch2.
(7th port) , which are different from each other. Since the same test measurement is performed on the same IC5 and IC6, the target pins of the IC5 and IC6 to be tested and measured are also the same pin (first pin).
N) . Since the pins to be tested and measured are the same pins, but the ports of the performance board for transmitting and receiving signals for the same pins are different, one of the test stations (in this case, the performance Either change the connection between the pins to be tested and measured on board 4) and the ports of the performance board or make the performance boards 3 , 4 different. Although it is necessary to change the connection between the target pin to be measured and the port of the performance board, this is practically difficult, and it is difficult to prepare two different types of performance boards. It is even more difficult.

An expensive and special signal generation for analog pins /
The above-mentioned difficulties can be solved by providing each of the test stations 1 and 2 independently, as shown in FIG. 3, with the channel ch1 and the channel ch2, which are signal reception and measurement units. However, in the case of a normal measurement in which two test stations are alternately operated in a time-sharing manner, one set of the channel ch1 and the channel ch2 becomes useless and uneconomical.

An object of the present invention is to provide a semiconductor test apparatus in which the measurement cost is not significantly increased even in the case of the simultaneous measurement as compared with the case of the normal measurement.

[0008]

A central control unit C for controlling the IC tester main body T and the test stations 1 and 2 includes an IC tester main body T to which two test stations 1 and 2 are connected. The two test stations 1 and 2 each include a performance board 3 or 4, and in the IC tester main body T, two channels ch1 and ch2, which are signal generation / signal reception measurement units, are provided. And switch switches 7 and 8 for switching and connecting the two channel ch1 and channel ch2 to the test stations 1 and 2, respectively. The switch 7 of one channel ch1 connects this channel ch1 to one test station. 1 of the performance board 3 in one channel ch1 Of the performance board 4 in the other test station 2 and to the port corresponding to the other channel ch2, and the changeover switch 8 of the other channel ch2 connects this channel ch2 to the one test station 1 Other channel ch2 of performance board 3 at
2. A semiconductor test apparatus connected to a corresponding port and connected to one channel ch1 corresponding port of the performance board 4 of the other test station 2 is constituted. In the semiconductor test apparatus, a signal generation unit includes a channel ch1 analog waveform generation memory 11, a channel ch2 analog waveform generation memory 12, and a multiplexer 2 for both channel ch1 and channel ch2.
2. A semiconductor test apparatus comprising a 0 / D / A converter 30 and a waveform content stored in the analog waveform generation memory is selectively switched and supplied to the D / A converter 30 by the multiplexer 20. In the semiconductor test apparatus described above, the signal generation unit includes an analog waveform generation memory of one channel and an analog waveform generation memory of the other channel, a multiplexer and a D / A converter for both of the channels.
A semiconductor test apparatus was constructed in which an address converter of these analog waveform generation memories was provided with an address converter.

[0009]

An embodiment of the present invention will be described with reference to FIG. T is an IC tester main body to which two test stations 1 and 2 are connected. C is a central controller, which sets various test and measurement conditions for the IC tester main body T and the two test stations 1 and 2.
It is for control. Each of the two test stations 1 and 2 has a performance board 3 or 4 and also has two channels ch1 and ch2, which are signal generation / signal reception measurement units, in the IC tester main body T. ing. Two channels c
h1 and channel ch2 are provided with respective changeover switches 7 or 8, and these changeover switches 7
Or 8 is for switching and connecting the channel ch1 and the channel ch2 to the test stations 1 and 2. Changeover switch 7 for one channel ch1
Sets this channel ch1 to one of the test stations 1
One channel c of performance board 3 at
h1 corresponding port PEch1 and performance board 4 in the other test station 2
Is connected to the other channel ch2 corresponding port PEch2 . Then, the changeover switch 8 of the other channel ch2 connects the channel ch2 to the port PEch2 corresponding to the other channel ch2 of the performance board 3 of one test station 1 and connects the channel ch2 to the performance board 4 of the other test station 2. Port PEc corresponding to one channel ch1
h1 .

In order to perform simultaneous measurement and normal measurement without problems by connecting as described above, the IC tester main body T and the two test stations 1 by the central controller C are used.
The software settings of various test and measurement conditions for the test stations 1 and 2 are the same as those of the test station 1 and the normal settings are performed. Replace and set. This setting can also be implemented by preparing hardware for the setting.

An embodiment of an analog waveform generator of a semiconductor test apparatus according to the present invention, which can suitably cope with both simultaneous measurement and normal measurement, will be described with reference to FIG. In the embodiment of FIG. 6A, the channel ch1 analog channel generation memory 11, the channel ch2 analog waveform generation memory 12, the multiplexer 20 and the D / D An A converter 30 is provided. The waveform contents stored in these analog waveform generation memories are selectively switched by the multiplexer 20 and supplied to the D / A converter 30, where they are converted into analog waveforms.

Here, the multiplexer 20 switches the analog waveform generation memories 11 and 12 to the D / A converter 30 and controls the connection as follows. For (A) Normal measurement station 1, the memory 11 ₁ by the multiplexer 20 ₁ while the connection switching to the D / A converter 30 ₁ is switched connecting the memory 12 ₂ by the multiplexer 20 ₂ to the D / A converter 30 _2.

As for the station 2, the memory 11 ₂
D a by the multiplexer 20 ₂ / A converter 30 ₂
To thereby switch connection and switching connect the memory 12 ₁ by the multiplexer 20 ₁ to the D / A converter 30 _1. In the state set in this way, each
IC5 and IC6 with one analog pin are alternated in time
When a test, first memory 11 ₁ - multiplexer
20 ₁ -D / A converter 30 ₁ -Changeover switch 7
(Solid line)-connection of PEch1-IC5 of station 1
The IC5 is tested on the route and the memory 12 ₁ −
Multiplexer 20 ₁ -D / A converter 30 ₁ -Off
Switch 7 (dotted line)-PEch 2- of station 2
The test of the IC 6 can be performed through the connection path of the IC 6.
In addition, the ICs 5 and 6 having two analog pins can be connected in time.
When the test alternately, first memory 11 ₁ and the memory 1
2 ₂ Each PEch1 station 1 and in the PEc
h2 and test IC5 via
12 ₁ and the memory 11 ₂ , respectively,
Testing of IC6 via Ech2 and PEch1
Can be. (B) the simultaneous measurement memory 11 ₁ to switch connects the memory 11 ₂ by the multiplexer 20 ₂ to the D / A converter 30 ₂ as well as switch connected to the D / A converter 30 ₁ by the multiplexer 20 _1. In the state set in this way
And ICs 5 and 6 each having one analog pin
When testing at the same time, the memory 11 ₁ -multiplexer
20 ₁ -D / A converter 30 ₁ -Changeover switch 7
(Solid line)-connection of PEch1-IC5 of station 1
Were tested in IC5 a path, at the same time the memory 11 ₂ - Mar
Switcher 20 ₂ -D / A converter 30 ₂ -Switching
Switch 8 (dotted line)-Station 2 PEch1-IC
The test of the IC 6 is performed by the connection path 6.

By providing an address converter in the address circuit of the waveform memory instead of switching the waveform data by the multiplexer as shown in FIG. 6B, control can be performed in the same manner as in FIG. 6A. .

[0015]

As described above, channel ch1 and channel ch, which are two signal generation / signal reception measurement units, are used.
2 is assigned to only one test station 1 and connected, and the other channel ch2 is assigned.
Is assigned to only the other test station 2 and connected, so that one channel ch1 is connected to one test station 2.
While connected to one of the channels ch1 corresponding ports of the performance board 3 at station 1 (for example, the first port), one of the channels ch1 corresponding ports of the performance board 4 other channel ch2 is also in the other test station 2 (e.g. 1st port)
To connect to. In short, the ports of the performance boards 3 and 4 are the same as one channel ch1 corresponding port (for example, the first port) . Therefore, the same pin (for example, the first pin) on the IC5 , 6 side and its
Since they are connected respectively, the same performance boards 3 and 4 can be used. That is, I having one analog pin each
When testing the same test of C at the same time,
A performance board can be used. This eliminates the need for two types of performance boards, which require a lot of time, money and cost to manufacture.
It means you only have to prepare one kind of board,
It is suitable. It is also advantageous in that there is no need to change the connection between the target pin of the IC to be measured and measured and the port of the performance board.

In the semiconductor test apparatus equipped with the analog waveform generator of the present invention, both the analog waveform generator memory 11 of the channel ch1 and the analog waveform generator memory 12 of the channel ch2 are provided in each channel, and these memories are multiplexed. 20 is used to switch and connect to the D / A converter 30. By doing so, the number of analog waveform generation memories is doubled. Instead, the required waveform can be output only by simple switching control of the multiplexer 20 by software. The switching connection control of the multiplexer 20 is easier than outputting a required waveform by providing a set of analog waveform generation memories and setting and managing these memory addresses by software. , Which leads to reduced test measurement time overhead.

[Brief description of the drawings]

FIG. 1 illustrates a conventional example of a semiconductor test apparatus.

FIGS. 2A and 2B are diagrams illustrating a connection between a channel and a test station in a conventional example of a semiconductor test apparatus.

FIG. 3 is a diagram illustrating a connection between a channel and a test station in a conventional example of a semiconductor test apparatus.

FIG. 4 is a diagram illustrating a connection between a channel and a test station in a conventional example of a semiconductor test apparatus.

FIG. 5 illustrates an embodiment of the present invention.

6A and 6B are diagrams illustrating an embodiment of an analog waveform generator used in the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test station 2 Test station T IC tester main body C Central control unit 3 Performance board 4 Performance board ch1 channel 1 ch2 channel 2 7 changeover switch 8 changeover switch

Claims (3)

(57) [Claims] 1. A two test stations comprising the IC tester main body which is allowed to connect, comprising a central control unit for controlling the I C tester body and test station, each two test station performance comprising a board, provided with a changeover switch which comprises a two-channel is a signal generator / signal reception measurement unit in the I C tester body to switch connects each of the two channels to two test stations and, selector switch of hand channels connected with connecting the channels to one channel corresponding ports of the performance board in one test station, the other channel corresponding ports of the performance board at the other test station The other channel Wherein the changeover switch is used to connect with connecting the channel to the other channel corresponding ports of the performance board in one test station, on one of the channels corresponding ports of the performance board at the other test station Semiconductor test equipment. 2. A semiconductor test system as claimed in claim 1, the analog waveform generator memory of the analog waveform generator memory and the other channel of one channel each signal generating unit of both channels, a multiplexer and a D /
Comprising A converter, a semiconductor test apparatus, wherein the waveform contents stored in these analog waveform generator memory is a member selected switch provided to the D / A converter by a multiplexer. In the semiconductor testing apparatus described in 3. The method of claim 1, the analog waveform generator memory of the analog waveform generator memory and the other channel of one channel each signal generating unit of both channels, the address converter and D /
Comprising A converter, it is input to the address circuit of these analog waveform generator memory
Address of the analog waveform generation memory
Address for one channel and one for the other channel
A semiconductor test apparatus, comprising: an address converter for selectively converting the data into an address.