JP3261800B2 - Integrated circuit for driving display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for driving and displaying a display panel of a liquid crystal type or the like, comprising test circuit means for confirming the performance of the display panel in combination with the display panel. The present invention relates to a display panel driving integrated circuit which can be driven for display together with another integrated circuit having a similar configuration or can be added in accordance with the data display capacity of a display panel to be driven.

[0002]

2. Description of the Related Art In order to display an image on a display panel of a liquid crystal type or the like, as is well known, it is necessary to simultaneously apply a display voltage to data lines while sequentially applying a scan voltage to the scan lines. It is customary to integrate drive circuits for lines and data lines into an integrated circuit.However, when manufacturing this integrated circuit, it is, of course, necessary to check the drive performance by testing. Can be FIG.
Shows an outline of such a driving circuit of the display panel.

A display panel 1 shown in a simplified manner has a large number of scanning lines 1a and data lines 1b, and pixels Pij which are intersections of the scanning lines 1a and data lines 1b.
The scanning line 1a is connected to the data line by the scanning driving circuit 71.
1b are respectively driven by the data driving circuits 72. In the illustrated example, the data line 1b is driven by a plurality of data driving circuits 72 each emitting m data outputs Di, and the scanning line 1a is driven by n.
Each is driven by a single scan drive circuit 71 that emits the scan outputs Sj. A clock generation circuit for synchronizing the display operation of the scan drive circuit 71 and the data drive circuit 72
73 is provided, for example, three types of clock pulses CP generated are supplied to the data driving circuit 72, and two of them, for example, are supplied to the scanning driving circuit 71 to respective clock terminals Tc. The data driving circuit 72 on the left side of the drawing receives display data D from a circuit (not shown) at one data terminal Td, and the data driving circuit 72 on the right side from the other data terminal Td as usual.
It is transmitted sequentially to 72.

In order to test the scan drive circuit 71 and the data drive circuit 72, a switching signal Sw for switching the operation between a display state and a test state and two designating signals S for designating a test mode are used. Drive circuits 71 and 72 receive them at test terminal Tt, respectively. The test is performed by switching the operation of both driving circuits 71 and 72 to four modes by two designation signals S. As a test, the display panel 1 is switched as shown in FIG.
A display test can be performed with the display panel 1 connected. In general, however, a digital measuring device with a scanner is connected in place of the display panel 1 and a plurality of data outputs Di and scan outputs Sj generated by both drive circuits 71 and 72 are connected. The measurement is performed by sequentially measuring the voltage values. The above-mentioned clock pulse CP is, for example, a clock for switching the polarity of a voltage applied to the pixel Pij for so-called AC driving of the display panel 1 in addition to a clock for switching the display data D and a switching for the scanning output Sj. Is included.

[0005]

The above-described scanning drive circuit 71
And the data drive circuit 72 can be integrated into an integrated circuit of a small chip size, or each can be appropriately combined.
Although the test terminal is necessary for testing, it is unnecessary when the chip is connected to the display panel and actually used, and other terminals are required to make sure that the needle of the test probe is in contact with it. Since it is necessary to use connection pads or the like which are considerably larger, there is a problem that a valuable chip area is unnecessarily consumed for the test terminals.

In particular, when an integrated circuit is highly integrated to increase the number of data lines and scanning lines that can be driven by one chip,
Since the number of output terminals, and thus the number of terminals per chip, increases according to the number of drive lines, it becomes very difficult to arrange a large number of terminals including test terminals on the periphery of the chip. At this time, the output terminals for driving the display panel can be reduced in size by using, for example, bump electrodes, but the test terminals cannot be reduced in size.Therefore, unnecessary test terminals increase the number of drive lines per chip in actual use. Or, it is an obstacle in reducing the cost by reducing the size to a small chip due to high integration.

In view of the above situation, an object of the present invention is to reduce the number of terminals of an integrated circuit including test terminals and a chip area required for forming the terminals.

[0008]

SUMMARY OF THE INVENTION According to the present invention, there is provided a state selection circuit for switching the operation of an integrated circuit between a normal state based on display data and a test state based on a test content specifying signal, and an input of a specifying signal. A switching terminal for inputting a switching signal for designating a normal state or a testing state;
In response to the switching signal, the designation signal, and the internally generated clock pulse, the clock signal is sent to the test terminal when the normal state is designated by the switching signal, and the designated signal is sent to the state selection circuit when the test state is designated. A switching circuit for outputting the specified signal to a test terminal in a test state, thereby proceeding with a test specified by the specified signal, and outputting a clock pulse from the test terminal in a normal state to be supplied to another integrated circuit. This is achieved by the integrated circuit described above. The integrated circuit according to the present invention may be divided into the above-described one for driving the scanning line and the one for driving the data line. However, the scanning driving circuit is divided into a plurality of integrated circuits for the data driving circuit, or one of the integrated circuits is used. It is advantageous to simplify the driving of the display panel by incorporating the components in a concentrated manner.

Also, the test for the integrated circuit of the present invention usually needs to be performed in a plurality of modes as described above.
In addition, since a plurality of types of clock pulses are required to drive the display panel, a plurality of test terminals are provided so that a plurality of modes can be designated, and when a test state is designated by a switching signal, a designation signal received at these test terminals is used. It is preferable that the test proceed in each of the designated modes, and when a normal state is designated, a plurality of clock pulses can be output from these test terminals. Further, the switching circuit constituting the integrated circuit of the present invention includes means for transmitting the signal of the test terminal to the state selection circuit only when the test state is designated by the switching signal;
It is preferable that the clock pulse is transmitted to the test terminal only when the normal state is designated.

[0010]

The present invention focuses on the point that, in the conventional display panel driving integrated circuit, the test terminals are used only in the test state as described above and are not used in the normal state of driving the display panel. The conventional problem is solved by using the terminals twice for inputting a designation signal for test contents and for outputting clock pulses. That is, the switching circuit described in the preceding paragraph is provided, and a switching signal is supplied to the switching terminal from the switching terminal. When a test state is designated by this, a designated signal is supplied from the switching circuit to the state selection circuit to test the operation of the integrated circuit. State, and when the normal state is designated, a clock pulse is supplied from the switching circuit to the state selection circuit to bring the operation of the integrated circuit into the normal state, and the clock pulse is also supplied to the test terminal, and the same display panel is displayed. The output is made to another integrated circuit to be driven.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing an embodiment of a display panel driving integrated circuit according to the present invention together with a display panel 1. FIG. 2 is a diagram for driving the display panel 1 by the integrated circuit 10 of the embodiment of FIG. 1 and another integrated circuit. FIG. 3 is a circuit diagram showing a detailed configuration example of a portion excluding the switching circuit 60 of the integrated circuit 10 in FIG. 1, and FIG. 4 is a circuit diagram showing a detailed configuration example of the switching circuit 60. In the embodiment shown in these figures, the display panel 1 is relatively small, and its scanning lines are driven by a scanning drive circuit 11 incorporated in the integrated circuit 10, and display data D and clock pulses are generated inside the integrated circuit 10. Shall be generated by

The display panel 1 shown at the right end of FIG. 1 is of a small liquid crystal type. For example, 16 scan lines are sequentially driven by a scan output Sj of a scan drive circuit 11, and a data drive circuit is provided.
For example, 40 data lines are simultaneously driven by the 12 data outputs Di. Since the display panel 1 is AC-driven, a drive voltage circuit 13 shown in the upper right part of the figure is provided, receives the positive and negative power supply voltages Vp and Vn and their intermediate voltages V1 to V4, and also converts the polarity signal M into a level shift circuit 13a. From the above-mentioned voltage according to the logical value of the polarity signal M.
The positive and negative drive voltages to be applied to the pixels Pij are selected, and the output stage 11d of the scan drive circuit 11 and the output stage of the data drive circuit 12 are selected.
Give to 12d.

A clock circuit 14 shown at the lower right of FIG. 1 is for generating a control clock for a display operation, and includes a clock pulse CP 1 for switching the scan output Sj of the scan drive circuit 11 and a display pulse for the display data to the data drive circuit 12. A clock pulse CP2 for reading and a polarity clock pulse MP for designating the polarity of the driving voltage applied to the pixel Pij are generated. The ROM 15 and RAM 16 shown on the left side are for storing display data.
Data read in parallel therefrom is converted into serial display data D by the data conversion circuit 17 in synchronization with the clock pulse CP2.

According to the present invention, the operations of the scan drive circuit 11, the data drive circuit 12, and the drive voltage circuit 13 are tested in the test state and the display panel 1.
A state selection circuit 50, which is enclosed by a dashed line, is provided to control the normal state in which normal display is performed. The state selection circuit 50 of this embodiment includes a data selection circuit 20, a polarity selection circuit 30, and a scan selection circuit 40. Further, a switching circuit 60 is provided to externally designate the above-mentioned normal state and test state by a switching signal Sw.
When a test state is specified by the switching signal Sw, the test mode specifying signals S1 to S3 received via the test terminals T1 to T3 are supplied to the state selection circuit 50 to receive the normal state. Is designated, the clock pulses CP1, CP2, and MP received from the clock circuit 14 are output from the test terminals T1 to T3, respectively.

The designation signal S1 output from the switching circuit 60 in the test state is common to the selection circuits 20 to 40 of the state selection circuit 50, and the designation signal S2 is the data selection circuit 20 and the scan selection circuit.
The designation signal S3 is supplied to the voltage selection circuit 30. Further, the display data D, the clock pulse MP, and the clock pulse CP1 from the data conversion circuit 17 are given to the data selection circuit 20, the voltage selection circuit 30, and the scan selection circuit 40, respectively.

Next, referring to FIG. 3, circuits and operations other than the switching circuit 60 will be described. Selection circuits 20 to 40 shown on the left side of the figure
In this embodiment, the designation signal S1 commonly received is set to low in the normal state and set to high in the test state. Selection circuit
Data selection circuit because the internal configuration of 20 to 40 is the same
Operation 20 will be described first. The composite gate 21 shown in the figure is a combination of two AND gates and a NOR gate, and a designated signal
When S1 is low, the lower AND gate is enabled by the output high of the inverter 22 and the upper AND gate is disabled, so that the display data D received by the lower AND gate via the inverter 23 is the composite gate 21. Is output as a signal s2. When the designation signal S1 is high, the lower AND gate is disabled and the upper AND gate is enabled.
, A complementary signal of the designation signal S2 received by the upper AND gate by the NOR gate is output as a signal s1.

Similarly, the polarity selection circuit 30 outputs the designation signal S1
Is low, the polarity clock pulse MP is output, and when high, complementary signals of the designated signal S3 are output as polarity signals M, respectively.
When the designation signal S1 is low, the clock pulse CP1 is outputted from the operation selection circuit 40, and when the designation signal S1 is high, a complementary signal of the designation signal S2 is outputted as the signal s1. As can be seen from the above description, the state selection circuit 50 including the selection circuits 20 to 40 performs the display data D, the clock pulse CP1, and the polarity clock pulse necessary for the display driving of the display panel 1 in the normal state in which the low is specified in the specification signal S1. In the test state in which MP is output and the specified signal S1 is set to high, the function of fixing the three outputs to logical values corresponding to each test mode specified by the specified signals S2 and S3 will be described later. Fulfill.

Each of the scan drive circuit 11 and the data drive circuit 12 is composed of a plurality of circuits for generating a scan output Sj and a data output Di, respectively. FIG. 3 shows only one of them for simplification. I have. The scanning drive circuit 11 includes a shift register 11a receiving the above-described signal s1, an exclusive NOR gate 11c receiving the output of the shift register 11a and a complementary signal of the polarity signal M, and an output stage 11d generating a scanning output Sj according to the output. Become. The configuration of the data drive circuit 12 is also substantially the same. The shift register 12a receives the signal s2 and the clock pulse CP2, the latch 12b reads the output of the stage in response to the clock pulse CP1, and the output and the polarity signal M And an output stage 12d for generating a data output Di according to the output of the exclusive NOR gate 12c.

The drive voltage circuit 13 is shown by a switch circuit instead of an actual transistor circuit in order to avoid complexity in the figure.
This corresponds to the case where the polarity signal M received via a is low. As can be seen, when the polarity signal M is low, the voltages Vp and V4 are applied to the output stage 11d of the scan drive circuit 11, and the voltages V3 and Vn are applied to the output stage 12d of the data drive circuit 12, respectively. Output stage of scan drive circuit 11 when high
The voltages V1 and Vn are supplied to 11d, and the voltages Vp and V2 are supplied to the output stage 12d of the data drive circuit 12, respectively. Note that Vp, V1, and V2 are positive voltages, and V3, V4, and Vn are negative voltages.

Next, a configuration example and an operation example of the switching circuit 60 will be described with reference to FIG. The switching signal Sw received by the switching terminal Ts on the lower side of the figure designates a normal state when it is low and a test state when it is high. The designation signals S1 to S3 received by the test terminals T1 to T3 in the test state are used to designate a test mode described later. In this embodiment, the number of designated signals is four because the number of modes is four. Since it is necessary to output three signals of the clock pulses CP1 and CP2 and the polarity clock pulse MP from the test terminals T1 to T3, in this embodiment, the test terminal T1 has the same designation as the switching signal Sw in order to simplify the circuit. signal
S1 shall be given. As a result, test terminals T1 to
Since all the circuits related to T3 have the same configuration, only the part related to the switching terminal Ts and the test terminal T1 will be described.

Inverters 61 and 62 are sequentially connected to the switching terminal Ts, and a complementary signal of the switching signal Sw by the inverter 61 is given to the lower input of the NOR gate 63 and the lower input of the clocked inverter 64. Switching signal Sw by 62
Is applied to the upper input of the clocked inverter 64. The designated signal S1 is supplied to the upper input of the NOR gate 63 from the test terminal T1 via the inverter 63a.
Clock pulse CP1 is an inverter for 64 clock inputs
64a. In the normal state where the switching signal SW is low, the NOR gate 63 is disabled by receiving high at the lower input, but the clocked inverter 64 is enabled by receiving high at the lower input and low at the upper input. Therefore, the output clock pulse CP1 is
Given to T1. When the switching signal SW is in the high test state, the clocked inverter 64 is disabled and the NOR gate 63 is enabled, so that the designation signal S1 received at the test terminal T1 is output from the NOR gate 63.

As can be seen from the above, the switching circuit 60 of FIG.
In the normal state where the switching signal Sw received at the switching terminal Ts is low, the clock pulses CP from the test terminals T1, T2 and T3 respectively.
1 and a clock pulse CP2 and a polarity clock pulse MP, and in the test state where the switching signal Sw is high, the test terminals T1 to T1
The designation signals S1 to S3 received by T3 are output to the scan selection circuit 40, the data selection circuit 20, and the polarity selection circuit 30 of the state selection circuit 50, respectively. As described above, in the switching circuit 60, the switching signal Sw
Clock pulse CP only when the normal state is specified by
1, CP2, MP are transmitted to the test terminals T1 to T3 by, for example, the clocked inverter 64, and the designation signals S1 to S3 received at the test terminals T1 to T3 only when the test state is designated are transmitted to the state selection circuit 50 by the NOR gate 63, for example. It is good to transmit to.

Returning to FIG. 1, the overall operation will be described. When the switching signal Sw is low, that is, when no signal is given to the switching terminal Ts,
Since the designation signal S1 from the switching circuit 60 is low, the state selection circuit 50 uses the signals sl and s2, the polarity signal M as the clock pulse CP1, the display data D, and the polarity clock pulse MP as the operation drive circuit 11 and the data drive circuit 12, To the drive voltage circuit 13, thereby entering a normal state, that is, a normal operation state in which a normal display based on the display data D is performed on the display panel 1, and at the same time, a clock is applied from the switching circuit 60 to the test terminals T1 to T3. Pulses CP1 and CP2 and polarity clock pulse MP
Is given. At this time, display data D is supplied to the data terminal Td from the last stage of the shift register 12a of the data drive circuit 12 via the amplifier circuit 18.

When a high switching signal Sw is given to the switching terminal Ts, the designated signals S1 to S3 received at the test terminals T1 to T3 are switched to the switching circuit.
The output signal 60 is given to the state selection circuit 50, the output signal s2 of the data selection circuit 20, the polarity signal M output by the polarity selection circuit 30, and the output signal s1 of the scan selection circuit 40 are designated by the designation signal S1.
The test state is fixed after being fixed to a logical value determined by a combination of S3. In this embodiment, as described above, the designated signal
Four test modes are designated by a combination of low and high of the designation signals S2 and S3 while keeping S1 high. At the time of this test, for example, instead of the display panel 1, a digital measuring device with a scanner
And the data drive circuit 12, and accurately measures a voltage value fixed in accordance with the combination of the designated signals S2 and S3 of the scan output Sj and the data output Di. Hereinafter, the four test modes in such a test state will be sequentially described.

In the first mode of the test, the designation is performed in a state where both the designation signals S2 and S3 are low. As described above, when the designation signal S1 is high, the selection circuits 20 and 30 output the complementary signal of the designation signal S2,
Since the selection circuit 40 outputs complementary signals of the designation signal S3, the polarity signals M of the signals s1 and s2 output from the state selection circuit 50 are both high. As can be seen from FIG. 3, when the polarity signal M is high, the drive voltage circuit 13 is switched to the scan drive circuit.
The output stage 11d receives the voltages V1 and Vn at its output stage 11d, but the exclusive NOR gate 11c receives the high from the shift register 11a and the low by the inverter of the polarity signal M and its output becomes low. Output stage 11 that is an inverter
The scan output Sj of d is fixed to the higher voltage V1. In the data drive circuit 12, the output stage 12d receives the voltages Vp and V2, but since the output of the exclusive NOR gate 12c becomes high, the data output Di of the output stage 12d becomes the lower voltage.
Fixed to V2. Thus, in the first mode, the scan output Sj
Is fixed to the voltage V1, and the data output Di is fixed to the voltage V2.

In the second mode, the high level of the designation signal S2 and the designation signal
Specify with S3 row. At this time, the signals s1 and s2 by the state selection circuit 50 go low, and the polarity signal M goes high. The voltage applied to the output stage 11d of the scan drive circuit 11 and the output stage 12d of the data drive circuit 12 due to the high polarity signal M is the same as in the first mode, but in the scan drive circuit 11, the exclusive NOR gate 11c is connected to the shift register. Since the output is made high by receiving the low from 11a, the scan output Sj of the output stage 11d is fixed to the lower voltage Vn, and the exclusive NOR gate 12c of the data drive circuit 12 receives the low from the latch 12b. Therefore, the data output Di of the output stage 12d is fixed to the higher voltage Vp. Therefore, in the second mode, the scan output Sj is fixed to the voltage Vn, and the data output Di is fixed to the voltage Vp.

The third mode is a low level of the designation signal S2 and a designation signal.
Specified by S3 high. At this time, the signals s1 and s2 by the state selection circuit 50 are high, and the polarity signal M is low. As can be seen from FIG. 3, the output stage 11d of the scan drive circuit 11 applies the voltages Vp and V4 to the output stage 1 of the data drive circuit 12 in response to the low level of the polarity signal M.
2d is supplied with the voltages V3 and Vn from the drive voltage circuit 13, respectively. Also, since the high and low of the signals s1 and s2 and the polarity signal M are opposite to those of the second mode, the exclusive NOR gate 11c
And the outputs of 12c go high and low as in the second mode,
The scan output Sj of the scan drive circuit 11 is fixed to the lower voltage V4, and the data output Di of the data drive circuit 12 is fixed to the higher voltage V3.

In the fourth mode, both the designation signal S2 and the designation signal S3 are designated as high. In this case, the output signals s1 and s2 of the state selection circuit 50 and the polarity signal M are all low.
Since the polarity signal M is low as in the third mode, the scanning drive circuit
The voltages received by the output stage 11d of the data drive circuit 11 and the output stage 12d of the data drive circuit 12 are the same as those in the previous mode, but the outputs of the exclusive NOR gates 11c and 12c are opposite to those in the third mode. Is fixed to the higher voltage Vp, and the data output Di is fixed to the lower voltage Vn.

Finally, an application example of the integrated circuit of the present invention will be described with reference to FIG. The integrated circuit 10 of the embodiment of FIG. 1 can drive the display panel 1 by itself. That is, the integrated circuit 10 of FIG. 1 shown in the left half of FIG. 2 has a function of generating display data, and is capable of driving each pixel Pij of the display panel 1 by outputting a plurality of data outputs Di and scanning outputs Sj. According to the recent high integration technology, the display driving integrated circuit can be integrated in a chip of several mm square unless the display panel 1 has a large size or a high gradation display. However, in the example of FIG. 2, since the display panel 1 is horizontally long and the number of data lines 1b is large, it is necessary to share and drive them by a plurality of integrated circuits. In order to drive the right half of the display panel 1 in FIG. Another integrated circuit 10a is used.

When a plurality of integrated circuits are used for driving the display panel, it is necessary to accurately distribute the display data D to each of the integrated circuits and to align the generation timing of the data output Di and the like. In the example of FIG. The transmission of the display data D from the circuit 10 to the other integrated circuit 10a is normally performed via the data terminal Td, but the transmission of the clock pulses CP1 and CP2 and the polarity clock pulse MP is performed as described above. Use ~ T3. Since the integrated circuit 10a receiving the transmission is on the driven side with respect to the integrated circuit 10, the clock circuit 14, ROM 15,
Since the RAM 16 and the data conversion circuit 17 are unnecessary, and in the example of FIG. 2, the scanning line 1a of the display panel 1 is also driven by the integrated circuit 10, the scanning drive circuit 11 and the operation selection circuit 40 are also unnecessary, and the data terminal Td The data driving circuit 12 reads the display data D inputted to the data driving circuit 12 in synchronization with the clock pulse CP2, and generates the data output Di in synchronization with the clock pulses CP1 and MP. Further, both the integrated circuits 10 and 10a are connected to the display panel 1 as shown in the drawing to perform a display test by supplying a switching signal Sw and a designation signal S1 to S3 to a switching terminal Ts and test terminals T1 to T3, respectively. Alternatively, the test can be performed individually by connecting to a measuring device as described above.

The present invention can be embodied in various modes without being limited to the embodiments and application examples described above. For example, in the embodiment, four test modes are used, but eight test modes can be set only by sharing the output terminal of three types of clock pulses with the test terminal. The switching terminal does not need to be particularly provided for the present invention, and can be shared with a terminal not used at the time of the test, for example, a data terminal. Further, it is not necessary to incorporate all the circuits of FIG. 1 into the integrated circuit of the present invention. Not only the display data generating function but also the clock generating function, the scan driving function, and the scanning function as in the other integrated circuit 10a of FIG. The selection function and the like can be omitted as appropriate. Further, the specific circuit configurations of the state selection circuit and the switching circuit shown in FIGS. 3 and 4 are merely examples, and an appropriate circuit configuration is possible within the gist of the present invention as the case may be or when necessary.

[0032]

As described above, in the integrated circuit for driving a display panel according to the present invention, the state selection circuit for switching the operation state of the integrated circuit between the normal state based on the display data and the test state based on the test content designating signal, and the designating signal A test terminal to be input, a switch terminal to input a switch signal for designating a normal state or a test state, and a normal state is designated by the switch signal in response to the switch signal, the designation signal, and the clock pulse for driving the display panel. And a switching circuit for supplying a designated signal to the state selection circuit when the test state is designated.The test is performed by the designated signal input to the test terminal in the test state. By enabling clock pulses to be output from terminals to other integrated circuits, the number of integrated circuit terminals and the chip area required for terminals can be minimized. For example, it is possible to improve the economical efficiency by reducing the chip size of the display panel driver IC.

The integrated circuit according to the present invention is particularly suitable when all circuits related to driving a relatively small display panel are integrated in one chip. By implementing the present invention, the effect of chip reduction by high integration is fully utilized. Economic efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is an overall block circuit diagram showing an embodiment of a display panel driving integrated circuit of the present invention together with a display panel.

FIG. 2 is a circuit diagram showing a manner of driving a display panel by a plurality of integrated circuits as an application example of the integrated circuit of the present invention.

FIG. 3 is a circuit diagram showing a specific configuration example of a circuit excluding a switching circuit of the integrated circuit of FIG. 1;

FIG. 4 is a circuit diagram showing a specific configuration example of a switching circuit of the integrated circuit of FIG. 1;

FIG. 5 is a block circuit diagram showing a conventional method of driving a display panel.

[Explanation of symbols]

 1 display panel 10 integrated circuit 10a other integrated circuit 11 scan drive circuit 12 data drive circuit 13 drive voltage circuit 14 clock circuit 20 data select circuit 30 polarity select circuit 40 scan select circuit 50 state select circuit 60 switching circuit CP1 clock pulse CP2 clock Pulse D Display data Di Data output MP Polarity clock pulse Sj Scan output Sw switching signal S1 specified signal S2 specified signal S3 specified signal Ts switching terminal T1 test terminal T2 test terminal T3 test terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G01R 31/28-31/30 G02F 1/133 505-580

Claims (3)

(57) [Claims] 1. An integrated circuit comprising a test means and capable of driving a display panel together with another integrated circuit, wherein an operation state of the integrated circuit is switched between a normal state based on display data and a test state specified by a test content designating signal. A selection circuit, a test terminal for inputting a designation signal, a switching terminal for inputting a switching signal for designating a normal state or a test state, a switching signal, a designation signal, and a clock pulse for driving a display panel generated internally. A switching circuit for supplying a clock pulse to the test terminal when the normal state is specified by the switching signal and a specifying signal to the state selection circuit when the test state is specified. Display in which a test pulse is output from a test terminal in a normal state and given to another integrated circuit in a normal state. Panel driving integrated circuit. 2. The circuit according to claim 1, wherein a plurality of test terminals are provided so that a designation signal of a test content of a plurality of modes can be inputted when a test state is designated by a switching signal to the switching circuit. An integrated circuit for driving a display panel, wherein a plurality of clock pulses are output from the plurality of test terminals when a normal state is designated. 3. A circuit according to claim 1, wherein the switching circuit supplies a signal from the test terminal to the state selection circuit only when a test state is specified by the switching signal, and a clock only when the normal state is specified. An integrated circuit for driving a display panel, comprising: means for applying a pulse to a test terminal.